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freedreno/a6xx: Also FLUSH_CACHE on image barrier

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For the same reason we need to on an UPDATE_BUFFER barrier.  Fixes
KHR-GLES31.core.compute_shader.pipeline-post-fs once the hard-coded
cache-flush is removed from launch_grid path.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20975>
This commit is contained in:
Rob Clark 2023-01-29 08:27:05 -08:00 • committed by Marge Bot
parent 23e65c6084
commit 9b22bdc956
1 changed files with 1 additions and 1 deletions
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src/gallium/drivers/freedreno/a6xx/fd6_barrier.c
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@ -177,7 +177,6 @@ fd6_memory_barrier(struct pipe_context *pctx, unsigned flags)
unsigned flushes = 0;
if (flags & (PIPE_BARRIER_SHADER_BUFFER |
PIPE_BARRIER_IMAGE |
PIPE_BARRIER_CONSTANT_BUFFER |
PIPE_BARRIER_VERTEX_BUFFER |
PIPE_BARRIER_INDEX_BUFFER |
@ -186,6 +185,7 @@ fd6_memory_barrier(struct pipe_context *pctx, unsigned flags)
}
if (flags & (PIPE_BARRIER_TEXTURE |
PIPE_BARRIER_IMAGE |
PIPE_BARRIER_INDIRECT_BUFFER |
PIPE_BARRIER_UPDATE_BUFFER |
PIPE_BARRIER_UPDATE_TEXTURE)) {