From 9abbcbc00ed6133c67977bf4a2d7e55d2d407a41 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Daniel=20Sch=C3=BCrmann?= Date: Thu, 2 Oct 2025 17:32:35 +0200 Subject: [PATCH] nir/opt_load_store_vectorize: don't add negative offsets to load/store_shared2_amd By hoisting the low address instead, we can make use of these instructions on GFX6. Totals from 3 (0.00% of 79839) affected shaders: (Navi48) Instrs: 3768 -> 3776 (+0.21%); split: -0.03%, +0.24% CodeSize: 20024 -> 20048 (+0.12%); split: -0.04%, +0.16% Latency: 16093 -> 16198 (+0.65%) InvThroughput: 3868 -> 3864 (-0.10%) VClause: 97 -> 93 (-4.12%) VALU: 2333 -> 2331 (-0.09%) Part-of: --- src/compiler/nir/nir_opt_load_store_vectorize.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/src/compiler/nir/nir_opt_load_store_vectorize.c b/src/compiler/nir/nir_opt_load_store_vectorize.c index a07ec690cce..e24091fe8f6 100644 --- a/src/compiler/nir/nir_opt_load_store_vectorize.c +++ b/src/compiler/nir/nir_opt_load_store_vectorize.c @@ -1536,14 +1536,14 @@ try_vectorize_shared2(struct vectorize_ctx *ctx, return false; } - /* vectorize the accesses */ - nir_builder b = nir_builder_at(nir_after_instr(first->is_store ? second->instr : first->instr)); - - nir_def *offset = first->intrin->src[first->is_store].ssa; - offset = nir_iadd_imm(&b, offset, nir_intrinsic_base(first->intrin)); + /* Take low as base address. */ + nir_def *offset = low->intrin->src[first->is_store].ssa; if (first != low) - offset = nir_iadd_imm(&b, offset, -(int)diff); + hoist_base_addr(&first->intrin->instr, offset->parent_instr); + nir_builder b = nir_builder_at(nir_after_instr(first->is_store ? second->instr : first->instr)); + offset = nir_iadd_imm(&b, offset, nir_intrinsic_base(low->intrin)); + /* vectorize the accesses */ uint32_t access = nir_intrinsic_access(first->intrin); if (first->is_store) { nir_def *low_val = low->intrin->src[low->info->value_src].ssa;