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nir: add shader_info::disable_input/output_offset_src_constant_folding

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and set it where needed to prevent nir_opt_constant_folding from breaking
those drivers.

Acked-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38277>
This commit is contained in:
Marek Olšák 2025-11-21 12:11:25 -05:00 • committed by Marge Bot
parent 7330bca9db
commit 9a56672f56
5 changed files with 13 additions and 0 deletions
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3
src/broadcom/compiler/vir.c
View file

@ -1040,6 +1040,7 @@ v3d_nir_lower_vs_early(struct v3d_compile *c)
NIR_PASS(_, c->s, nir_lower_io, nir_var_shader_in | nir_var_shader_out,
type_size_vec4,
(nir_lower_io_options)0);
c->s->info.disable_output_offset_src_constant_folding = true;
/* For geometry stages using the same segment for inputs and outputs
* we need to read all inputs before writing any output. If we switch
@ -1082,6 +1083,8 @@ v3d_nir_lower_gs_early(struct v3d_compile *c)
NIR_PASS(_, c->s, nir_lower_io, nir_var_shader_in | nir_var_shader_out,
type_size_vec4,
(nir_lower_io_options)0);
c->s->info.disable_output_offset_src_constant_folding = true;
/* clean up nir_lower_io's deref_var remains and do a constant folding pass
* on the code it generated.
*/

6
src/compiler/shader_info.h
View file

@ -244,6 +244,12 @@ typedef struct shader_info {
/* Whether flrp has been lowered. */
bool flrp_lowered:1;
/* Whether nir_opt_constant_folding should not fold offset srcs of
* IO intrinsics.
*/
bool disable_input_offset_src_constant_folding:1;
bool disable_output_offset_src_constant_folding:1;
/* Whether nir_lower_io has been called to lower derefs.
* nir_variables for inputs and outputs might not be present in the IR.
*/

1
src/gallium/drivers/vc4/vc4_program.c
View file

@ -2514,6 +2514,7 @@ vc4_shader_state_create(struct pipe_context *pctx,
NIR_PASS(_, s, nir_lower_io,
nir_var_shader_in | nir_var_shader_out | nir_var_uniform,
type_size, (nir_lower_io_options)0);
s->info.disable_output_offset_src_constant_folding = true;
NIR_PASS(_, s, nir_normalize_cubemap_coords);

1
src/intel/compiler/brw/brw_nir.c
View file

@ -1165,6 +1165,7 @@ brw_nir_lower_fs_outputs(nir_shader *nir)
}
NIR_PASS(_, nir, nir_lower_io, nir_var_shader_out, type_size_vec4, 0);
nir->info.disable_output_offset_src_constant_folding = true;
}
static bool

2
src/microsoft/compiler/nir_to_dxil.c
View file

@ -6636,6 +6636,8 @@ nir_to_dxil(struct nir_shader *s, const struct nir_to_dxil_options *opts,
NIR_PASS(_, s, nir_lower_frexp);
NIR_PASS(_, s, nir_lower_flrp, 16 | 32 | 64, true);
NIR_PASS(_, s, nir_lower_io, nir_var_shader_in | nir_var_shader_out, type_size_vec4, nir_lower_io_lower_64bit_to_32);
s->info.disable_input_offset_src_constant_folding = true;
s->info.disable_output_offset_src_constant_folding = true;
NIR_PASS(_, s, dxil_nir_ensure_position_writes);
NIR_PASS(_, s, dxil_nir_lower_system_values);
NIR_PASS(_, s, nir_lower_io_to_scalar, nir_var_shader_in | nir_var_system_value | nir_var_shader_out, NULL, NULL);