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i965: Refactor Sandybridge implied move handling.
This was open-coded in three different places, and more are necessary. Extract this into a function so it can be reused. Unfortunately, not all variations were the same: in particular, one set compression control and checked that the source register was not ARF_NULL. This seemed like a good idea, so all cases now do so.
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1 changed files with 32 additions and 36 deletions
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@ -52,6 +52,35 @@ static void guess_execution_size(struct brw_compile *p,
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}
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}
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/**
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* Prior to Sandybridge, the SEND instruction accepted non-MRF source
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* registers, implicitly moving the operand to a message register.
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*
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* On Sandybridge, this is no longer the case. This function performs the
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* explicit move; it should be called before emitting a SEND instruction.
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*/
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static void
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gen6_resolve_implied_move(struct brw_compile *p,
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struct brw_reg *src,
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GLuint msg_reg_nr)
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{
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struct intel_context *intel = &p->brw->intel;
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if (intel->gen != 6)
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return;
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if (src->file == BRW_ARCHITECTURE_REGISTER_FILE && src->nr == BRW_ARF_NULL)
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return;
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brw_push_insn_state(p);
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brw_set_mask_control(p, BRW_MASK_DISABLE);
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brw_set_compression_control(p, BRW_COMPRESSION_NONE);
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brw_MOV(p, retype(brw_message_reg(msg_reg_nr), BRW_REGISTER_TYPE_UD),
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retype(*src, BRW_REGISTER_TYPE_UD));
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brw_pop_insn_state(p);
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*src = brw_message_reg(msg_reg_nr);
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}
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static void brw_set_dest(struct brw_compile *p,
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static void brw_set_dest(struct brw_compile *p,
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struct brw_instruction *insn,
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struct brw_instruction *insn,
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struct brw_reg dest)
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struct brw_reg dest)
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@ -1966,20 +1995,7 @@ void brw_SAMPLE(struct brw_compile *p,
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{
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{
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struct brw_instruction *insn;
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struct brw_instruction *insn;
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/* Sandybridge doesn't have the implied move for SENDs,
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gen6_resolve_implied_move(p, &src0, msg_reg_nr);
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* and the first message register index comes from src0.
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*/
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if (intel->gen >= 6) {
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if (src0.file != BRW_ARCHITECTURE_REGISTER_FILE ||
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src0.nr != BRW_ARF_NULL) {
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brw_push_insn_state(p);
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brw_set_mask_control( p, BRW_MASK_DISABLE );
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brw_set_compression_control(p, BRW_COMPRESSION_NONE);
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brw_MOV(p, retype(brw_message_reg(msg_reg_nr), src0.type), src0);
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brw_pop_insn_state(p);
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}
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src0 = brw_message_reg(msg_reg_nr);
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}
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insn = next_insn(p, BRW_OPCODE_SEND);
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insn = next_insn(p, BRW_OPCODE_SEND);
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insn->header.predicate_control = 0; /* XXX */
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insn->header.predicate_control = 0; /* XXX */
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@ -2034,17 +2050,7 @@ void brw_urb_WRITE(struct brw_compile *p,
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struct intel_context *intel = &p->brw->intel;
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struct intel_context *intel = &p->brw->intel;
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struct brw_instruction *insn;
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struct brw_instruction *insn;
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/* Sandybridge doesn't have the implied move for SENDs,
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gen6_resolve_implied_move(p, &src0, msg_reg_nr);
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* and the first message register index comes from src0.
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*/
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if (intel->gen >= 6) {
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brw_push_insn_state(p);
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brw_set_mask_control( p, BRW_MASK_DISABLE );
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brw_MOV(p, retype(brw_message_reg(msg_reg_nr), BRW_REGISTER_TYPE_UD),
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retype(src0, BRW_REGISTER_TYPE_UD));
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brw_pop_insn_state(p);
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src0 = brw_message_reg(msg_reg_nr);
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}
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insn = next_insn(p, BRW_OPCODE_SEND);
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insn = next_insn(p, BRW_OPCODE_SEND);
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@ -2154,17 +2160,7 @@ void brw_ff_sync(struct brw_compile *p,
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struct intel_context *intel = &p->brw->intel;
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struct intel_context *intel = &p->brw->intel;
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struct brw_instruction *insn;
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struct brw_instruction *insn;
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/* Sandybridge doesn't have the implied move for SENDs,
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gen6_resolve_implied_move(p, &src0, msg_reg_nr);
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* and the first message register index comes from src0.
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*/
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if (intel->gen >= 6) {
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brw_push_insn_state(p);
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brw_set_mask_control( p, BRW_MASK_DISABLE );
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brw_MOV(p, retype(brw_message_reg(msg_reg_nr), BRW_REGISTER_TYPE_UD),
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retype(src0, BRW_REGISTER_TYPE_UD));
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brw_pop_insn_state(p);
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src0 = brw_message_reg(msg_reg_nr);
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}
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insn = next_insn(p, BRW_OPCODE_SEND);
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insn = next_insn(p, BRW_OPCODE_SEND);
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brw_set_dest(p, insn, dest);
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brw_set_dest(p, insn, dest);
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