diff --git a/src/intel/compiler/brw_eu.c b/src/intel/compiler/brw_eu.c
index e89d8bc1d31..efc37665bcd 100644
--- a/src/intel/compiler/brw_eu.c
+++ b/src/intel/compiler/brw_eu.c
@@ -206,43 +206,6 @@ brw_set_default_compression_control(struct brw_codegen *p,
    default:
       unreachable("not reached");
    }
-
-   if (p->devinfo->ver <= 6) {
-      p->current->compressed =
-         (compression_control == BRW_COMPRESSION_COMPRESSED);
-   }
-}
-
-/**
- * Enable or disable instruction compression on the given instruction leaving
- * the currently selected channel enable group untouched.
- */
-void
-brw_inst_set_compression(const struct intel_device_info *devinfo,
-                         brw_inst *inst, bool on)
-{
-   if (devinfo->ver >= 6) {
-      /* No-op, the EU will figure out for us whether the instruction needs to
-       * be compressed.
-       */
-   } else {
-      /* The channel group and compression controls are non-orthogonal, there
-       * are two possible representations for uncompressed instructions and we
-       * may need to preserve the current one to avoid changing the selected
-       * channel group inadvertently.
-       */
-      if (on)
-         brw_inst_set_qtr_control(devinfo, inst, BRW_COMPRESSION_COMPRESSED);
-      else if (brw_inst_qtr_control(devinfo, inst)
-               == BRW_COMPRESSION_COMPRESSED)
-         brw_inst_set_qtr_control(devinfo, inst, BRW_COMPRESSION_NONE);
-   }
-}
-
-void
-brw_set_default_compression(struct brw_codegen *p, bool on)
-{
-   p->current->compressed = on;
 }
 
 /**
diff --git a/src/intel/compiler/brw_eu.h b/src/intel/compiler/brw_eu.h
index 1148ad2af56..b37c6e8ea76 100644
--- a/src/intel/compiler/brw_eu.h
+++ b/src/intel/compiler/brw_eu.h
@@ -58,9 +58,6 @@ struct brw_insn_state {
    /* Group in units of channels */
    unsigned group:5;
 
-   /* Compression control on gfx4-5 */
-   bool compressed:1;
-
    /* One of BRW_MASK_* */
    unsigned mask_control:1;
 
@@ -162,9 +159,6 @@ void brw_set_default_exec_size(struct brw_codegen *p, unsigned value);
 void brw_set_default_mask_control( struct brw_codegen *p, unsigned value );
 void brw_set_default_saturate( struct brw_codegen *p, bool enable );
 void brw_set_default_access_mode( struct brw_codegen *p, unsigned access_mode );
-void brw_inst_set_compression(const struct intel_device_info *devinfo,
-                              brw_inst *inst, bool on);
-void brw_set_default_compression(struct brw_codegen *p, bool on);
 void brw_inst_set_group(const struct intel_device_info *devinfo,
                         brw_inst *inst, unsigned group);
 void brw_set_default_group(struct brw_codegen *p, unsigned group);
diff --git a/src/intel/compiler/brw_eu_emit.c b/src/intel/compiler/brw_eu_emit.c
index b98a6438d07..c5ae26f67ad 100644
--- a/src/intel/compiler/brw_eu_emit.c
+++ b/src/intel/compiler/brw_eu_emit.c
@@ -544,7 +544,6 @@ brw_inst_set_state(const struct brw_isa_info *isa,
 
    brw_inst_set_exec_size(devinfo, insn, state->exec_size);
    brw_inst_set_group(devinfo, insn, state->group);
-   brw_inst_set_compression(devinfo, insn, state->compressed);
    brw_inst_set_access_mode(devinfo, insn, state->access_mode);
    brw_inst_set_mask_control(devinfo, insn, state->mask_control);
    if (devinfo->ver >= 12)
@@ -1724,7 +1723,6 @@ void brw_oword_block_write_scratch(struct brw_codegen *p,
 					 BRW_REGISTER_TYPE_UW);
 
       brw_inst_set_sfid(devinfo, insn, target_cache);
-      brw_inst_set_compression(devinfo, insn, false);
 
       if (brw_inst_exec_size(devinfo, insn) >= 16)
 	 src_header = vec16(src_header);
@@ -1813,7 +1811,6 @@ brw_oword_block_read_scratch(struct brw_codegen *p,
 
       brw_inst_set_sfid(devinfo, insn, target_cache);
       assert(brw_inst_pred_control(devinfo, insn) == 0);
-      brw_inst_set_compression(devinfo, insn, false);
 
       brw_set_dest(p, insn, dest);	/* UW? */
       brw_set_src0(p, insn, mrf);
diff --git a/src/intel/compiler/brw_fs_generator.cpp b/src/intel/compiler/brw_fs_generator.cpp
index 79dad3b45a0..3f7e671a122 100644
--- a/src/intel/compiler/brw_fs_generator.cpp
+++ b/src/intel/compiler/brw_fs_generator.cpp
@@ -811,7 +811,6 @@ fs_generator::generate_scratch_write(fs_inst *inst, struct brw_reg src)
 
    brw_push_insn_state(p);
    brw_set_default_exec_size(p, cvt(lower_size) - 1);
-   brw_set_default_compression(p, lower_size > 8);
 
    for (unsigned i = 0; i < inst->exec_size / lower_size; i++) {
       brw_set_default_group(p, inst->group + lower_size * i);
@@ -969,7 +968,6 @@ fs_generator::generate_set_sample_id(fs_inst *inst,
                                suboffset(reg, i * lower_size / 4));
       brw_inst_set_exec_size(devinfo, insn, cvt(lower_size) - 1);
       brw_inst_set_group(devinfo, insn, inst->group + lower_size * i);
-      brw_inst_set_compression(devinfo, insn, lower_size > 8);
       brw_set_default_swsb(p, tgl_swsb_null());
    }
 }
@@ -1104,7 +1102,6 @@ fs_generator::generate_code(const cfg_t *cfg, int dispatch_width,
        */
       const bool compressed =
            inst->dst.component_size(inst->exec_size) > REG_SIZE;
-      brw_set_default_compression(p, compressed);
 
       if (devinfo->ver >= 20 && inst->group % 8 != 0) {
          assert(inst->force_writemask_all);