diff --git a/src/amd/vpelib/inc/vpe_types.h b/src/amd/vpelib/inc/vpe_types.h index d16415f35f8..540e6d48b44 100644 --- a/src/amd/vpelib/inc/vpe_types.h +++ b/src/amd/vpelib/inc/vpe_types.h @@ -131,6 +131,7 @@ enum vpe_ip_level { VPE_IP_LEVEL_1_0, /**< vpe 1.0 */ VPE_IP_LEVEL_1_1, /**< vpe 1.1 */ VPE_IP_LEVEL_2_0, /**< vpe 2.0 */ + VPE_IP_LEVEL_2_2, /**< vpe 2.2 */ }; enum vpe_mps_mode { diff --git a/src/amd/vpelib/meson.build b/src/amd/vpelib/meson.build index 73e17a86b45..4a8232c4595 100644 --- a/src/amd/vpelib/meson.build +++ b/src/amd/vpelib/meson.build @@ -25,6 +25,7 @@ c_args_vpe += [ '-DVPE_BUILD_1_X', '-DVPE_BUILD_1_1', '-DVPE_BUILD_2_0', + '-DVPE_BUILD_2_2', ] vpe_files = files( @@ -142,6 +143,8 @@ vpe_files = files( 'src/chip/vpe20/vpe20_plane_desc_writer.c', 'src/chip/vpe20/vpe20_resource.c', 'src/chip/vpe20/vpe20_vpe_desc_writer.c', + 'src/chip/vpe22/inc/vpe22_resource.h', + 'src/chip/vpe22/vpe22_resource.c', 'src/imported/SPL/dc_spl.c', 'src/imported/SPL/dc_spl.h', 'src/imported/SPL/dc_spl_filters.c', @@ -161,6 +164,7 @@ inc_amd_vpe = include_directories( 'src/chip/vpe10/inc', 'src/chip/vpe11/inc', 'src/chip/vpe20/inc', + 'src/chip/vpe22/inc', 'src/imported/SPL', 'src/imported', ) diff --git a/src/amd/vpelib/src/chip/vpe20/vpe20_cdc_fe.c b/src/amd/vpelib/src/chip/vpe20/vpe20_cdc_fe.c index 56b468f1beb..d219c09544b 100644 --- a/src/amd/vpelib/src/chip/vpe20/vpe20_cdc_fe.c +++ b/src/amd/vpelib/src/chip/vpe20/vpe20_cdc_fe.c @@ -107,7 +107,8 @@ void vpe20_cdc_program_crossbar_config(struct cdc_fe *cdc_fe, enum vpe_surface_p format == VPE_SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616 || format == VPE_SURFACE_PIXEL_FORMAT_GRPH_BGRA16161616_UNORM || format == VPE_SURFACE_PIXEL_FORMAT_GRPH_BGRA16161616_SNORM || - format == VPE_SURFACE_PIXEL_FORMAT_VIDEO_AYCbCr8888) { + format == VPE_SURFACE_PIXEL_FORMAT_VIDEO_AYCbCr8888 || + format == VPE_SURFACE_PIXEL_FORMAT_GRPH_RGBE) { red_bar = MUX_SEL_CB_B; blue_bar = MUX_SEL_CR_R; } diff --git a/src/amd/vpelib/src/chip/vpe20/vpe20_dpp.c b/src/amd/vpelib/src/chip/vpe20/vpe20_dpp.c index 01f24707b9a..8d42c0a9a0d 100644 --- a/src/amd/vpelib/src/chip/vpe20/vpe20_dpp.c +++ b/src/amd/vpelib/src/chip/vpe20/vpe20_dpp.c @@ -330,6 +330,10 @@ void vpe20_dpp_program_cnv( case VPE_SURFACE_PIXEL_FORMAT_VIDEO_CrYCbA1010102: /* Y410 */ pixel_format = 115; break; + case VPE_SURFACE_PIXEL_FORMAT_GRPH_RGBE: + pixel_format = 116; + alpha_en = 0; + break; case VPE_SURFACE_PIXEL_FORMAT_GRPH_R8: // use crossbar pixel_format = 120; alpha_en = 0; @@ -343,6 +347,7 @@ void vpe20_dpp_program_cnv( } REG_SET(VPCNVC_SURFACE_PIXEL_FORMAT, 0, VPCNVC_SURFACE_PIXEL_FORMAT, pixel_format); + // RGBE default set VPCNVC_FORMAT_CROSSBAR_R/G/B to 0x0/0x1/0x2 REG_SET_7(VPCNVC_FORMAT_CONTROL, REG_DEFAULT(VPCNVC_FORMAT_CONTROL), FORMAT_EXPANSION_MODE, hw_expansion_mode, FORMAT_CNV16, 0, FORMAT_CONTROL__ALPHA_EN, alpha_en, VPCNVC_BYPASS, dpp->vpe_priv->init.debug.vpcnvc_bypass, VPCNVC_BYPASS_MSB_ALIGN, 0, CLAMP_POSITIVE, 0, diff --git a/src/amd/vpelib/src/chip/vpe20/vpe20_resource.c b/src/amd/vpelib/src/chip/vpe20/vpe20_resource.c index 059c668ee03..b3f90e10405 100644 --- a/src/amd/vpelib/src/chip/vpe20/vpe20_resource.c +++ b/src/amd/vpelib/src/chip/vpe20/vpe20_resource.c @@ -2538,6 +2538,8 @@ uint32_t vpe20_get_hw_surface_format(enum vpe_surface_pixel_format format) surf_format = 298; break; case VPE_SURFACE_PIXEL_FORMAT_GRPH_RGBE: + surf_format = 116; + break; default: VPE_ASSERT("Invalid pixel format"); break; diff --git a/src/amd/vpelib/src/chip/vpe22/inc/asic/chip_default.h b/src/amd/vpelib/src/chip/vpe22/inc/asic/chip_default.h new file mode 100644 index 00000000000..dec8a6fdf07 --- /dev/null +++ b/src/amd/vpelib/src/chip/vpe22/inc/asic/chip_default.h @@ -0,0 +1,1464 @@ +// Copyright (c) 1994 - 2025 Advanced Micro Devices, Inc. All rights reserved. + +/* + * chip_default.h + * + * Register Spec Release: + * + * + * (c) 2021 Advanced Micro Devices, Inc. (unpublished) + * + * All rights reserved. This notice is intended as a precaution against + * inadvertent publication and does not imply publication or any waiver + * of confidentiality. The year included in the foregoing notice is the + * year of creation of the work. + * + */ + +#ifndef _vpe22_chip_DEFAULT_HEADER +#define _vpe22_chip_DEFAULT_HEADER + +// Registers from CDC block + +#define mmVPEP_MGCG_CNTL_DEFAULT 0x0000 +#define mmVPCDC_SOFT_RESET_DEFAULT 0x0000 +#define mmVPCDC_FE0_SURFACE_CONFIG_DEFAULT 0x0000 +#define mmVPCDC_FE0_CROSSBAR_CONFIG_DEFAULT 0x0000 +#define mmVPCDC_FE0_VIEWPORT_START_CONFIG_DEFAULT 0x0000 +#define mmVPCDC_FE0_VIEWPORT_DIMENSION_CONFIG_DEFAULT 0x0000 +#define mmVPCDC_FE0_VIEWPORT_START_C_CONFIG_DEFAULT 0x0000 +#define mmVPCDC_FE0_VIEWPORT_DIMENSION_C_CONFIG_DEFAULT 0x0000 +#define mmVPCDC_FE1_SURFACE_CONFIG_DEFAULT 0x0000 +#define mmVPCDC_FE1_CROSSBAR_CONFIG_DEFAULT 0x0000 +#define mmVPCDC_FE1_VIEWPORT_START_CONFIG_DEFAULT 0x0000 +#define mmVPCDC_FE1_VIEWPORT_DIMENSION_CONFIG_DEFAULT 0x0000 +#define mmVPCDC_FE1_VIEWPORT_START_C_CONFIG_DEFAULT 0x0000 +#define mmVPCDC_FE1_VIEWPORT_DIMENSION_C_CONFIG_DEFAULT 0x0000 +#define mmVPCDC_BE0_P2B_CONFIG_DEFAULT 0x0036 +#define mmVPCDC_BE0_GLOBAL_SYNC_CONFIG_DEFAULT 0x960F014 +#define mmVPCDC_BE1_P2B_CONFIG_DEFAULT 0x0036 +#define mmVPCDC_BE1_GLOBAL_SYNC_CONFIG_DEFAULT 0x960F014 +#define mmVPCDC_BE2_P2B_CONFIG_DEFAULT 0x0036 +#define mmVPCDC_BE2_GLOBAL_SYNC_CONFIG_DEFAULT 0x960F014 +#define mmVPCDC_BE3_P2B_CONFIG_DEFAULT 0x0036 +#define mmVPCDC_BE3_GLOBAL_SYNC_CONFIG_DEFAULT 0x960F014 +#define mmVPCDC_GLOBAL_SYNC_TRIGGER_DEFAULT 0x0000 +#define mmVPEP_MEM_GLOBAL_PWR_REQ_CNTL_DEFAULT 0x0000 +#define mmVPFE0_MEM_PWR_CNTL_DEFAULT 0x0000 +#define mmVPFE1_MEM_PWR_CNTL_DEFAULT 0x0000 +#define mmVPBE0_MEM_PWR_CNTL_DEFAULT 0x0000 +#define mmVPBE1_MEM_PWR_CNTL_DEFAULT 0x0000 +#define mmVPBE2_MEM_PWR_CNTL_DEFAULT 0x0000 +#define mmVPBE3_MEM_PWR_CNTL_DEFAULT 0x0000 +#define mmVPCDC_3DLUT_FL_CONFIG_DEFAULT 0x0127 +#define mmVPCDC_CONTROL_DEFAULT 0x0000 + +// Registers from VPCNVC_CFG block + +#define mmVPCNVC_CFG0_VPCNVC_SURFACE_PIXEL_FORMAT_DEFAULT 0x0008 +#define mmVPCNVC_CFG0_VPCNVC_SURFACE_PIXEL_FORMAT_DEFAULT 0x0008 +#define mmVPCNVC_CFG1_VPCNVC_SURFACE_PIXEL_FORMAT_DEFAULT 0x0008 +#define mmVPCNVC_CFG1_VPCNVC_SURFACE_PIXEL_FORMAT_DEFAULT 0x0008 +#define mmVPCNVC_CFG0_VPCNVC_FORMAT_CONTROL_DEFAULT 0x24000000 +#define mmVPCNVC_CFG0_VPCNVC_FORMAT_CONTROL_DEFAULT 0x24000000 +#define mmVPCNVC_CFG1_VPCNVC_FORMAT_CONTROL_DEFAULT 0x24000000 +#define mmVPCNVC_CFG1_VPCNVC_FORMAT_CONTROL_DEFAULT 0x24000000 +#define mmVPCNVC_CFG0_VPCNVC_FCNV_FP_BIAS_R_DEFAULT 0x0000 +#define mmVPCNVC_CFG0_VPCNVC_FCNV_FP_BIAS_R_DEFAULT 0x0000 +#define mmVPCNVC_CFG1_VPCNVC_FCNV_FP_BIAS_R_DEFAULT 0x0000 +#define mmVPCNVC_CFG1_VPCNVC_FCNV_FP_BIAS_R_DEFAULT 0x0000 +#define mmVPCNVC_CFG0_VPCNVC_FCNV_FP_BIAS_G_DEFAULT 0x0000 +#define mmVPCNVC_CFG0_VPCNVC_FCNV_FP_BIAS_G_DEFAULT 0x0000 +#define mmVPCNVC_CFG1_VPCNVC_FCNV_FP_BIAS_G_DEFAULT 0x0000 +#define mmVPCNVC_CFG1_VPCNVC_FCNV_FP_BIAS_G_DEFAULT 0x0000 +#define mmVPCNVC_CFG0_VPCNVC_FCNV_FP_BIAS_B_DEFAULT 0x0000 +#define mmVPCNVC_CFG0_VPCNVC_FCNV_FP_BIAS_B_DEFAULT 0x0000 +#define mmVPCNVC_CFG1_VPCNVC_FCNV_FP_BIAS_B_DEFAULT 0x0000 +#define mmVPCNVC_CFG1_VPCNVC_FCNV_FP_BIAS_B_DEFAULT 0x0000 +#define mmVPCNVC_CFG0_VPCNVC_FCNV_FP_SCALE_R_DEFAULT 0x1F000 +#define mmVPCNVC_CFG0_VPCNVC_FCNV_FP_SCALE_R_DEFAULT 0x1F000 +#define mmVPCNVC_CFG1_VPCNVC_FCNV_FP_SCALE_R_DEFAULT 0x1F000 +#define mmVPCNVC_CFG1_VPCNVC_FCNV_FP_SCALE_R_DEFAULT 0x1F000 +#define mmVPCNVC_CFG0_VPCNVC_FCNV_FP_SCALE_G_DEFAULT 0x1F000 +#define mmVPCNVC_CFG0_VPCNVC_FCNV_FP_SCALE_G_DEFAULT 0x1F000 +#define mmVPCNVC_CFG1_VPCNVC_FCNV_FP_SCALE_G_DEFAULT 0x1F000 +#define mmVPCNVC_CFG1_VPCNVC_FCNV_FP_SCALE_G_DEFAULT 0x1F000 +#define mmVPCNVC_CFG0_VPCNVC_FCNV_FP_SCALE_B_DEFAULT 0x1F000 +#define mmVPCNVC_CFG0_VPCNVC_FCNV_FP_SCALE_B_DEFAULT 0x1F000 +#define mmVPCNVC_CFG1_VPCNVC_FCNV_FP_SCALE_B_DEFAULT 0x1F000 +#define mmVPCNVC_CFG1_VPCNVC_FCNV_FP_SCALE_B_DEFAULT 0x1F000 +#define mmVPCNVC_CFG0_VPCNVC_COLOR_KEYER_CONTROL_DEFAULT 0x0000 +#define mmVPCNVC_CFG0_VPCNVC_COLOR_KEYER_CONTROL_DEFAULT 0x0000 +#define mmVPCNVC_CFG1_VPCNVC_COLOR_KEYER_CONTROL_DEFAULT 0x0000 +#define mmVPCNVC_CFG1_VPCNVC_COLOR_KEYER_CONTROL_DEFAULT 0x0000 +#define mmVPCNVC_CFG0_VPCNVC_COLOR_KEYER_ALPHA_DEFAULT 0x0000 +#define mmVPCNVC_CFG0_VPCNVC_COLOR_KEYER_ALPHA_DEFAULT 0x0000 +#define mmVPCNVC_CFG1_VPCNVC_COLOR_KEYER_ALPHA_DEFAULT 0x0000 +#define mmVPCNVC_CFG1_VPCNVC_COLOR_KEYER_ALPHA_DEFAULT 0x0000 +#define mmVPCNVC_CFG0_VPCNVC_COLOR_KEYER_RED_DEFAULT 0x0000 +#define mmVPCNVC_CFG0_VPCNVC_COLOR_KEYER_RED_DEFAULT 0x0000 +#define mmVPCNVC_CFG1_VPCNVC_COLOR_KEYER_RED_DEFAULT 0x0000 +#define mmVPCNVC_CFG1_VPCNVC_COLOR_KEYER_RED_DEFAULT 0x0000 +#define mmVPCNVC_CFG0_VPCNVC_COLOR_KEYER_GREEN_DEFAULT 0x0000 +#define mmVPCNVC_CFG0_VPCNVC_COLOR_KEYER_GREEN_DEFAULT 0x0000 +#define mmVPCNVC_CFG1_VPCNVC_COLOR_KEYER_GREEN_DEFAULT 0x0000 +#define mmVPCNVC_CFG1_VPCNVC_COLOR_KEYER_GREEN_DEFAULT 0x0000 +#define mmVPCNVC_CFG0_VPCNVC_COLOR_KEYER_BLUE_DEFAULT 0x0000 +#define mmVPCNVC_CFG0_VPCNVC_COLOR_KEYER_BLUE_DEFAULT 0x0000 +#define mmVPCNVC_CFG1_VPCNVC_COLOR_KEYER_BLUE_DEFAULT 0x0000 +#define mmVPCNVC_CFG1_VPCNVC_COLOR_KEYER_BLUE_DEFAULT 0x0000 +#define mmVPCNVC_CFG0_VPCNVC_ALPHA_2BIT_LUT01_DEFAULT 0x5550000 +#define mmVPCNVC_CFG0_VPCNVC_ALPHA_2BIT_LUT01_DEFAULT 0x5550000 +#define mmVPCNVC_CFG1_VPCNVC_ALPHA_2BIT_LUT01_DEFAULT 0x5550000 +#define mmVPCNVC_CFG1_VPCNVC_ALPHA_2BIT_LUT01_DEFAULT 0x5550000 +#define mmVPCNVC_CFG0_VPCNVC_ALPHA_2BIT_LUT23_DEFAULT 0xFFF0AAA +#define mmVPCNVC_CFG0_VPCNVC_ALPHA_2BIT_LUT23_DEFAULT 0xFFF0AAA +#define mmVPCNVC_CFG1_VPCNVC_ALPHA_2BIT_LUT23_DEFAULT 0xFFF0AAA +#define mmVPCNVC_CFG1_VPCNVC_ALPHA_2BIT_LUT23_DEFAULT 0xFFF0AAA +#define mmVPCNVC_CFG0_VPCNVC_PRE_DEALPHA_DEFAULT 0x0000 +#define mmVPCNVC_CFG0_VPCNVC_PRE_DEALPHA_DEFAULT 0x0000 +#define mmVPCNVC_CFG1_VPCNVC_PRE_DEALPHA_DEFAULT 0x0000 +#define mmVPCNVC_CFG1_VPCNVC_PRE_DEALPHA_DEFAULT 0x0000 +#define mmVPCNVC_CFG0_VPCNVC_PRE_CSC_MODE_DEFAULT 0x0000 +#define mmVPCNVC_CFG0_VPCNVC_PRE_CSC_MODE_DEFAULT 0x0000 +#define mmVPCNVC_CFG1_VPCNVC_PRE_CSC_MODE_DEFAULT 0x0000 +#define mmVPCNVC_CFG1_VPCNVC_PRE_CSC_MODE_DEFAULT 0x0000 +#define mmVPCNVC_CFG0_VPCNVC_PRE_CSC_C11_C12_DEFAULT 0x2000 +#define mmVPCNVC_CFG0_VPCNVC_PRE_CSC_C11_C12_DEFAULT 0x2000 +#define mmVPCNVC_CFG1_VPCNVC_PRE_CSC_C11_C12_DEFAULT 0x2000 +#define mmVPCNVC_CFG1_VPCNVC_PRE_CSC_C11_C12_DEFAULT 0x2000 +#define mmVPCNVC_CFG0_VPCNVC_PRE_CSC_C13_C14_DEFAULT 0x0000 +#define mmVPCNVC_CFG0_VPCNVC_PRE_CSC_C13_C14_DEFAULT 0x0000 +#define mmVPCNVC_CFG1_VPCNVC_PRE_CSC_C13_C14_DEFAULT 0x0000 +#define mmVPCNVC_CFG1_VPCNVC_PRE_CSC_C13_C14_DEFAULT 0x0000 +#define mmVPCNVC_CFG0_VPCNVC_PRE_CSC_C21_C22_DEFAULT 0x20000000 +#define mmVPCNVC_CFG0_VPCNVC_PRE_CSC_C21_C22_DEFAULT 0x20000000 +#define mmVPCNVC_CFG1_VPCNVC_PRE_CSC_C21_C22_DEFAULT 0x20000000 +#define mmVPCNVC_CFG1_VPCNVC_PRE_CSC_C21_C22_DEFAULT 0x20000000 +#define mmVPCNVC_CFG0_VPCNVC_PRE_CSC_C23_C24_DEFAULT 0x0000 +#define mmVPCNVC_CFG0_VPCNVC_PRE_CSC_C23_C24_DEFAULT 0x0000 +#define mmVPCNVC_CFG1_VPCNVC_PRE_CSC_C23_C24_DEFAULT 0x0000 +#define mmVPCNVC_CFG1_VPCNVC_PRE_CSC_C23_C24_DEFAULT 0x0000 +#define mmVPCNVC_CFG0_VPCNVC_PRE_CSC_C31_C32_DEFAULT 0x0000 +#define mmVPCNVC_CFG0_VPCNVC_PRE_CSC_C31_C32_DEFAULT 0x0000 +#define mmVPCNVC_CFG1_VPCNVC_PRE_CSC_C31_C32_DEFAULT 0x0000 +#define mmVPCNVC_CFG1_VPCNVC_PRE_CSC_C31_C32_DEFAULT 0x0000 +#define mmVPCNVC_CFG0_VPCNVC_PRE_CSC_C33_C34_DEFAULT 0x2000 +#define mmVPCNVC_CFG0_VPCNVC_PRE_CSC_C33_C34_DEFAULT 0x2000 +#define mmVPCNVC_CFG1_VPCNVC_PRE_CSC_C33_C34_DEFAULT 0x2000 +#define mmVPCNVC_CFG1_VPCNVC_PRE_CSC_C33_C34_DEFAULT 0x2000 +#define mmVPCNVC_CFG0_VPCNVC_COEF_FORMAT_DEFAULT 0x0000 +#define mmVPCNVC_CFG0_VPCNVC_COEF_FORMAT_DEFAULT 0x0000 +#define mmVPCNVC_CFG1_VPCNVC_COEF_FORMAT_DEFAULT 0x0000 +#define mmVPCNVC_CFG1_VPCNVC_COEF_FORMAT_DEFAULT 0x0000 +#define mmVPCNVC_CFG0_VPCNVC_PRE_DEGAM_DEFAULT 0x0000 +#define mmVPCNVC_CFG0_VPCNVC_PRE_DEGAM_DEFAULT 0x0000 +#define mmVPCNVC_CFG1_VPCNVC_PRE_DEGAM_DEFAULT 0x0000 +#define mmVPCNVC_CFG1_VPCNVC_PRE_DEGAM_DEFAULT 0x0000 +#define mmVPCNVC_CFG0_VPCNVC_PRE_REALPHA_DEFAULT 0x0000 +#define mmVPCNVC_CFG0_VPCNVC_PRE_REALPHA_DEFAULT 0x0000 +#define mmVPCNVC_CFG1_VPCNVC_PRE_REALPHA_DEFAULT 0x0000 +#define mmVPCNVC_CFG1_VPCNVC_PRE_REALPHA_DEFAULT 0x0000 + + +// Registers from VPDSCL block + +#define mmVPDSCL0_VPDSCL_COEF_RAM_TAP_SELECT_DEFAULT 0x0000 +#define mmVPDSCL0_VPDSCL_COEF_RAM_TAP_SELECT_DEFAULT 0x0000 +#define mmVPDSCL1_VPDSCL_COEF_RAM_TAP_SELECT_DEFAULT 0x0000 +#define mmVPDSCL1_VPDSCL_COEF_RAM_TAP_SELECT_DEFAULT 0x0000 +#define mmVPDSCL0_VPDSCL_COEF_RAM_TAP_DATA_DEFAULT 0x0000 +#define mmVPDSCL0_VPDSCL_COEF_RAM_TAP_DATA_DEFAULT 0x0000 +#define mmVPDSCL1_VPDSCL_COEF_RAM_TAP_DATA_DEFAULT 0x0000 +#define mmVPDSCL1_VPDSCL_COEF_RAM_TAP_DATA_DEFAULT 0x0000 +#define mmVPDSCL0_VPDSCL_MODE_DEFAULT 0x0000 +#define mmVPDSCL0_VPDSCL_MODE_DEFAULT 0x0000 +#define mmVPDSCL1_VPDSCL_MODE_DEFAULT 0x0000 +#define mmVPDSCL1_VPDSCL_MODE_DEFAULT 0x0000 +#define mmVPDSCL0_VPDSCL_TAP_CONTROL_DEFAULT 0x0000 +#define mmVPDSCL0_VPDSCL_TAP_CONTROL_DEFAULT 0x0000 +#define mmVPDSCL1_VPDSCL_TAP_CONTROL_DEFAULT 0x0000 +#define mmVPDSCL1_VPDSCL_TAP_CONTROL_DEFAULT 0x0000 +#define mmVPDSCL0_VPDSCL_CONTROL_DEFAULT 0x0000 +#define mmVPDSCL0_VPDSCL_CONTROL_DEFAULT 0x0000 +#define mmVPDSCL1_VPDSCL_CONTROL_DEFAULT 0x0000 +#define mmVPDSCL1_VPDSCL_CONTROL_DEFAULT 0x0000 +#define mmVPDSCL0_VPDSCL_2TAP_CONTROL_DEFAULT 0x1000100 +#define mmVPDSCL0_VPDSCL_2TAP_CONTROL_DEFAULT 0x1000100 +#define mmVPDSCL1_VPDSCL_2TAP_CONTROL_DEFAULT 0x1000100 +#define mmVPDSCL1_VPDSCL_2TAP_CONTROL_DEFAULT 0x1000100 +#define mmVPDSCL0_VPDSCL_MANUAL_REPLICATE_CONTROL_DEFAULT 0x0000 +#define mmVPDSCL0_VPDSCL_MANUAL_REPLICATE_CONTROL_DEFAULT 0x0000 +#define mmVPDSCL1_VPDSCL_MANUAL_REPLICATE_CONTROL_DEFAULT 0x0000 +#define mmVPDSCL1_VPDSCL_MANUAL_REPLICATE_CONTROL_DEFAULT 0x0000 +#define mmVPDSCL0_VPDSCL_HORZ_FILTER_SCALE_RATIO_DEFAULT 0x0000 +#define mmVPDSCL0_VPDSCL_HORZ_FILTER_SCALE_RATIO_DEFAULT 0x0000 +#define mmVPDSCL1_VPDSCL_HORZ_FILTER_SCALE_RATIO_DEFAULT 0x0000 +#define mmVPDSCL1_VPDSCL_HORZ_FILTER_SCALE_RATIO_DEFAULT 0x0000 +#define mmVPDSCL0_VPDSCL_HORZ_FILTER_INIT_DEFAULT 0x1000000 +#define mmVPDSCL0_VPDSCL_HORZ_FILTER_INIT_DEFAULT 0x1000000 +#define mmVPDSCL1_VPDSCL_HORZ_FILTER_INIT_DEFAULT 0x1000000 +#define mmVPDSCL1_VPDSCL_HORZ_FILTER_INIT_DEFAULT 0x1000000 +#define mmVPDSCL0_VPDSCL_HORZ_FILTER_SCALE_RATIO_C_DEFAULT 0x0000 +#define mmVPDSCL0_VPDSCL_HORZ_FILTER_SCALE_RATIO_C_DEFAULT 0x0000 +#define mmVPDSCL1_VPDSCL_HORZ_FILTER_SCALE_RATIO_C_DEFAULT 0x0000 +#define mmVPDSCL1_VPDSCL_HORZ_FILTER_SCALE_RATIO_C_DEFAULT 0x0000 +#define mmVPDSCL0_VPDSCL_HORZ_FILTER_INIT_C_DEFAULT 0x1000000 +#define mmVPDSCL0_VPDSCL_HORZ_FILTER_INIT_C_DEFAULT 0x1000000 +#define mmVPDSCL1_VPDSCL_HORZ_FILTER_INIT_C_DEFAULT 0x1000000 +#define mmVPDSCL1_VPDSCL_HORZ_FILTER_INIT_C_DEFAULT 0x1000000 +#define mmVPDSCL0_VPDSCL_VERT_FILTER_SCALE_RATIO_DEFAULT 0x0000 +#define mmVPDSCL0_VPDSCL_VERT_FILTER_SCALE_RATIO_DEFAULT 0x0000 +#define mmVPDSCL1_VPDSCL_VERT_FILTER_SCALE_RATIO_DEFAULT 0x0000 +#define mmVPDSCL1_VPDSCL_VERT_FILTER_SCALE_RATIO_DEFAULT 0x0000 +#define mmVPDSCL0_VPDSCL_VERT_FILTER_INIT_DEFAULT 0x1000000 +#define mmVPDSCL0_VPDSCL_VERT_FILTER_INIT_DEFAULT 0x1000000 +#define mmVPDSCL1_VPDSCL_VERT_FILTER_INIT_DEFAULT 0x1000000 +#define mmVPDSCL1_VPDSCL_VERT_FILTER_INIT_DEFAULT 0x1000000 +#define mmVPDSCL0_VPDSCL_VERT_FILTER_INIT_BOT_DEFAULT 0x1000000 +#define mmVPDSCL0_VPDSCL_VERT_FILTER_INIT_BOT_DEFAULT 0x1000000 +#define mmVPDSCL1_VPDSCL_VERT_FILTER_INIT_BOT_DEFAULT 0x1000000 +#define mmVPDSCL1_VPDSCL_VERT_FILTER_INIT_BOT_DEFAULT 0x1000000 +#define mmVPDSCL0_VPDSCL_VERT_FILTER_SCALE_RATIO_C_DEFAULT 0x0000 +#define mmVPDSCL0_VPDSCL_VERT_FILTER_SCALE_RATIO_C_DEFAULT 0x0000 +#define mmVPDSCL1_VPDSCL_VERT_FILTER_SCALE_RATIO_C_DEFAULT 0x0000 +#define mmVPDSCL1_VPDSCL_VERT_FILTER_SCALE_RATIO_C_DEFAULT 0x0000 +#define mmVPDSCL0_VPDSCL_VERT_FILTER_INIT_C_DEFAULT 0x1000000 +#define mmVPDSCL0_VPDSCL_VERT_FILTER_INIT_C_DEFAULT 0x1000000 +#define mmVPDSCL1_VPDSCL_VERT_FILTER_INIT_C_DEFAULT 0x1000000 +#define mmVPDSCL1_VPDSCL_VERT_FILTER_INIT_C_DEFAULT 0x1000000 +#define mmVPDSCL0_VPDSCL_VERT_FILTER_INIT_BOT_C_DEFAULT 0x1000000 +#define mmVPDSCL0_VPDSCL_VERT_FILTER_INIT_BOT_C_DEFAULT 0x1000000 +#define mmVPDSCL1_VPDSCL_VERT_FILTER_INIT_BOT_C_DEFAULT 0x1000000 +#define mmVPDSCL1_VPDSCL_VERT_FILTER_INIT_BOT_C_DEFAULT 0x1000000 +#define mmVPDSCL0_VPDSCL_BLACK_COLOR_DEFAULT 0x3C000000 +#define mmVPDSCL0_VPDSCL_BLACK_COLOR_DEFAULT 0x3C000000 +#define mmVPDSCL1_VPDSCL_BLACK_COLOR_DEFAULT 0x3C000000 +#define mmVPDSCL1_VPDSCL_BLACK_COLOR_DEFAULT 0x3C000000 +#define mmVPDSCL0_VPDSCL_UPDATE_DEFAULT 0x0000 +#define mmVPDSCL0_VPDSCL_UPDATE_DEFAULT 0x0000 +#define mmVPDSCL1_VPDSCL_UPDATE_DEFAULT 0x0000 +#define mmVPDSCL1_VPDSCL_UPDATE_DEFAULT 0x0000 +#define mmVPDSCL0_VPDSCL_AUTOCAL_DEFAULT 0x0000 +#define mmVPDSCL0_VPDSCL_AUTOCAL_DEFAULT 0x0000 +#define mmVPDSCL1_VPDSCL_AUTOCAL_DEFAULT 0x0000 +#define mmVPDSCL1_VPDSCL_AUTOCAL_DEFAULT 0x0000 +#define mmVPDSCL0_VPDSCL_EXT_OVERSCAN_LEFT_RIGHT_DEFAULT 0x0000 +#define mmVPDSCL0_VPDSCL_EXT_OVERSCAN_LEFT_RIGHT_DEFAULT 0x0000 +#define mmVPDSCL1_VPDSCL_EXT_OVERSCAN_LEFT_RIGHT_DEFAULT 0x0000 +#define mmVPDSCL1_VPDSCL_EXT_OVERSCAN_LEFT_RIGHT_DEFAULT 0x0000 +#define mmVPDSCL0_VPDSCL_EXT_OVERSCAN_TOP_BOTTOM_DEFAULT 0x0000 +#define mmVPDSCL0_VPDSCL_EXT_OVERSCAN_TOP_BOTTOM_DEFAULT 0x0000 +#define mmVPDSCL1_VPDSCL_EXT_OVERSCAN_TOP_BOTTOM_DEFAULT 0x0000 +#define mmVPDSCL1_VPDSCL_EXT_OVERSCAN_TOP_BOTTOM_DEFAULT 0x0000 +#define mmVPDSCL0_VPOTG_H_BLANK_DEFAULT 0x0000 +#define mmVPDSCL0_VPOTG_H_BLANK_DEFAULT 0x0000 +#define mmVPDSCL1_VPOTG_H_BLANK_DEFAULT 0x0000 +#define mmVPDSCL1_VPOTG_H_BLANK_DEFAULT 0x0000 +#define mmVPDSCL0_VPOTG_V_BLANK_DEFAULT 0x0000 +#define mmVPDSCL0_VPOTG_V_BLANK_DEFAULT 0x0000 +#define mmVPDSCL1_VPOTG_V_BLANK_DEFAULT 0x0000 +#define mmVPDSCL1_VPOTG_V_BLANK_DEFAULT 0x0000 +#define mmVPDSCL0_VPDSCL_RECOUT_START_DEFAULT 0x0000 +#define mmVPDSCL0_VPDSCL_RECOUT_START_DEFAULT 0x0000 +#define mmVPDSCL1_VPDSCL_RECOUT_START_DEFAULT 0x0000 +#define mmVPDSCL1_VPDSCL_RECOUT_START_DEFAULT 0x0000 +#define mmVPDSCL0_VPDSCL_RECOUT_SIZE_DEFAULT 0x0000 +#define mmVPDSCL0_VPDSCL_RECOUT_SIZE_DEFAULT 0x0000 +#define mmVPDSCL1_VPDSCL_RECOUT_SIZE_DEFAULT 0x0000 +#define mmVPDSCL1_VPDSCL_RECOUT_SIZE_DEFAULT 0x0000 +#define mmVPDSCL0_VPMPC_SIZE_DEFAULT 0x0000 +#define mmVPDSCL0_VPMPC_SIZE_DEFAULT 0x0000 +#define mmVPDSCL1_VPMPC_SIZE_DEFAULT 0x0000 +#define mmVPDSCL1_VPMPC_SIZE_DEFAULT 0x0000 +#define mmVPDSCL0_VPLB_DATA_FORMAT_DEFAULT 0x0000 +#define mmVPDSCL0_VPLB_DATA_FORMAT_DEFAULT 0x0000 +#define mmVPDSCL1_VPLB_DATA_FORMAT_DEFAULT 0x0000 +#define mmVPDSCL1_VPLB_DATA_FORMAT_DEFAULT 0x0000 +#define mmVPDSCL0_VPLB_MEMORY_CTRL_DEFAULT 0x3F00 +#define mmVPDSCL0_VPLB_MEMORY_CTRL_DEFAULT 0x3F00 +#define mmVPDSCL1_VPLB_MEMORY_CTRL_DEFAULT 0x3F00 +#define mmVPDSCL1_VPLB_MEMORY_CTRL_DEFAULT 0x3F00 +#define mmVPDSCL0_VPLB_V_COUNTER_DEFAULT 0x0000 +#define mmVPDSCL0_VPLB_V_COUNTER_DEFAULT 0x0000 +#define mmVPDSCL1_VPLB_V_COUNTER_DEFAULT 0x0000 +#define mmVPDSCL1_VPLB_V_COUNTER_DEFAULT 0x0000 +#define mmVPDSCL0_VPDSCL_MEM_PWR_CTRL_DEFAULT 0x0000 +#define mmVPDSCL0_VPDSCL_MEM_PWR_CTRL_DEFAULT 0x0000 +#define mmVPDSCL1_VPDSCL_MEM_PWR_CTRL_DEFAULT 0x0000 +#define mmVPDSCL1_VPDSCL_MEM_PWR_CTRL_DEFAULT 0x0000 +#define mmVPDSCL0_VPDSCL_MEM_PWR_STATUS_DEFAULT 0x0000 +#define mmVPDSCL0_VPDSCL_MEM_PWR_STATUS_DEFAULT 0x0000 +#define mmVPDSCL1_VPDSCL_MEM_PWR_STATUS_DEFAULT 0x0000 +#define mmVPDSCL1_VPDSCL_MEM_PWR_STATUS_DEFAULT 0x0000 +#define mmVPDSCL0_VPDSCL_EASF_H_MODE_DEFAULT 0x0100 +#define mmVPDSCL0_VPDSCL_EASF_H_MODE_DEFAULT 0x0100 +#define mmVPDSCL1_VPDSCL_EASF_H_MODE_DEFAULT 0x0100 +#define mmVPDSCL1_VPDSCL_EASF_H_MODE_DEFAULT 0x0100 +#define mmVPDSCL0_VPDSCL_EASF_V_MODE_DEFAULT 0x0100 +#define mmVPDSCL0_VPDSCL_EASF_V_MODE_DEFAULT 0x0100 +#define mmVPDSCL1_VPDSCL_EASF_V_MODE_DEFAULT 0x0100 +#define mmVPDSCL1_VPDSCL_EASF_V_MODE_DEFAULT 0x0100 +#define mmVPDSCL0_VPDSCL_SC_MODE_DEFAULT 0x0000 +#define mmVPDSCL0_VPDSCL_SC_MODE_DEFAULT 0x0000 +#define mmVPDSCL1_VPDSCL_SC_MODE_DEFAULT 0x0000 +#define mmVPDSCL1_VPDSCL_SC_MODE_DEFAULT 0x0000 +#define mmVPDSCL0_VPDSCL_SC_MATRIX_C0C1_DEFAULT 0x0000 +#define mmVPDSCL0_VPDSCL_SC_MATRIX_C0C1_DEFAULT 0x0000 +#define mmVPDSCL1_VPDSCL_SC_MATRIX_C0C1_DEFAULT 0x0000 +#define mmVPDSCL1_VPDSCL_SC_MATRIX_C0C1_DEFAULT 0x0000 +#define mmVPDSCL0_VPDSCL_SC_MATRIX_C2C3_DEFAULT 0x0000 +#define mmVPDSCL0_VPDSCL_SC_MATRIX_C2C3_DEFAULT 0x0000 +#define mmVPDSCL1_VPDSCL_SC_MATRIX_C2C3_DEFAULT 0x0000 +#define mmVPDSCL1_VPDSCL_SC_MATRIX_C2C3_DEFAULT 0x0000 +#define mmVPDSCL0_VPDSCL_EASF_H_RINGEST_EVENTAP_GAIN_DEFAULT 0x0000 +#define mmVPDSCL0_VPDSCL_EASF_H_RINGEST_EVENTAP_GAIN_DEFAULT 0x0000 +#define mmVPDSCL1_VPDSCL_EASF_H_RINGEST_EVENTAP_GAIN_DEFAULT 0x0000 +#define mmVPDSCL1_VPDSCL_EASF_H_RINGEST_EVENTAP_GAIN_DEFAULT 0x0000 +#define mmVPDSCL0_VPDSCL_EASF_H_RINGEST_EVENTAP_REDUCE_DEFAULT 0x0000 +#define mmVPDSCL0_VPDSCL_EASF_H_RINGEST_EVENTAP_REDUCE_DEFAULT 0x0000 +#define mmVPDSCL1_VPDSCL_EASF_H_RINGEST_EVENTAP_REDUCE_DEFAULT 0x0000 +#define mmVPDSCL1_VPDSCL_EASF_H_RINGEST_EVENTAP_REDUCE_DEFAULT 0x0000 +#define mmVPDSCL0_VPDSCL_EASF_V_RINGEST_EVENTAP_GAIN_DEFAULT 0x0000 +#define mmVPDSCL0_VPDSCL_EASF_V_RINGEST_EVENTAP_GAIN_DEFAULT 0x0000 +#define mmVPDSCL1_VPDSCL_EASF_V_RINGEST_EVENTAP_GAIN_DEFAULT 0x0000 +#define mmVPDSCL1_VPDSCL_EASF_V_RINGEST_EVENTAP_GAIN_DEFAULT 0x0000 +#define mmVPDSCL0_VPDSCL_EASF_V_RINGEST_EVENTAP_REDUCE_DEFAULT 0x0000 +#define mmVPDSCL0_VPDSCL_EASF_V_RINGEST_EVENTAP_REDUCE_DEFAULT 0x0000 +#define mmVPDSCL1_VPDSCL_EASF_V_RINGEST_EVENTAP_REDUCE_DEFAULT 0x0000 +#define mmVPDSCL1_VPDSCL_EASF_V_RINGEST_EVENTAP_REDUCE_DEFAULT 0x0000 +#define mmVPDSCL0_VPDSCL_EASF_V_RINGEST_3TAP_CNTL1_DEFAULT 0x0000 +#define mmVPDSCL0_VPDSCL_EASF_V_RINGEST_3TAP_CNTL1_DEFAULT 0x0000 +#define mmVPDSCL1_VPDSCL_EASF_V_RINGEST_3TAP_CNTL1_DEFAULT 0x0000 +#define mmVPDSCL1_VPDSCL_EASF_V_RINGEST_3TAP_CNTL1_DEFAULT 0x0000 +#define mmVPDSCL0_VPDSCL_EASF_V_RINGEST_3TAP_CNTL2_DEFAULT 0x0000 +#define mmVPDSCL0_VPDSCL_EASF_V_RINGEST_3TAP_CNTL2_DEFAULT 0x0000 +#define mmVPDSCL1_VPDSCL_EASF_V_RINGEST_3TAP_CNTL2_DEFAULT 0x0000 +#define mmVPDSCL1_VPDSCL_EASF_V_RINGEST_3TAP_CNTL2_DEFAULT 0x0000 +#define mmVPDSCL0_VPDSCL_EASF_V_RINGEST_3TAP_CNTL3_DEFAULT 0x0000 +#define mmVPDSCL0_VPDSCL_EASF_V_RINGEST_3TAP_CNTL3_DEFAULT 0x0000 +#define mmVPDSCL1_VPDSCL_EASF_V_RINGEST_3TAP_CNTL3_DEFAULT 0x0000 +#define mmVPDSCL1_VPDSCL_EASF_V_RINGEST_3TAP_CNTL3_DEFAULT 0x0000 +#define mmVPDSCL0_VPDSCL_EASF_RINGEST_FORCE_DEFAULT 0x0000 +#define mmVPDSCL0_VPDSCL_EASF_RINGEST_FORCE_DEFAULT 0x0000 +#define mmVPDSCL1_VPDSCL_EASF_RINGEST_FORCE_DEFAULT 0x0000 +#define mmVPDSCL1_VPDSCL_EASF_RINGEST_FORCE_DEFAULT 0x0000 +#define mmVPDSCL0_VPDSCL_EASF_H_BF_CNTL_DEFAULT 0x11100B00 +#define mmVPDSCL0_VPDSCL_EASF_H_BF_CNTL_DEFAULT 0x11100B00 +#define mmVPDSCL1_VPDSCL_EASF_H_BF_CNTL_DEFAULT 0x11100B00 +#define mmVPDSCL1_VPDSCL_EASF_H_BF_CNTL_DEFAULT 0x11100B00 +#define mmVPDSCL0_VPDSCL_EASF_H_BF_FINAL_MAX_MIN_DEFAULT 0x3F3F +#define mmVPDSCL0_VPDSCL_EASF_H_BF_FINAL_MAX_MIN_DEFAULT 0x3F3F +#define mmVPDSCL1_VPDSCL_EASF_H_BF_FINAL_MAX_MIN_DEFAULT 0x3F3F +#define mmVPDSCL1_VPDSCL_EASF_H_BF_FINAL_MAX_MIN_DEFAULT 0x3F3F +#define mmVPDSCL0_VPDSCL_EASF_V_BF_CNTL_DEFAULT 0x11100B00 +#define mmVPDSCL0_VPDSCL_EASF_V_BF_CNTL_DEFAULT 0x11100B00 +#define mmVPDSCL1_VPDSCL_EASF_V_BF_CNTL_DEFAULT 0x11100B00 +#define mmVPDSCL1_VPDSCL_EASF_V_BF_CNTL_DEFAULT 0x11100B00 +#define mmVPDSCL0_VPDSCL_EASF_V_BF_FINAL_MAX_MIN_DEFAULT 0x3F3F +#define mmVPDSCL0_VPDSCL_EASF_V_BF_FINAL_MAX_MIN_DEFAULT 0x3F3F +#define mmVPDSCL1_VPDSCL_EASF_V_BF_FINAL_MAX_MIN_DEFAULT 0x3F3F +#define mmVPDSCL1_VPDSCL_EASF_V_BF_FINAL_MAX_MIN_DEFAULT 0x3F3F +#define mmVPDSCL0_VPDSCL_EASF_H_BF1_PWL_SEG0_DEFAULT 0x0000 +#define mmVPDSCL0_VPDSCL_EASF_H_BF1_PWL_SEG0_DEFAULT 0x0000 +#define mmVPDSCL1_VPDSCL_EASF_H_BF1_PWL_SEG0_DEFAULT 0x0000 +#define mmVPDSCL1_VPDSCL_EASF_H_BF1_PWL_SEG0_DEFAULT 0x0000 +#define mmVPDSCL0_VPDSCL_EASF_H_BF1_PWL_SEG1_DEFAULT 0x0000 +#define mmVPDSCL0_VPDSCL_EASF_H_BF1_PWL_SEG1_DEFAULT 0x0000 +#define mmVPDSCL1_VPDSCL_EASF_H_BF1_PWL_SEG1_DEFAULT 0x0000 +#define mmVPDSCL1_VPDSCL_EASF_H_BF1_PWL_SEG1_DEFAULT 0x0000 +#define mmVPDSCL0_VPDSCL_EASF_H_BF1_PWL_SEG2_DEFAULT 0x0000 +#define mmVPDSCL0_VPDSCL_EASF_H_BF1_PWL_SEG2_DEFAULT 0x0000 +#define mmVPDSCL1_VPDSCL_EASF_H_BF1_PWL_SEG2_DEFAULT 0x0000 +#define mmVPDSCL1_VPDSCL_EASF_H_BF1_PWL_SEG2_DEFAULT 0x0000 +#define mmVPDSCL0_VPDSCL_EASF_H_BF1_PWL_SEG3_DEFAULT 0x0000 +#define mmVPDSCL0_VPDSCL_EASF_H_BF1_PWL_SEG3_DEFAULT 0x0000 +#define mmVPDSCL1_VPDSCL_EASF_H_BF1_PWL_SEG3_DEFAULT 0x0000 +#define mmVPDSCL1_VPDSCL_EASF_H_BF1_PWL_SEG3_DEFAULT 0x0000 +#define mmVPDSCL0_VPDSCL_EASF_H_BF1_PWL_SEG4_DEFAULT 0x0000 +#define mmVPDSCL0_VPDSCL_EASF_H_BF1_PWL_SEG4_DEFAULT 0x0000 +#define mmVPDSCL1_VPDSCL_EASF_H_BF1_PWL_SEG4_DEFAULT 0x0000 +#define mmVPDSCL1_VPDSCL_EASF_H_BF1_PWL_SEG4_DEFAULT 0x0000 +#define mmVPDSCL0_VPDSCL_EASF_H_BF1_PWL_SEG5_DEFAULT 0x0000 +#define mmVPDSCL0_VPDSCL_EASF_H_BF1_PWL_SEG5_DEFAULT 0x0000 +#define mmVPDSCL1_VPDSCL_EASF_H_BF1_PWL_SEG5_DEFAULT 0x0000 +#define mmVPDSCL1_VPDSCL_EASF_H_BF1_PWL_SEG5_DEFAULT 0x0000 +#define mmVPDSCL0_VPDSCL_EASF_H_BF1_PWL_SEG6_DEFAULT 0x0000 +#define mmVPDSCL0_VPDSCL_EASF_H_BF1_PWL_SEG6_DEFAULT 0x0000 +#define mmVPDSCL1_VPDSCL_EASF_H_BF1_PWL_SEG6_DEFAULT 0x0000 +#define mmVPDSCL1_VPDSCL_EASF_H_BF1_PWL_SEG6_DEFAULT 0x0000 +#define mmVPDSCL0_VPDSCL_EASF_H_BF1_PWL_SEG7_DEFAULT 0x0000 +#define mmVPDSCL0_VPDSCL_EASF_H_BF1_PWL_SEG7_DEFAULT 0x0000 +#define mmVPDSCL1_VPDSCL_EASF_H_BF1_PWL_SEG7_DEFAULT 0x0000 +#define mmVPDSCL1_VPDSCL_EASF_H_BF1_PWL_SEG7_DEFAULT 0x0000 +#define mmVPDSCL0_VPDSCL_EASF_V_BF1_PWL_SEG0_DEFAULT 0x0000 +#define mmVPDSCL0_VPDSCL_EASF_V_BF1_PWL_SEG0_DEFAULT 0x0000 +#define mmVPDSCL1_VPDSCL_EASF_V_BF1_PWL_SEG0_DEFAULT 0x0000 +#define mmVPDSCL1_VPDSCL_EASF_V_BF1_PWL_SEG0_DEFAULT 0x0000 +#define mmVPDSCL0_VPDSCL_EASF_V_BF1_PWL_SEG1_DEFAULT 0x0000 +#define mmVPDSCL0_VPDSCL_EASF_V_BF1_PWL_SEG1_DEFAULT 0x0000 +#define mmVPDSCL1_VPDSCL_EASF_V_BF1_PWL_SEG1_DEFAULT 0x0000 +#define mmVPDSCL1_VPDSCL_EASF_V_BF1_PWL_SEG1_DEFAULT 0x0000 +#define mmVPDSCL0_VPDSCL_EASF_V_BF1_PWL_SEG2_DEFAULT 0x0000 +#define mmVPDSCL0_VPDSCL_EASF_V_BF1_PWL_SEG2_DEFAULT 0x0000 +#define mmVPDSCL1_VPDSCL_EASF_V_BF1_PWL_SEG2_DEFAULT 0x0000 +#define mmVPDSCL1_VPDSCL_EASF_V_BF1_PWL_SEG2_DEFAULT 0x0000 +#define mmVPDSCL0_VPDSCL_EASF_V_BF1_PWL_SEG3_DEFAULT 0x0000 +#define mmVPDSCL0_VPDSCL_EASF_V_BF1_PWL_SEG3_DEFAULT 0x0000 +#define mmVPDSCL1_VPDSCL_EASF_V_BF1_PWL_SEG3_DEFAULT 0x0000 +#define mmVPDSCL1_VPDSCL_EASF_V_BF1_PWL_SEG3_DEFAULT 0x0000 +#define mmVPDSCL0_VPDSCL_EASF_V_BF1_PWL_SEG4_DEFAULT 0x0000 +#define mmVPDSCL0_VPDSCL_EASF_V_BF1_PWL_SEG4_DEFAULT 0x0000 +#define mmVPDSCL1_VPDSCL_EASF_V_BF1_PWL_SEG4_DEFAULT 0x0000 +#define mmVPDSCL1_VPDSCL_EASF_V_BF1_PWL_SEG4_DEFAULT 0x0000 +#define mmVPDSCL0_VPDSCL_EASF_V_BF1_PWL_SEG5_DEFAULT 0x0000 +#define mmVPDSCL0_VPDSCL_EASF_V_BF1_PWL_SEG5_DEFAULT 0x0000 +#define mmVPDSCL1_VPDSCL_EASF_V_BF1_PWL_SEG5_DEFAULT 0x0000 +#define mmVPDSCL1_VPDSCL_EASF_V_BF1_PWL_SEG5_DEFAULT 0x0000 +#define mmVPDSCL0_VPDSCL_EASF_V_BF1_PWL_SEG6_DEFAULT 0x0000 +#define mmVPDSCL0_VPDSCL_EASF_V_BF1_PWL_SEG6_DEFAULT 0x0000 +#define mmVPDSCL1_VPDSCL_EASF_V_BF1_PWL_SEG6_DEFAULT 0x0000 +#define mmVPDSCL1_VPDSCL_EASF_V_BF1_PWL_SEG6_DEFAULT 0x0000 +#define mmVPDSCL0_VPDSCL_EASF_V_BF1_PWL_SEG7_DEFAULT 0x0000 +#define mmVPDSCL0_VPDSCL_EASF_V_BF1_PWL_SEG7_DEFAULT 0x0000 +#define mmVPDSCL1_VPDSCL_EASF_V_BF1_PWL_SEG7_DEFAULT 0x0000 +#define mmVPDSCL1_VPDSCL_EASF_V_BF1_PWL_SEG7_DEFAULT 0x0000 +#define mmVPDSCL0_VPDSCL_EASF_H_BF3_PWL_SEG0_DEFAULT 0x0000 +#define mmVPDSCL0_VPDSCL_EASF_H_BF3_PWL_SEG0_DEFAULT 0x0000 +#define mmVPDSCL1_VPDSCL_EASF_H_BF3_PWL_SEG0_DEFAULT 0x0000 +#define mmVPDSCL1_VPDSCL_EASF_H_BF3_PWL_SEG0_DEFAULT 0x0000 +#define mmVPDSCL0_VPDSCL_EASF_H_BF3_PWL_SEG1_DEFAULT 0x0000 +#define mmVPDSCL0_VPDSCL_EASF_H_BF3_PWL_SEG1_DEFAULT 0x0000 +#define mmVPDSCL1_VPDSCL_EASF_H_BF3_PWL_SEG1_DEFAULT 0x0000 +#define mmVPDSCL1_VPDSCL_EASF_H_BF3_PWL_SEG1_DEFAULT 0x0000 +#define mmVPDSCL0_VPDSCL_EASF_H_BF3_PWL_SEG2_DEFAULT 0x0000 +#define mmVPDSCL0_VPDSCL_EASF_H_BF3_PWL_SEG2_DEFAULT 0x0000 +#define mmVPDSCL1_VPDSCL_EASF_H_BF3_PWL_SEG2_DEFAULT 0x0000 +#define mmVPDSCL1_VPDSCL_EASF_H_BF3_PWL_SEG2_DEFAULT 0x0000 +#define mmVPDSCL0_VPDSCL_EASF_H_BF3_PWL_SEG3_DEFAULT 0x0000 +#define mmVPDSCL0_VPDSCL_EASF_H_BF3_PWL_SEG3_DEFAULT 0x0000 +#define mmVPDSCL1_VPDSCL_EASF_H_BF3_PWL_SEG3_DEFAULT 0x0000 +#define mmVPDSCL1_VPDSCL_EASF_H_BF3_PWL_SEG3_DEFAULT 0x0000 +#define mmVPDSCL0_VPDSCL_EASF_H_BF3_PWL_SEG4_DEFAULT 0x0000 +#define mmVPDSCL0_VPDSCL_EASF_H_BF3_PWL_SEG4_DEFAULT 0x0000 +#define mmVPDSCL1_VPDSCL_EASF_H_BF3_PWL_SEG4_DEFAULT 0x0000 +#define mmVPDSCL1_VPDSCL_EASF_H_BF3_PWL_SEG4_DEFAULT 0x0000 +#define mmVPDSCL0_VPDSCL_EASF_H_BF3_PWL_SEG5_DEFAULT 0x0000 +#define mmVPDSCL0_VPDSCL_EASF_H_BF3_PWL_SEG5_DEFAULT 0x0000 +#define mmVPDSCL1_VPDSCL_EASF_H_BF3_PWL_SEG5_DEFAULT 0x0000 +#define mmVPDSCL1_VPDSCL_EASF_H_BF3_PWL_SEG5_DEFAULT 0x0000 +#define mmVPDSCL0_VPDSCL_EASF_V_BF3_PWL_SEG0_DEFAULT 0x0000 +#define mmVPDSCL0_VPDSCL_EASF_V_BF3_PWL_SEG0_DEFAULT 0x0000 +#define mmVPDSCL1_VPDSCL_EASF_V_BF3_PWL_SEG0_DEFAULT 0x0000 +#define mmVPDSCL1_VPDSCL_EASF_V_BF3_PWL_SEG0_DEFAULT 0x0000 +#define mmVPDSCL0_VPDSCL_EASF_V_BF3_PWL_SEG1_DEFAULT 0x0000 +#define mmVPDSCL0_VPDSCL_EASF_V_BF3_PWL_SEG1_DEFAULT 0x0000 +#define mmVPDSCL1_VPDSCL_EASF_V_BF3_PWL_SEG1_DEFAULT 0x0000 +#define mmVPDSCL1_VPDSCL_EASF_V_BF3_PWL_SEG1_DEFAULT 0x0000 +#define mmVPDSCL0_VPDSCL_EASF_V_BF3_PWL_SEG2_DEFAULT 0x0000 +#define mmVPDSCL0_VPDSCL_EASF_V_BF3_PWL_SEG2_DEFAULT 0x0000 +#define mmVPDSCL1_VPDSCL_EASF_V_BF3_PWL_SEG2_DEFAULT 0x0000 +#define mmVPDSCL1_VPDSCL_EASF_V_BF3_PWL_SEG2_DEFAULT 0x0000 +#define mmVPDSCL0_VPDSCL_EASF_V_BF3_PWL_SEG3_DEFAULT 0x0000 +#define mmVPDSCL0_VPDSCL_EASF_V_BF3_PWL_SEG3_DEFAULT 0x0000 +#define mmVPDSCL1_VPDSCL_EASF_V_BF3_PWL_SEG3_DEFAULT 0x0000 +#define mmVPDSCL1_VPDSCL_EASF_V_BF3_PWL_SEG3_DEFAULT 0x0000 +#define mmVPDSCL0_VPDSCL_EASF_V_BF3_PWL_SEG4_DEFAULT 0x0000 +#define mmVPDSCL0_VPDSCL_EASF_V_BF3_PWL_SEG4_DEFAULT 0x0000 +#define mmVPDSCL1_VPDSCL_EASF_V_BF3_PWL_SEG4_DEFAULT 0x0000 +#define mmVPDSCL1_VPDSCL_EASF_V_BF3_PWL_SEG4_DEFAULT 0x0000 +#define mmVPDSCL0_VPDSCL_EASF_V_BF3_PWL_SEG5_DEFAULT 0x0000 +#define mmVPDSCL0_VPDSCL_EASF_V_BF3_PWL_SEG5_DEFAULT 0x0000 +#define mmVPDSCL1_VPDSCL_EASF_V_BF3_PWL_SEG5_DEFAULT 0x0000 +#define mmVPDSCL1_VPDSCL_EASF_V_BF3_PWL_SEG5_DEFAULT 0x0000 +#define mmVPDSCL0_VPISHARP_MODE_DEFAULT 0x0000 +#define mmVPDSCL0_VPISHARP_MODE_DEFAULT 0x0000 +#define mmVPDSCL1_VPISHARP_MODE_DEFAULT 0x0000 +#define mmVPDSCL1_VPISHARP_MODE_DEFAULT 0x0000 +#define mmVPDSCL0_VPISHARP_DELTA_CTRL_DEFAULT 0x0000 +#define mmVPDSCL0_VPISHARP_DELTA_CTRL_DEFAULT 0x0000 +#define mmVPDSCL1_VPISHARP_DELTA_CTRL_DEFAULT 0x0000 +#define mmVPDSCL1_VPISHARP_DELTA_CTRL_DEFAULT 0x0000 +#define mmVPDSCL0_VPISHARP_DELTA_INDEX_DEFAULT 0x0000 +#define mmVPDSCL0_VPISHARP_DELTA_INDEX_DEFAULT 0x0000 +#define mmVPDSCL1_VPISHARP_DELTA_INDEX_DEFAULT 0x0000 +#define mmVPDSCL1_VPISHARP_DELTA_INDEX_DEFAULT 0x0000 +#define mmVPDSCL0_VPISHARP_DELTA_DATA_DEFAULT 0x0000 +#define mmVPDSCL0_VPISHARP_DELTA_DATA_DEFAULT 0x0000 +#define mmVPDSCL1_VPISHARP_DELTA_DATA_DEFAULT 0x0000 +#define mmVPDSCL1_VPISHARP_DELTA_DATA_DEFAULT 0x0000 +#define mmVPDSCL0_VPISHARP_NLDELTA_SOFT_CLIP_DEFAULT 0x0000 +#define mmVPDSCL0_VPISHARP_NLDELTA_SOFT_CLIP_DEFAULT 0x0000 +#define mmVPDSCL1_VPISHARP_NLDELTA_SOFT_CLIP_DEFAULT 0x0000 +#define mmVPDSCL1_VPISHARP_NLDELTA_SOFT_CLIP_DEFAULT 0x0000 +#define mmVPDSCL0_VPISHARP_NOISEDET_THRESHOLD_DEFAULT 0x03FF +#define mmVPDSCL0_VPISHARP_NOISEDET_THRESHOLD_DEFAULT 0x03FF +#define mmVPDSCL1_VPISHARP_NOISEDET_THRESHOLD_DEFAULT 0x03FF +#define mmVPDSCL1_VPISHARP_NOISEDET_THRESHOLD_DEFAULT 0x03FF +#define mmVPDSCL0_VPISHARP_NOISE_GAIN_PWL_DEFAULT 0x0000 +#define mmVPDSCL0_VPISHARP_NOISE_GAIN_PWL_DEFAULT 0x0000 +#define mmVPDSCL1_VPISHARP_NOISE_GAIN_PWL_DEFAULT 0x0000 +#define mmVPDSCL1_VPISHARP_NOISE_GAIN_PWL_DEFAULT 0x0000 +#define mmVPDSCL0_VPISHARP_LBA_PWL_SEG0_DEFAULT 0x0000 +#define mmVPDSCL0_VPISHARP_LBA_PWL_SEG0_DEFAULT 0x0000 +#define mmVPDSCL1_VPISHARP_LBA_PWL_SEG0_DEFAULT 0x0000 +#define mmVPDSCL1_VPISHARP_LBA_PWL_SEG0_DEFAULT 0x0000 +#define mmVPDSCL0_VPISHARP_LBA_PWL_SEG1_DEFAULT 0x0000 +#define mmVPDSCL0_VPISHARP_LBA_PWL_SEG1_DEFAULT 0x0000 +#define mmVPDSCL1_VPISHARP_LBA_PWL_SEG1_DEFAULT 0x0000 +#define mmVPDSCL1_VPISHARP_LBA_PWL_SEG1_DEFAULT 0x0000 +#define mmVPDSCL0_VPISHARP_LBA_PWL_SEG2_DEFAULT 0x0000 +#define mmVPDSCL0_VPISHARP_LBA_PWL_SEG2_DEFAULT 0x0000 +#define mmVPDSCL1_VPISHARP_LBA_PWL_SEG2_DEFAULT 0x0000 +#define mmVPDSCL1_VPISHARP_LBA_PWL_SEG2_DEFAULT 0x0000 +#define mmVPDSCL0_VPISHARP_LBA_PWL_SEG3_DEFAULT 0x0000 +#define mmVPDSCL0_VPISHARP_LBA_PWL_SEG3_DEFAULT 0x0000 +#define mmVPDSCL1_VPISHARP_LBA_PWL_SEG3_DEFAULT 0x0000 +#define mmVPDSCL1_VPISHARP_LBA_PWL_SEG3_DEFAULT 0x0000 +#define mmVPDSCL0_VPISHARP_LBA_PWL_SEG4_DEFAULT 0x0000 +#define mmVPDSCL0_VPISHARP_LBA_PWL_SEG4_DEFAULT 0x0000 +#define mmVPDSCL1_VPISHARP_LBA_PWL_SEG4_DEFAULT 0x0000 +#define mmVPDSCL1_VPISHARP_LBA_PWL_SEG4_DEFAULT 0x0000 +#define mmVPDSCL0_VPISHARP_LBA_PWL_SEG5_DEFAULT 0x0000 +#define mmVPDSCL0_VPISHARP_LBA_PWL_SEG5_DEFAULT 0x0000 +#define mmVPDSCL1_VPISHARP_LBA_PWL_SEG5_DEFAULT 0x0000 +#define mmVPDSCL1_VPISHARP_LBA_PWL_SEG5_DEFAULT 0x0000 +#define mmVPDSCL0_VPISHARP_DELTA_LUT_MEM_PWR_CTRL_DEFAULT 0x0000 +#define mmVPDSCL0_VPISHARP_DELTA_LUT_MEM_PWR_CTRL_DEFAULT 0x0000 +#define mmVPDSCL1_VPISHARP_DELTA_LUT_MEM_PWR_CTRL_DEFAULT 0x0000 +#define mmVPDSCL1_VPISHARP_DELTA_LUT_MEM_PWR_CTRL_DEFAULT 0x0000 + + +// Registers from VPCM block + +#define mmVPCM0_VPCM_CONTROL_DEFAULT 0x0000 +#define mmVPCM0_VPCM_CONTROL_DEFAULT 0x0000 +#define mmVPCM1_VPCM_CONTROL_DEFAULT 0x0000 +#define mmVPCM1_VPCM_CONTROL_DEFAULT 0x0000 +#define mmVPCM0_VPCM_POST_CSC_CONTROL_DEFAULT 0x0000 +#define mmVPCM0_VPCM_POST_CSC_CONTROL_DEFAULT 0x0000 +#define mmVPCM1_VPCM_POST_CSC_CONTROL_DEFAULT 0x0000 +#define mmVPCM1_VPCM_POST_CSC_CONTROL_DEFAULT 0x0000 +#define mmVPCM0_VPCM_POST_CSC_C11_C12_DEFAULT 0x2000 +#define mmVPCM0_VPCM_POST_CSC_C11_C12_DEFAULT 0x2000 +#define mmVPCM1_VPCM_POST_CSC_C11_C12_DEFAULT 0x2000 +#define mmVPCM1_VPCM_POST_CSC_C11_C12_DEFAULT 0x2000 +#define mmVPCM0_VPCM_POST_CSC_C13_C14_DEFAULT 0x0000 +#define mmVPCM0_VPCM_POST_CSC_C13_C14_DEFAULT 0x0000 +#define mmVPCM1_VPCM_POST_CSC_C13_C14_DEFAULT 0x0000 +#define mmVPCM1_VPCM_POST_CSC_C13_C14_DEFAULT 0x0000 +#define mmVPCM0_VPCM_POST_CSC_C21_C22_DEFAULT 0x20000000 +#define mmVPCM0_VPCM_POST_CSC_C21_C22_DEFAULT 0x20000000 +#define mmVPCM1_VPCM_POST_CSC_C21_C22_DEFAULT 0x20000000 +#define mmVPCM1_VPCM_POST_CSC_C21_C22_DEFAULT 0x20000000 +#define mmVPCM0_VPCM_POST_CSC_C23_C24_DEFAULT 0x0000 +#define mmVPCM0_VPCM_POST_CSC_C23_C24_DEFAULT 0x0000 +#define mmVPCM1_VPCM_POST_CSC_C23_C24_DEFAULT 0x0000 +#define mmVPCM1_VPCM_POST_CSC_C23_C24_DEFAULT 0x0000 +#define mmVPCM0_VPCM_POST_CSC_C31_C32_DEFAULT 0x0000 +#define mmVPCM0_VPCM_POST_CSC_C31_C32_DEFAULT 0x0000 +#define mmVPCM1_VPCM_POST_CSC_C31_C32_DEFAULT 0x0000 +#define mmVPCM1_VPCM_POST_CSC_C31_C32_DEFAULT 0x0000 +#define mmVPCM0_VPCM_POST_CSC_C33_C34_DEFAULT 0x2000 +#define mmVPCM0_VPCM_POST_CSC_C33_C34_DEFAULT 0x2000 +#define mmVPCM1_VPCM_POST_CSC_C33_C34_DEFAULT 0x2000 +#define mmVPCM1_VPCM_POST_CSC_C33_C34_DEFAULT 0x2000 +#define mmVPCM0_VPCM_BIAS_CR_R_DEFAULT 0x0000 +#define mmVPCM0_VPCM_BIAS_CR_R_DEFAULT 0x0000 +#define mmVPCM1_VPCM_BIAS_CR_R_DEFAULT 0x0000 +#define mmVPCM1_VPCM_BIAS_CR_R_DEFAULT 0x0000 +#define mmVPCM0_VPCM_BIAS_Y_G_CB_B_DEFAULT 0x0000 +#define mmVPCM0_VPCM_BIAS_Y_G_CB_B_DEFAULT 0x0000 +#define mmVPCM1_VPCM_BIAS_Y_G_CB_B_DEFAULT 0x0000 +#define mmVPCM1_VPCM_BIAS_Y_G_CB_B_DEFAULT 0x0000 +#define mmVPCM0_VPCM_GAMCOR_CONTROL_DEFAULT 0x0000 +#define mmVPCM0_VPCM_GAMCOR_CONTROL_DEFAULT 0x0000 +#define mmVPCM1_VPCM_GAMCOR_CONTROL_DEFAULT 0x0000 +#define mmVPCM1_VPCM_GAMCOR_CONTROL_DEFAULT 0x0000 +#define mmVPCM0_VPCM_GAMCOR_LUT_INDEX_DEFAULT 0x0000 +#define mmVPCM0_VPCM_GAMCOR_LUT_INDEX_DEFAULT 0x0000 +#define mmVPCM1_VPCM_GAMCOR_LUT_INDEX_DEFAULT 0x0000 +#define mmVPCM1_VPCM_GAMCOR_LUT_INDEX_DEFAULT 0x0000 +#define mmVPCM0_VPCM_GAMCOR_LUT_DATA_DEFAULT 0x0000 +#define mmVPCM0_VPCM_GAMCOR_LUT_DATA_DEFAULT 0x0000 +#define mmVPCM1_VPCM_GAMCOR_LUT_DATA_DEFAULT 0x0000 +#define mmVPCM1_VPCM_GAMCOR_LUT_DATA_DEFAULT 0x0000 +#define mmVPCM0_VPCM_GAMCOR_LUT_CONTROL_DEFAULT 0x0007 +#define mmVPCM0_VPCM_GAMCOR_LUT_CONTROL_DEFAULT 0x0007 +#define mmVPCM1_VPCM_GAMCOR_LUT_CONTROL_DEFAULT 0x0007 +#define mmVPCM1_VPCM_GAMCOR_LUT_CONTROL_DEFAULT 0x0007 +#define mmVPCM0_VPCM_GAMCOR_RAMA_START_CNTL_B_DEFAULT 0x0000 +#define mmVPCM0_VPCM_GAMCOR_RAMA_START_CNTL_B_DEFAULT 0x0000 +#define mmVPCM1_VPCM_GAMCOR_RAMA_START_CNTL_B_DEFAULT 0x0000 +#define mmVPCM1_VPCM_GAMCOR_RAMA_START_CNTL_B_DEFAULT 0x0000 +#define mmVPCM0_VPCM_GAMCOR_RAMA_START_CNTL_G_DEFAULT 0x0000 +#define mmVPCM0_VPCM_GAMCOR_RAMA_START_CNTL_G_DEFAULT 0x0000 +#define mmVPCM1_VPCM_GAMCOR_RAMA_START_CNTL_G_DEFAULT 0x0000 +#define mmVPCM1_VPCM_GAMCOR_RAMA_START_CNTL_G_DEFAULT 0x0000 +#define mmVPCM0_VPCM_GAMCOR_RAMA_START_CNTL_R_DEFAULT 0x0000 +#define mmVPCM0_VPCM_GAMCOR_RAMA_START_CNTL_R_DEFAULT 0x0000 +#define mmVPCM1_VPCM_GAMCOR_RAMA_START_CNTL_R_DEFAULT 0x0000 +#define mmVPCM1_VPCM_GAMCOR_RAMA_START_CNTL_R_DEFAULT 0x0000 +#define mmVPCM0_VPCM_GAMCOR_RAMA_START_SLOPE_CNTL_B_DEFAULT 0x0000 +#define mmVPCM0_VPCM_GAMCOR_RAMA_START_SLOPE_CNTL_B_DEFAULT 0x0000 +#define mmVPCM1_VPCM_GAMCOR_RAMA_START_SLOPE_CNTL_B_DEFAULT 0x0000 +#define mmVPCM1_VPCM_GAMCOR_RAMA_START_SLOPE_CNTL_B_DEFAULT 0x0000 +#define mmVPCM0_VPCM_GAMCOR_RAMA_START_SLOPE_CNTL_G_DEFAULT 0x0000 +#define mmVPCM0_VPCM_GAMCOR_RAMA_START_SLOPE_CNTL_G_DEFAULT 0x0000 +#define mmVPCM1_VPCM_GAMCOR_RAMA_START_SLOPE_CNTL_G_DEFAULT 0x0000 +#define mmVPCM1_VPCM_GAMCOR_RAMA_START_SLOPE_CNTL_G_DEFAULT 0x0000 +#define mmVPCM0_VPCM_GAMCOR_RAMA_START_SLOPE_CNTL_R_DEFAULT 0x0000 +#define mmVPCM0_VPCM_GAMCOR_RAMA_START_SLOPE_CNTL_R_DEFAULT 0x0000 +#define mmVPCM1_VPCM_GAMCOR_RAMA_START_SLOPE_CNTL_R_DEFAULT 0x0000 +#define mmVPCM1_VPCM_GAMCOR_RAMA_START_SLOPE_CNTL_R_DEFAULT 0x0000 +#define mmVPCM0_VPCM_GAMCOR_RAMA_START_BASE_CNTL_B_DEFAULT 0x0000 +#define mmVPCM0_VPCM_GAMCOR_RAMA_START_BASE_CNTL_B_DEFAULT 0x0000 +#define mmVPCM1_VPCM_GAMCOR_RAMA_START_BASE_CNTL_B_DEFAULT 0x0000 +#define mmVPCM1_VPCM_GAMCOR_RAMA_START_BASE_CNTL_B_DEFAULT 0x0000 +#define mmVPCM0_VPCM_GAMCOR_RAMA_START_BASE_CNTL_G_DEFAULT 0x0000 +#define mmVPCM0_VPCM_GAMCOR_RAMA_START_BASE_CNTL_G_DEFAULT 0x0000 +#define mmVPCM1_VPCM_GAMCOR_RAMA_START_BASE_CNTL_G_DEFAULT 0x0000 +#define mmVPCM1_VPCM_GAMCOR_RAMA_START_BASE_CNTL_G_DEFAULT 0x0000 +#define mmVPCM0_VPCM_GAMCOR_RAMA_START_BASE_CNTL_R_DEFAULT 0x0000 +#define mmVPCM0_VPCM_GAMCOR_RAMA_START_BASE_CNTL_R_DEFAULT 0x0000 +#define mmVPCM1_VPCM_GAMCOR_RAMA_START_BASE_CNTL_R_DEFAULT 0x0000 +#define mmVPCM1_VPCM_GAMCOR_RAMA_START_BASE_CNTL_R_DEFAULT 0x0000 +#define mmVPCM0_VPCM_GAMCOR_RAMA_END_CNTL1_B_DEFAULT 0x0000 +#define mmVPCM0_VPCM_GAMCOR_RAMA_END_CNTL1_B_DEFAULT 0x0000 +#define mmVPCM1_VPCM_GAMCOR_RAMA_END_CNTL1_B_DEFAULT 0x0000 +#define mmVPCM1_VPCM_GAMCOR_RAMA_END_CNTL1_B_DEFAULT 0x0000 +#define mmVPCM0_VPCM_GAMCOR_RAMA_END_CNTL2_B_DEFAULT 0x0000 +#define mmVPCM0_VPCM_GAMCOR_RAMA_END_CNTL2_B_DEFAULT 0x0000 +#define mmVPCM1_VPCM_GAMCOR_RAMA_END_CNTL2_B_DEFAULT 0x0000 +#define mmVPCM1_VPCM_GAMCOR_RAMA_END_CNTL2_B_DEFAULT 0x0000 +#define mmVPCM0_VPCM_GAMCOR_RAMA_END_CNTL1_G_DEFAULT 0x0000 +#define mmVPCM0_VPCM_GAMCOR_RAMA_END_CNTL1_G_DEFAULT 0x0000 +#define mmVPCM1_VPCM_GAMCOR_RAMA_END_CNTL1_G_DEFAULT 0x0000 +#define mmVPCM1_VPCM_GAMCOR_RAMA_END_CNTL1_G_DEFAULT 0x0000 +#define mmVPCM0_VPCM_GAMCOR_RAMA_END_CNTL2_G_DEFAULT 0x0000 +#define mmVPCM0_VPCM_GAMCOR_RAMA_END_CNTL2_G_DEFAULT 0x0000 +#define mmVPCM1_VPCM_GAMCOR_RAMA_END_CNTL2_G_DEFAULT 0x0000 +#define mmVPCM1_VPCM_GAMCOR_RAMA_END_CNTL2_G_DEFAULT 0x0000 +#define mmVPCM0_VPCM_GAMCOR_RAMA_END_CNTL1_R_DEFAULT 0x0000 +#define mmVPCM0_VPCM_GAMCOR_RAMA_END_CNTL1_R_DEFAULT 0x0000 +#define mmVPCM1_VPCM_GAMCOR_RAMA_END_CNTL1_R_DEFAULT 0x0000 +#define mmVPCM1_VPCM_GAMCOR_RAMA_END_CNTL1_R_DEFAULT 0x0000 +#define mmVPCM0_VPCM_GAMCOR_RAMA_END_CNTL2_R_DEFAULT 0x0000 +#define mmVPCM0_VPCM_GAMCOR_RAMA_END_CNTL2_R_DEFAULT 0x0000 +#define mmVPCM1_VPCM_GAMCOR_RAMA_END_CNTL2_R_DEFAULT 0x0000 +#define mmVPCM1_VPCM_GAMCOR_RAMA_END_CNTL2_R_DEFAULT 0x0000 +#define mmVPCM0_VPCM_GAMCOR_RAMA_OFFSET_B_DEFAULT 0x0000 +#define mmVPCM0_VPCM_GAMCOR_RAMA_OFFSET_B_DEFAULT 0x0000 +#define mmVPCM1_VPCM_GAMCOR_RAMA_OFFSET_B_DEFAULT 0x0000 +#define mmVPCM1_VPCM_GAMCOR_RAMA_OFFSET_B_DEFAULT 0x0000 +#define mmVPCM0_VPCM_GAMCOR_RAMA_OFFSET_G_DEFAULT 0x0000 +#define mmVPCM0_VPCM_GAMCOR_RAMA_OFFSET_G_DEFAULT 0x0000 +#define mmVPCM1_VPCM_GAMCOR_RAMA_OFFSET_G_DEFAULT 0x0000 +#define mmVPCM1_VPCM_GAMCOR_RAMA_OFFSET_G_DEFAULT 0x0000 +#define mmVPCM0_VPCM_GAMCOR_RAMA_OFFSET_R_DEFAULT 0x0000 +#define mmVPCM0_VPCM_GAMCOR_RAMA_OFFSET_R_DEFAULT 0x0000 +#define mmVPCM1_VPCM_GAMCOR_RAMA_OFFSET_R_DEFAULT 0x0000 +#define mmVPCM1_VPCM_GAMCOR_RAMA_OFFSET_R_DEFAULT 0x0000 +#define mmVPCM0_VPCM_GAMCOR_RAMA_REGION_0_1_DEFAULT 0x0000 +#define mmVPCM0_VPCM_GAMCOR_RAMA_REGION_0_1_DEFAULT 0x0000 +#define mmVPCM1_VPCM_GAMCOR_RAMA_REGION_0_1_DEFAULT 0x0000 +#define mmVPCM1_VPCM_GAMCOR_RAMA_REGION_0_1_DEFAULT 0x0000 +#define mmVPCM0_VPCM_GAMCOR_RAMA_REGION_2_3_DEFAULT 0x0000 +#define mmVPCM0_VPCM_GAMCOR_RAMA_REGION_2_3_DEFAULT 0x0000 +#define mmVPCM1_VPCM_GAMCOR_RAMA_REGION_2_3_DEFAULT 0x0000 +#define mmVPCM1_VPCM_GAMCOR_RAMA_REGION_2_3_DEFAULT 0x0000 +#define mmVPCM0_VPCM_GAMCOR_RAMA_REGION_4_5_DEFAULT 0x0000 +#define mmVPCM0_VPCM_GAMCOR_RAMA_REGION_4_5_DEFAULT 0x0000 +#define mmVPCM1_VPCM_GAMCOR_RAMA_REGION_4_5_DEFAULT 0x0000 +#define mmVPCM1_VPCM_GAMCOR_RAMA_REGION_4_5_DEFAULT 0x0000 +#define mmVPCM0_VPCM_GAMCOR_RAMA_REGION_6_7_DEFAULT 0x0000 +#define mmVPCM0_VPCM_GAMCOR_RAMA_REGION_6_7_DEFAULT 0x0000 +#define mmVPCM1_VPCM_GAMCOR_RAMA_REGION_6_7_DEFAULT 0x0000 +#define mmVPCM1_VPCM_GAMCOR_RAMA_REGION_6_7_DEFAULT 0x0000 +#define mmVPCM0_VPCM_GAMCOR_RAMA_REGION_8_9_DEFAULT 0x0000 +#define mmVPCM0_VPCM_GAMCOR_RAMA_REGION_8_9_DEFAULT 0x0000 +#define mmVPCM1_VPCM_GAMCOR_RAMA_REGION_8_9_DEFAULT 0x0000 +#define mmVPCM1_VPCM_GAMCOR_RAMA_REGION_8_9_DEFAULT 0x0000 +#define mmVPCM0_VPCM_GAMCOR_RAMA_REGION_10_11_DEFAULT 0x0000 +#define mmVPCM0_VPCM_GAMCOR_RAMA_REGION_10_11_DEFAULT 0x0000 +#define mmVPCM1_VPCM_GAMCOR_RAMA_REGION_10_11_DEFAULT 0x0000 +#define mmVPCM1_VPCM_GAMCOR_RAMA_REGION_10_11_DEFAULT 0x0000 +#define mmVPCM0_VPCM_GAMCOR_RAMA_REGION_12_13_DEFAULT 0x0000 +#define mmVPCM0_VPCM_GAMCOR_RAMA_REGION_12_13_DEFAULT 0x0000 +#define mmVPCM1_VPCM_GAMCOR_RAMA_REGION_12_13_DEFAULT 0x0000 +#define mmVPCM1_VPCM_GAMCOR_RAMA_REGION_12_13_DEFAULT 0x0000 +#define mmVPCM0_VPCM_GAMCOR_RAMA_REGION_14_15_DEFAULT 0x0000 +#define mmVPCM0_VPCM_GAMCOR_RAMA_REGION_14_15_DEFAULT 0x0000 +#define mmVPCM1_VPCM_GAMCOR_RAMA_REGION_14_15_DEFAULT 0x0000 +#define mmVPCM1_VPCM_GAMCOR_RAMA_REGION_14_15_DEFAULT 0x0000 +#define mmVPCM0_VPCM_GAMCOR_RAMA_REGION_16_17_DEFAULT 0x0000 +#define mmVPCM0_VPCM_GAMCOR_RAMA_REGION_16_17_DEFAULT 0x0000 +#define mmVPCM1_VPCM_GAMCOR_RAMA_REGION_16_17_DEFAULT 0x0000 +#define mmVPCM1_VPCM_GAMCOR_RAMA_REGION_16_17_DEFAULT 0x0000 +#define mmVPCM0_VPCM_GAMCOR_RAMA_REGION_18_19_DEFAULT 0x0000 +#define mmVPCM0_VPCM_GAMCOR_RAMA_REGION_18_19_DEFAULT 0x0000 +#define mmVPCM1_VPCM_GAMCOR_RAMA_REGION_18_19_DEFAULT 0x0000 +#define mmVPCM1_VPCM_GAMCOR_RAMA_REGION_18_19_DEFAULT 0x0000 +#define mmVPCM0_VPCM_GAMCOR_RAMA_REGION_20_21_DEFAULT 0x0000 +#define mmVPCM0_VPCM_GAMCOR_RAMA_REGION_20_21_DEFAULT 0x0000 +#define mmVPCM1_VPCM_GAMCOR_RAMA_REGION_20_21_DEFAULT 0x0000 +#define mmVPCM1_VPCM_GAMCOR_RAMA_REGION_20_21_DEFAULT 0x0000 +#define mmVPCM0_VPCM_GAMCOR_RAMA_REGION_22_23_DEFAULT 0x0000 +#define mmVPCM0_VPCM_GAMCOR_RAMA_REGION_22_23_DEFAULT 0x0000 +#define mmVPCM1_VPCM_GAMCOR_RAMA_REGION_22_23_DEFAULT 0x0000 +#define mmVPCM1_VPCM_GAMCOR_RAMA_REGION_22_23_DEFAULT 0x0000 +#define mmVPCM0_VPCM_GAMCOR_RAMA_REGION_24_25_DEFAULT 0x0000 +#define mmVPCM0_VPCM_GAMCOR_RAMA_REGION_24_25_DEFAULT 0x0000 +#define mmVPCM1_VPCM_GAMCOR_RAMA_REGION_24_25_DEFAULT 0x0000 +#define mmVPCM1_VPCM_GAMCOR_RAMA_REGION_24_25_DEFAULT 0x0000 +#define mmVPCM0_VPCM_GAMCOR_RAMA_REGION_26_27_DEFAULT 0x0000 +#define mmVPCM0_VPCM_GAMCOR_RAMA_REGION_26_27_DEFAULT 0x0000 +#define mmVPCM1_VPCM_GAMCOR_RAMA_REGION_26_27_DEFAULT 0x0000 +#define mmVPCM1_VPCM_GAMCOR_RAMA_REGION_26_27_DEFAULT 0x0000 +#define mmVPCM0_VPCM_GAMCOR_RAMA_REGION_28_29_DEFAULT 0x0000 +#define mmVPCM0_VPCM_GAMCOR_RAMA_REGION_28_29_DEFAULT 0x0000 +#define mmVPCM1_VPCM_GAMCOR_RAMA_REGION_28_29_DEFAULT 0x0000 +#define mmVPCM1_VPCM_GAMCOR_RAMA_REGION_28_29_DEFAULT 0x0000 +#define mmVPCM0_VPCM_GAMCOR_RAMA_REGION_30_31_DEFAULT 0x0000 +#define mmVPCM0_VPCM_GAMCOR_RAMA_REGION_30_31_DEFAULT 0x0000 +#define mmVPCM1_VPCM_GAMCOR_RAMA_REGION_30_31_DEFAULT 0x0000 +#define mmVPCM1_VPCM_GAMCOR_RAMA_REGION_30_31_DEFAULT 0x0000 +#define mmVPCM0_VPCM_GAMCOR_RAMA_REGION_32_33_DEFAULT 0x0000 +#define mmVPCM0_VPCM_GAMCOR_RAMA_REGION_32_33_DEFAULT 0x0000 +#define mmVPCM1_VPCM_GAMCOR_RAMA_REGION_32_33_DEFAULT 0x0000 +#define mmVPCM1_VPCM_GAMCOR_RAMA_REGION_32_33_DEFAULT 0x0000 +#define mmVPCM0_VPCM_HDR_MULT_COEF_DEFAULT 0x1F000 +#define mmVPCM0_VPCM_HDR_MULT_COEF_DEFAULT 0x1F000 +#define mmVPCM1_VPCM_HDR_MULT_COEF_DEFAULT 0x1F000 +#define mmVPCM1_VPCM_HDR_MULT_COEF_DEFAULT 0x1F000 +#define mmVPCM0_VPCM_MEM_PWR_CTRL_DEFAULT 0x0000 +#define mmVPCM0_VPCM_MEM_PWR_CTRL_DEFAULT 0x0000 +#define mmVPCM1_VPCM_MEM_PWR_CTRL_DEFAULT 0x0000 +#define mmVPCM1_VPCM_MEM_PWR_CTRL_DEFAULT 0x0000 +#define mmVPCM0_VPCM_MEM_PWR_STATUS_DEFAULT 0x0000 +#define mmVPCM0_VPCM_MEM_PWR_STATUS_DEFAULT 0x0000 +#define mmVPCM1_VPCM_MEM_PWR_STATUS_DEFAULT 0x0000 +#define mmVPCM1_VPCM_MEM_PWR_STATUS_DEFAULT 0x0000 +#define mmVPCM0_VPCM_DEALPHA_DEFAULT 0x0000 +#define mmVPCM0_VPCM_DEALPHA_DEFAULT 0x0000 +#define mmVPCM1_VPCM_DEALPHA_DEFAULT 0x0000 +#define mmVPCM1_VPCM_DEALPHA_DEFAULT 0x0000 +#define mmVPCM0_VPCM_COEF_FORMAT_DEFAULT 0x0000 +#define mmVPCM0_VPCM_COEF_FORMAT_DEFAULT 0x0000 +#define mmVPCM1_VPCM_COEF_FORMAT_DEFAULT 0x0000 +#define mmVPCM1_VPCM_COEF_FORMAT_DEFAULT 0x0000 +#define mmVPCM0_VPCM_HIST_CNTL_DEFAULT 0x1200 +#define mmVPCM0_VPCM_HIST_CNTL_DEFAULT 0x1200 +#define mmVPCM1_VPCM_HIST_CNTL_DEFAULT 0x1200 +#define mmVPCM1_VPCM_HIST_CNTL_DEFAULT 0x1200 +#define mmVPCM0_VPCM_HIST_SCALE_SRC1_DEFAULT 0x1F000 +#define mmVPCM0_VPCM_HIST_SCALE_SRC1_DEFAULT 0x1F000 +#define mmVPCM1_VPCM_HIST_SCALE_SRC1_DEFAULT 0x1F000 +#define mmVPCM1_VPCM_HIST_SCALE_SRC1_DEFAULT 0x1F000 +#define mmVPCM0_VPCM_HIST_COEFA_SRC2_DEFAULT 0x1F000 +#define mmVPCM0_VPCM_HIST_COEFA_SRC2_DEFAULT 0x1F000 +#define mmVPCM1_VPCM_HIST_COEFA_SRC2_DEFAULT 0x1F000 +#define mmVPCM1_VPCM_HIST_COEFA_SRC2_DEFAULT 0x1F000 +#define mmVPCM0_VPCM_HIST_COEFB_SRC2_DEFAULT 0x1F000 +#define mmVPCM0_VPCM_HIST_COEFB_SRC2_DEFAULT 0x1F000 +#define mmVPCM1_VPCM_HIST_COEFB_SRC2_DEFAULT 0x1F000 +#define mmVPCM1_VPCM_HIST_COEFB_SRC2_DEFAULT 0x1F000 +#define mmVPCM0_VPCM_HIST_COEFC_SRC2_DEFAULT 0x1F000 +#define mmVPCM0_VPCM_HIST_COEFC_SRC2_DEFAULT 0x1F000 +#define mmVPCM1_VPCM_HIST_COEFC_SRC2_DEFAULT 0x1F000 +#define mmVPCM1_VPCM_HIST_COEFC_SRC2_DEFAULT 0x1F000 +#define mmVPCM0_VPCM_HIST_SCALE_SRC3_DEFAULT 0x1F000 +#define mmVPCM0_VPCM_HIST_SCALE_SRC3_DEFAULT 0x1F000 +#define mmVPCM1_VPCM_HIST_SCALE_SRC3_DEFAULT 0x1F000 +#define mmVPCM1_VPCM_HIST_SCALE_SRC3_DEFAULT 0x1F000 +#define mmVPCM0_VPCM_HIST_BIAS_SRC1_DEFAULT 0x0000 +#define mmVPCM0_VPCM_HIST_BIAS_SRC1_DEFAULT 0x0000 +#define mmVPCM1_VPCM_HIST_BIAS_SRC1_DEFAULT 0x0000 +#define mmVPCM1_VPCM_HIST_BIAS_SRC1_DEFAULT 0x0000 +#define mmVPCM0_VPCM_HIST_BIAS_SRC2_DEFAULT 0x0000 +#define mmVPCM0_VPCM_HIST_BIAS_SRC2_DEFAULT 0x0000 +#define mmVPCM1_VPCM_HIST_BIAS_SRC2_DEFAULT 0x0000 +#define mmVPCM1_VPCM_HIST_BIAS_SRC2_DEFAULT 0x0000 +#define mmVPCM0_VPCM_HIST_BIAS_SRC3_DEFAULT 0x0000 +#define mmVPCM0_VPCM_HIST_BIAS_SRC3_DEFAULT 0x0000 +#define mmVPCM1_VPCM_HIST_BIAS_SRC3_DEFAULT 0x0000 +#define mmVPCM1_VPCM_HIST_BIAS_SRC3_DEFAULT 0x0000 + + +// Registers from VPDPP_TOP block + +#define mmVPDPP_TOP0_VPDPP_CONTROL_DEFAULT 0x70000000 +#define mmVPDPP_TOP0_VPDPP_CONTROL_DEFAULT 0x70000000 +#define mmVPDPP_TOP1_VPDPP_CONTROL_DEFAULT 0x70000000 +#define mmVPDPP_TOP1_VPDPP_CONTROL_DEFAULT 0x70000000 +#define mmVPDPP_TOP0_VPDPP_CRC_CTRL_DEFAULT 0x0000 +#define mmVPDPP_TOP0_VPDPP_CRC_CTRL_DEFAULT 0x0000 +#define mmVPDPP_TOP1_VPDPP_CRC_CTRL_DEFAULT 0x0000 +#define mmVPDPP_TOP1_VPDPP_CRC_CTRL_DEFAULT 0x0000 + + +// Registers from VPMPC_CFG block + +#define mmVPMPC_CLOCK_CONTROL_DEFAULT 0x0000 +#define mmVPMPC_SOFT_RESET_DEFAULT 0x0000 +#define mmVPMPC_CRC_CTRL_DEFAULT 0x0000 +#define mmVPMPC_CRC_SEL_CONTROL_DEFAULT 0x0000 +#define mmVPMPC_CRC_RESULT_AR_DEFAULT 0x0000 +#define mmVPMPC_CRC_RESULT_GB_DEFAULT 0x0000 +#define mmVPMPC_CRC_RESULT_C_DEFAULT 0x0000 +#define mmVPMPC_BYPASS_BG_AR_DEFAULT 0x0000 +#define mmVPMPC_BYPASS_BG_GB_DEFAULT 0x0000 +#define mmVPMPC_HOST_READ_CONTROL_DEFAULT 0x0000 +#define mmVPMPC_PENDING_STATUS_MISC_DEFAULT 0x0000 +#define mmVPMPC_VPCDC0_3DLUT_FL_CONFIG_DEFAULT 0x0000 +#define mmVPMPC_VPCDC0_3DLUT_FL_BIAS_SCALE_DEFAULT 0x0000 + + +// Registers from VPMPC_OCSC block + +#define mmVPMPC_OUT0_MUX_DEFAULT 0x000F +#define mmVPMPC_OUT0_FLOAT_CONTROL_DEFAULT 0x0000 +#define mmVPMPC_OUT0_DENORM_CONTROL_DEFAULT 0xFFF000 +#define mmVPMPC_OUT0_DENORM_CLAMP_G_Y_DEFAULT 0xFFF000 +#define mmVPMPC_OUT0_DENORM_CLAMP_B_CB_DEFAULT 0xFFF000 +#define mmVPMPC_OUT1_MUX_DEFAULT 0x000F +#define mmVPMPC_OUT1_FLOAT_CONTROL_DEFAULT 0x0000 +#define mmVPMPC_OUT1_DENORM_CONTROL_DEFAULT 0xFFF000 +#define mmVPMPC_OUT1_DENORM_CLAMP_G_Y_DEFAULT 0xFFF000 +#define mmVPMPC_OUT1_DENORM_CLAMP_B_CB_DEFAULT 0xFFF000 +#define mmVPMPC_OUT_CSC_COEF_FORMAT_DEFAULT 0x0000 +#define mmVPMPC_OUT0_CSC_MODE_DEFAULT 0x0000 +#define mmVPMPC_OUT0_CSC_C11_C12_A_DEFAULT 0x0000 +#define mmVPMPC_OUT0_CSC_C13_C14_A_DEFAULT 0x0000 +#define mmVPMPC_OUT0_CSC_C21_C22_A_DEFAULT 0x0000 +#define mmVPMPC_OUT0_CSC_C23_C24_A_DEFAULT 0x0000 +#define mmVPMPC_OUT0_CSC_C31_C32_A_DEFAULT 0x0000 +#define mmVPMPC_OUT0_CSC_C33_C34_A_DEFAULT 0x0000 +#define mmVPMPC_OUT1_CSC_MODE_DEFAULT 0x0000 +#define mmVPMPC_OUT1_CSC_C11_C12_A_DEFAULT 0x0000 +#define mmVPMPC_OUT1_CSC_C13_C14_A_DEFAULT 0x0000 +#define mmVPMPC_OUT1_CSC_C21_C22_A_DEFAULT 0x0000 +#define mmVPMPC_OUT1_CSC_C23_C24_A_DEFAULT 0x0000 +#define mmVPMPC_OUT1_CSC_C31_C32_A_DEFAULT 0x0000 +#define mmVPMPC_OUT1_CSC_C33_C34_A_DEFAULT 0x0000 + + +// Registers from VPMPCC block + +#define mmVPMPCC0_VPMPCC_TOP_SEL_DEFAULT 0x000F +#define mmVPMPCC0_VPMPCC_TOP_SEL_DEFAULT 0x000F +#define mmVPMPCC1_VPMPCC_TOP_SEL_DEFAULT 0x000F +#define mmVPMPCC1_VPMPCC_TOP_SEL_DEFAULT 0x000F +#define mmVPMPCC0_VPMPCC_BOT_SEL_DEFAULT 0x000F +#define mmVPMPCC0_VPMPCC_BOT_SEL_DEFAULT 0x000F +#define mmVPMPCC1_VPMPCC_BOT_SEL_DEFAULT 0x000F +#define mmVPMPCC1_VPMPCC_BOT_SEL_DEFAULT 0x000F +#define mmVPMPCC0_VPMPCC_VPOPP_ID_DEFAULT 0x000F +#define mmVPMPCC0_VPMPCC_VPOPP_ID_DEFAULT 0x000F +#define mmVPMPCC1_VPMPCC_VPOPP_ID_DEFAULT 0x000F +#define mmVPMPCC1_VPMPCC_VPOPP_ID_DEFAULT 0x000F +#define mmVPMPCC0_VPMPCC_CONTROL_DEFAULT 0x0061 +#define mmVPMPCC0_VPMPCC_CONTROL_DEFAULT 0x0061 +#define mmVPMPCC1_VPMPCC_CONTROL_DEFAULT 0x0061 +#define mmVPMPCC1_VPMPCC_CONTROL_DEFAULT 0x0061 +#define mmVPMPCC0_VPMPCC_CONTROL2_DEFAULT 0xFFF0FFF +#define mmVPMPCC0_VPMPCC_CONTROL2_DEFAULT 0xFFF0FFF +#define mmVPMPCC1_VPMPCC_CONTROL2_DEFAULT 0xFFF0FFF +#define mmVPMPCC1_VPMPCC_CONTROL2_DEFAULT 0xFFF0FFF +#define mmVPMPCC0_VPMPCC_TOP_GAIN_DEFAULT 0x1F000 +#define mmVPMPCC0_VPMPCC_TOP_GAIN_DEFAULT 0x1F000 +#define mmVPMPCC1_VPMPCC_TOP_GAIN_DEFAULT 0x1F000 +#define mmVPMPCC1_VPMPCC_TOP_GAIN_DEFAULT 0x1F000 +#define mmVPMPCC0_VPMPCC_BOT_GAIN_INSIDE_DEFAULT 0x1F000 +#define mmVPMPCC0_VPMPCC_BOT_GAIN_INSIDE_DEFAULT 0x1F000 +#define mmVPMPCC1_VPMPCC_BOT_GAIN_INSIDE_DEFAULT 0x1F000 +#define mmVPMPCC1_VPMPCC_BOT_GAIN_INSIDE_DEFAULT 0x1F000 +#define mmVPMPCC0_VPMPCC_BOT_GAIN_OUTSIDE_DEFAULT 0x1F000 +#define mmVPMPCC0_VPMPCC_BOT_GAIN_OUTSIDE_DEFAULT 0x1F000 +#define mmVPMPCC1_VPMPCC_BOT_GAIN_OUTSIDE_DEFAULT 0x1F000 +#define mmVPMPCC1_VPMPCC_BOT_GAIN_OUTSIDE_DEFAULT 0x1F000 +#define mmVPMPCC0_VPMPCC_MOVABLE_CM_LOCATION_CONTROL_DEFAULT 0x0001 +#define mmVPMPCC0_VPMPCC_MOVABLE_CM_LOCATION_CONTROL_DEFAULT 0x0001 +#define mmVPMPCC1_VPMPCC_MOVABLE_CM_LOCATION_CONTROL_DEFAULT 0x0001 +#define mmVPMPCC1_VPMPCC_MOVABLE_CM_LOCATION_CONTROL_DEFAULT 0x0001 +#define mmVPMPCC0_VPMPCC_BG_R_CR_DEFAULT 0x0000 +#define mmVPMPCC0_VPMPCC_BG_R_CR_DEFAULT 0x0000 +#define mmVPMPCC1_VPMPCC_BG_R_CR_DEFAULT 0x0000 +#define mmVPMPCC1_VPMPCC_BG_R_CR_DEFAULT 0x0000 +#define mmVPMPCC0_VPMPCC_BG_G_Y_DEFAULT 0x0000 +#define mmVPMPCC0_VPMPCC_BG_G_Y_DEFAULT 0x0000 +#define mmVPMPCC1_VPMPCC_BG_G_Y_DEFAULT 0x0000 +#define mmVPMPCC1_VPMPCC_BG_G_Y_DEFAULT 0x0000 +#define mmVPMPCC0_VPMPCC_BG_B_CB_DEFAULT 0x0000 +#define mmVPMPCC0_VPMPCC_BG_B_CB_DEFAULT 0x0000 +#define mmVPMPCC1_VPMPCC_BG_B_CB_DEFAULT 0x0000 +#define mmVPMPCC1_VPMPCC_BG_B_CB_DEFAULT 0x0000 +#define mmVPMPCC0_VPMPCC_MEM_PWR_CTRL_DEFAULT 0x0010 +#define mmVPMPCC0_VPMPCC_MEM_PWR_CTRL_DEFAULT 0x0010 +#define mmVPMPCC1_VPMPCC_MEM_PWR_CTRL_DEFAULT 0x0010 +#define mmVPMPCC1_VPMPCC_MEM_PWR_CTRL_DEFAULT 0x0010 +#define mmVPMPCC0_VPMPCC_STATUS_DEFAULT 0x0000 +#define mmVPMPCC0_VPMPCC_STATUS_DEFAULT 0x0000 +#define mmVPMPCC1_VPMPCC_STATUS_DEFAULT 0x0000 +#define mmVPMPCC1_VPMPCC_STATUS_DEFAULT 0x0000 + + +// Registers from VPMPCC_OGAM block + +#define mmVPMPCC_OGAM0_VPMPCC_OGAM_CONTROL_DEFAULT 0x0000 +#define mmVPMPCC_OGAM0_VPMPCC_OGAM_CONTROL_DEFAULT 0x0000 +#define mmVPMPCC_OGAM1_VPMPCC_OGAM_CONTROL_DEFAULT 0x0000 +#define mmVPMPCC_OGAM1_VPMPCC_OGAM_CONTROL_DEFAULT 0x0000 +#define mmVPMPCC_OGAM0_VPMPCC_OGAM_LUT_INDEX_DEFAULT 0x0000 +#define mmVPMPCC_OGAM0_VPMPCC_OGAM_LUT_INDEX_DEFAULT 0x0000 +#define mmVPMPCC_OGAM1_VPMPCC_OGAM_LUT_INDEX_DEFAULT 0x0000 +#define mmVPMPCC_OGAM1_VPMPCC_OGAM_LUT_INDEX_DEFAULT 0x0000 +#define mmVPMPCC_OGAM0_VPMPCC_OGAM_LUT_DATA_DEFAULT 0x0000 +#define mmVPMPCC_OGAM0_VPMPCC_OGAM_LUT_DATA_DEFAULT 0x0000 +#define mmVPMPCC_OGAM1_VPMPCC_OGAM_LUT_DATA_DEFAULT 0x0000 +#define mmVPMPCC_OGAM1_VPMPCC_OGAM_LUT_DATA_DEFAULT 0x0000 +#define mmVPMPCC_OGAM0_VPMPCC_OGAM_LUT_CONTROL_DEFAULT 0x0007 +#define mmVPMPCC_OGAM0_VPMPCC_OGAM_LUT_CONTROL_DEFAULT 0x0007 +#define mmVPMPCC_OGAM1_VPMPCC_OGAM_LUT_CONTROL_DEFAULT 0x0007 +#define mmVPMPCC_OGAM1_VPMPCC_OGAM_LUT_CONTROL_DEFAULT 0x0007 +#define mmVPMPCC_OGAM0_VPMPCC_OGAM_RAMA_START_CNTL_B_DEFAULT 0x0000 +#define mmVPMPCC_OGAM0_VPMPCC_OGAM_RAMA_START_CNTL_B_DEFAULT 0x0000 +#define mmVPMPCC_OGAM1_VPMPCC_OGAM_RAMA_START_CNTL_B_DEFAULT 0x0000 +#define mmVPMPCC_OGAM1_VPMPCC_OGAM_RAMA_START_CNTL_B_DEFAULT 0x0000 +#define mmVPMPCC_OGAM0_VPMPCC_OGAM_RAMA_START_CNTL_G_DEFAULT 0x0000 +#define mmVPMPCC_OGAM0_VPMPCC_OGAM_RAMA_START_CNTL_G_DEFAULT 0x0000 +#define mmVPMPCC_OGAM1_VPMPCC_OGAM_RAMA_START_CNTL_G_DEFAULT 0x0000 +#define mmVPMPCC_OGAM1_VPMPCC_OGAM_RAMA_START_CNTL_G_DEFAULT 0x0000 +#define mmVPMPCC_OGAM0_VPMPCC_OGAM_RAMA_START_CNTL_R_DEFAULT 0x0000 +#define mmVPMPCC_OGAM0_VPMPCC_OGAM_RAMA_START_CNTL_R_DEFAULT 0x0000 +#define mmVPMPCC_OGAM1_VPMPCC_OGAM_RAMA_START_CNTL_R_DEFAULT 0x0000 +#define mmVPMPCC_OGAM1_VPMPCC_OGAM_RAMA_START_CNTL_R_DEFAULT 0x0000 +#define mmVPMPCC_OGAM0_VPMPCC_OGAM_RAMA_START_SLOPE_CNTL_B_DEFAULT 0x0000 +#define mmVPMPCC_OGAM0_VPMPCC_OGAM_RAMA_START_SLOPE_CNTL_B_DEFAULT 0x0000 +#define mmVPMPCC_OGAM1_VPMPCC_OGAM_RAMA_START_SLOPE_CNTL_B_DEFAULT 0x0000 +#define mmVPMPCC_OGAM1_VPMPCC_OGAM_RAMA_START_SLOPE_CNTL_B_DEFAULT 0x0000 +#define mmVPMPCC_OGAM0_VPMPCC_OGAM_RAMA_START_SLOPE_CNTL_G_DEFAULT 0x0000 +#define mmVPMPCC_OGAM0_VPMPCC_OGAM_RAMA_START_SLOPE_CNTL_G_DEFAULT 0x0000 +#define mmVPMPCC_OGAM1_VPMPCC_OGAM_RAMA_START_SLOPE_CNTL_G_DEFAULT 0x0000 +#define mmVPMPCC_OGAM1_VPMPCC_OGAM_RAMA_START_SLOPE_CNTL_G_DEFAULT 0x0000 +#define mmVPMPCC_OGAM0_VPMPCC_OGAM_RAMA_START_SLOPE_CNTL_R_DEFAULT 0x0000 +#define mmVPMPCC_OGAM0_VPMPCC_OGAM_RAMA_START_SLOPE_CNTL_R_DEFAULT 0x0000 +#define mmVPMPCC_OGAM1_VPMPCC_OGAM_RAMA_START_SLOPE_CNTL_R_DEFAULT 0x0000 +#define mmVPMPCC_OGAM1_VPMPCC_OGAM_RAMA_START_SLOPE_CNTL_R_DEFAULT 0x0000 +#define mmVPMPCC_OGAM0_VPMPCC_OGAM_RAMA_START_BASE_CNTL_B_DEFAULT 0x0000 +#define mmVPMPCC_OGAM0_VPMPCC_OGAM_RAMA_START_BASE_CNTL_B_DEFAULT 0x0000 +#define mmVPMPCC_OGAM1_VPMPCC_OGAM_RAMA_START_BASE_CNTL_B_DEFAULT 0x0000 +#define mmVPMPCC_OGAM1_VPMPCC_OGAM_RAMA_START_BASE_CNTL_B_DEFAULT 0x0000 +#define mmVPMPCC_OGAM0_VPMPCC_OGAM_RAMA_START_BASE_CNTL_G_DEFAULT 0x0000 +#define mmVPMPCC_OGAM0_VPMPCC_OGAM_RAMA_START_BASE_CNTL_G_DEFAULT 0x0000 +#define mmVPMPCC_OGAM1_VPMPCC_OGAM_RAMA_START_BASE_CNTL_G_DEFAULT 0x0000 +#define mmVPMPCC_OGAM1_VPMPCC_OGAM_RAMA_START_BASE_CNTL_G_DEFAULT 0x0000 +#define mmVPMPCC_OGAM0_VPMPCC_OGAM_RAMA_START_BASE_CNTL_R_DEFAULT 0x0000 +#define mmVPMPCC_OGAM0_VPMPCC_OGAM_RAMA_START_BASE_CNTL_R_DEFAULT 0x0000 +#define mmVPMPCC_OGAM1_VPMPCC_OGAM_RAMA_START_BASE_CNTL_R_DEFAULT 0x0000 +#define mmVPMPCC_OGAM1_VPMPCC_OGAM_RAMA_START_BASE_CNTL_R_DEFAULT 0x0000 +#define mmVPMPCC_OGAM0_VPMPCC_OGAM_RAMA_END_CNTL1_B_DEFAULT 0x0000 +#define mmVPMPCC_OGAM0_VPMPCC_OGAM_RAMA_END_CNTL1_B_DEFAULT 0x0000 +#define mmVPMPCC_OGAM1_VPMPCC_OGAM_RAMA_END_CNTL1_B_DEFAULT 0x0000 +#define mmVPMPCC_OGAM1_VPMPCC_OGAM_RAMA_END_CNTL1_B_DEFAULT 0x0000 +#define mmVPMPCC_OGAM0_VPMPCC_OGAM_RAMA_END_CNTL2_B_DEFAULT 0x0000 +#define mmVPMPCC_OGAM0_VPMPCC_OGAM_RAMA_END_CNTL2_B_DEFAULT 0x0000 +#define mmVPMPCC_OGAM1_VPMPCC_OGAM_RAMA_END_CNTL2_B_DEFAULT 0x0000 +#define mmVPMPCC_OGAM1_VPMPCC_OGAM_RAMA_END_CNTL2_B_DEFAULT 0x0000 +#define mmVPMPCC_OGAM0_VPMPCC_OGAM_RAMA_END_CNTL1_G_DEFAULT 0x0000 +#define mmVPMPCC_OGAM0_VPMPCC_OGAM_RAMA_END_CNTL1_G_DEFAULT 0x0000 +#define mmVPMPCC_OGAM1_VPMPCC_OGAM_RAMA_END_CNTL1_G_DEFAULT 0x0000 +#define mmVPMPCC_OGAM1_VPMPCC_OGAM_RAMA_END_CNTL1_G_DEFAULT 0x0000 +#define mmVPMPCC_OGAM0_VPMPCC_OGAM_RAMA_END_CNTL2_G_DEFAULT 0x0000 +#define mmVPMPCC_OGAM0_VPMPCC_OGAM_RAMA_END_CNTL2_G_DEFAULT 0x0000 +#define mmVPMPCC_OGAM1_VPMPCC_OGAM_RAMA_END_CNTL2_G_DEFAULT 0x0000 +#define mmVPMPCC_OGAM1_VPMPCC_OGAM_RAMA_END_CNTL2_G_DEFAULT 0x0000 +#define mmVPMPCC_OGAM0_VPMPCC_OGAM_RAMA_END_CNTL1_R_DEFAULT 0x0000 +#define mmVPMPCC_OGAM0_VPMPCC_OGAM_RAMA_END_CNTL1_R_DEFAULT 0x0000 +#define mmVPMPCC_OGAM1_VPMPCC_OGAM_RAMA_END_CNTL1_R_DEFAULT 0x0000 +#define mmVPMPCC_OGAM1_VPMPCC_OGAM_RAMA_END_CNTL1_R_DEFAULT 0x0000 +#define mmVPMPCC_OGAM0_VPMPCC_OGAM_RAMA_END_CNTL2_R_DEFAULT 0x0000 +#define mmVPMPCC_OGAM0_VPMPCC_OGAM_RAMA_END_CNTL2_R_DEFAULT 0x0000 +#define mmVPMPCC_OGAM1_VPMPCC_OGAM_RAMA_END_CNTL2_R_DEFAULT 0x0000 +#define mmVPMPCC_OGAM1_VPMPCC_OGAM_RAMA_END_CNTL2_R_DEFAULT 0x0000 +#define mmVPMPCC_OGAM0_VPMPCC_OGAM_RAMA_OFFSET_B_DEFAULT 0x0000 +#define mmVPMPCC_OGAM0_VPMPCC_OGAM_RAMA_OFFSET_B_DEFAULT 0x0000 +#define mmVPMPCC_OGAM1_VPMPCC_OGAM_RAMA_OFFSET_B_DEFAULT 0x0000 +#define mmVPMPCC_OGAM1_VPMPCC_OGAM_RAMA_OFFSET_B_DEFAULT 0x0000 +#define mmVPMPCC_OGAM0_VPMPCC_OGAM_RAMA_OFFSET_G_DEFAULT 0x0000 +#define mmVPMPCC_OGAM0_VPMPCC_OGAM_RAMA_OFFSET_G_DEFAULT 0x0000 +#define mmVPMPCC_OGAM1_VPMPCC_OGAM_RAMA_OFFSET_G_DEFAULT 0x0000 +#define mmVPMPCC_OGAM1_VPMPCC_OGAM_RAMA_OFFSET_G_DEFAULT 0x0000 +#define mmVPMPCC_OGAM0_VPMPCC_OGAM_RAMA_OFFSET_R_DEFAULT 0x0000 +#define mmVPMPCC_OGAM0_VPMPCC_OGAM_RAMA_OFFSET_R_DEFAULT 0x0000 +#define mmVPMPCC_OGAM1_VPMPCC_OGAM_RAMA_OFFSET_R_DEFAULT 0x0000 +#define mmVPMPCC_OGAM1_VPMPCC_OGAM_RAMA_OFFSET_R_DEFAULT 0x0000 +#define mmVPMPCC_OGAM0_VPMPCC_OGAM_RAMA_REGION_0_1_DEFAULT 0x0000 +#define mmVPMPCC_OGAM0_VPMPCC_OGAM_RAMA_REGION_0_1_DEFAULT 0x0000 +#define mmVPMPCC_OGAM1_VPMPCC_OGAM_RAMA_REGION_0_1_DEFAULT 0x0000 +#define mmVPMPCC_OGAM1_VPMPCC_OGAM_RAMA_REGION_0_1_DEFAULT 0x0000 +#define mmVPMPCC_OGAM0_VPMPCC_OGAM_RAMA_REGION_2_3_DEFAULT 0x0000 +#define mmVPMPCC_OGAM0_VPMPCC_OGAM_RAMA_REGION_2_3_DEFAULT 0x0000 +#define mmVPMPCC_OGAM1_VPMPCC_OGAM_RAMA_REGION_2_3_DEFAULT 0x0000 +#define mmVPMPCC_OGAM1_VPMPCC_OGAM_RAMA_REGION_2_3_DEFAULT 0x0000 +#define mmVPMPCC_OGAM0_VPMPCC_OGAM_RAMA_REGION_4_5_DEFAULT 0x0000 +#define mmVPMPCC_OGAM0_VPMPCC_OGAM_RAMA_REGION_4_5_DEFAULT 0x0000 +#define mmVPMPCC_OGAM1_VPMPCC_OGAM_RAMA_REGION_4_5_DEFAULT 0x0000 +#define mmVPMPCC_OGAM1_VPMPCC_OGAM_RAMA_REGION_4_5_DEFAULT 0x0000 +#define mmVPMPCC_OGAM0_VPMPCC_OGAM_RAMA_REGION_6_7_DEFAULT 0x0000 +#define mmVPMPCC_OGAM0_VPMPCC_OGAM_RAMA_REGION_6_7_DEFAULT 0x0000 +#define mmVPMPCC_OGAM1_VPMPCC_OGAM_RAMA_REGION_6_7_DEFAULT 0x0000 +#define mmVPMPCC_OGAM1_VPMPCC_OGAM_RAMA_REGION_6_7_DEFAULT 0x0000 +#define mmVPMPCC_OGAM0_VPMPCC_OGAM_RAMA_REGION_8_9_DEFAULT 0x0000 +#define mmVPMPCC_OGAM0_VPMPCC_OGAM_RAMA_REGION_8_9_DEFAULT 0x0000 +#define mmVPMPCC_OGAM1_VPMPCC_OGAM_RAMA_REGION_8_9_DEFAULT 0x0000 +#define mmVPMPCC_OGAM1_VPMPCC_OGAM_RAMA_REGION_8_9_DEFAULT 0x0000 +#define mmVPMPCC_OGAM0_VPMPCC_OGAM_RAMA_REGION_10_11_DEFAULT 0x0000 +#define mmVPMPCC_OGAM0_VPMPCC_OGAM_RAMA_REGION_10_11_DEFAULT 0x0000 +#define mmVPMPCC_OGAM1_VPMPCC_OGAM_RAMA_REGION_10_11_DEFAULT 0x0000 +#define mmVPMPCC_OGAM1_VPMPCC_OGAM_RAMA_REGION_10_11_DEFAULT 0x0000 +#define mmVPMPCC_OGAM0_VPMPCC_OGAM_RAMA_REGION_12_13_DEFAULT 0x0000 +#define mmVPMPCC_OGAM0_VPMPCC_OGAM_RAMA_REGION_12_13_DEFAULT 0x0000 +#define mmVPMPCC_OGAM1_VPMPCC_OGAM_RAMA_REGION_12_13_DEFAULT 0x0000 +#define mmVPMPCC_OGAM1_VPMPCC_OGAM_RAMA_REGION_12_13_DEFAULT 0x0000 +#define mmVPMPCC_OGAM0_VPMPCC_OGAM_RAMA_REGION_14_15_DEFAULT 0x0000 +#define mmVPMPCC_OGAM0_VPMPCC_OGAM_RAMA_REGION_14_15_DEFAULT 0x0000 +#define mmVPMPCC_OGAM1_VPMPCC_OGAM_RAMA_REGION_14_15_DEFAULT 0x0000 +#define mmVPMPCC_OGAM1_VPMPCC_OGAM_RAMA_REGION_14_15_DEFAULT 0x0000 +#define mmVPMPCC_OGAM0_VPMPCC_OGAM_RAMA_REGION_16_17_DEFAULT 0x0000 +#define mmVPMPCC_OGAM0_VPMPCC_OGAM_RAMA_REGION_16_17_DEFAULT 0x0000 +#define mmVPMPCC_OGAM1_VPMPCC_OGAM_RAMA_REGION_16_17_DEFAULT 0x0000 +#define mmVPMPCC_OGAM1_VPMPCC_OGAM_RAMA_REGION_16_17_DEFAULT 0x0000 +#define mmVPMPCC_OGAM0_VPMPCC_OGAM_RAMA_REGION_18_19_DEFAULT 0x0000 +#define mmVPMPCC_OGAM0_VPMPCC_OGAM_RAMA_REGION_18_19_DEFAULT 0x0000 +#define mmVPMPCC_OGAM1_VPMPCC_OGAM_RAMA_REGION_18_19_DEFAULT 0x0000 +#define mmVPMPCC_OGAM1_VPMPCC_OGAM_RAMA_REGION_18_19_DEFAULT 0x0000 +#define mmVPMPCC_OGAM0_VPMPCC_OGAM_RAMA_REGION_20_21_DEFAULT 0x0000 +#define mmVPMPCC_OGAM0_VPMPCC_OGAM_RAMA_REGION_20_21_DEFAULT 0x0000 +#define mmVPMPCC_OGAM1_VPMPCC_OGAM_RAMA_REGION_20_21_DEFAULT 0x0000 +#define mmVPMPCC_OGAM1_VPMPCC_OGAM_RAMA_REGION_20_21_DEFAULT 0x0000 +#define mmVPMPCC_OGAM0_VPMPCC_OGAM_RAMA_REGION_22_23_DEFAULT 0x0000 +#define mmVPMPCC_OGAM0_VPMPCC_OGAM_RAMA_REGION_22_23_DEFAULT 0x0000 +#define mmVPMPCC_OGAM1_VPMPCC_OGAM_RAMA_REGION_22_23_DEFAULT 0x0000 +#define mmVPMPCC_OGAM1_VPMPCC_OGAM_RAMA_REGION_22_23_DEFAULT 0x0000 +#define mmVPMPCC_OGAM0_VPMPCC_OGAM_RAMA_REGION_24_25_DEFAULT 0x0000 +#define mmVPMPCC_OGAM0_VPMPCC_OGAM_RAMA_REGION_24_25_DEFAULT 0x0000 +#define mmVPMPCC_OGAM1_VPMPCC_OGAM_RAMA_REGION_24_25_DEFAULT 0x0000 +#define mmVPMPCC_OGAM1_VPMPCC_OGAM_RAMA_REGION_24_25_DEFAULT 0x0000 +#define mmVPMPCC_OGAM0_VPMPCC_OGAM_RAMA_REGION_26_27_DEFAULT 0x0000 +#define mmVPMPCC_OGAM0_VPMPCC_OGAM_RAMA_REGION_26_27_DEFAULT 0x0000 +#define mmVPMPCC_OGAM1_VPMPCC_OGAM_RAMA_REGION_26_27_DEFAULT 0x0000 +#define mmVPMPCC_OGAM1_VPMPCC_OGAM_RAMA_REGION_26_27_DEFAULT 0x0000 +#define mmVPMPCC_OGAM0_VPMPCC_OGAM_RAMA_REGION_28_29_DEFAULT 0x0000 +#define mmVPMPCC_OGAM0_VPMPCC_OGAM_RAMA_REGION_28_29_DEFAULT 0x0000 +#define mmVPMPCC_OGAM1_VPMPCC_OGAM_RAMA_REGION_28_29_DEFAULT 0x0000 +#define mmVPMPCC_OGAM1_VPMPCC_OGAM_RAMA_REGION_28_29_DEFAULT 0x0000 +#define mmVPMPCC_OGAM0_VPMPCC_OGAM_RAMA_REGION_30_31_DEFAULT 0x0000 +#define mmVPMPCC_OGAM0_VPMPCC_OGAM_RAMA_REGION_30_31_DEFAULT 0x0000 +#define mmVPMPCC_OGAM1_VPMPCC_OGAM_RAMA_REGION_30_31_DEFAULT 0x0000 +#define mmVPMPCC_OGAM1_VPMPCC_OGAM_RAMA_REGION_30_31_DEFAULT 0x0000 +#define mmVPMPCC_OGAM0_VPMPCC_OGAM_RAMA_REGION_32_33_DEFAULT 0x0000 +#define mmVPMPCC_OGAM0_VPMPCC_OGAM_RAMA_REGION_32_33_DEFAULT 0x0000 +#define mmVPMPCC_OGAM1_VPMPCC_OGAM_RAMA_REGION_32_33_DEFAULT 0x0000 +#define mmVPMPCC_OGAM1_VPMPCC_OGAM_RAMA_REGION_32_33_DEFAULT 0x0000 +#define mmVPMPCC_OGAM0_VPMPCC_GAMUT_REMAP_COEF_FORMAT_DEFAULT 0x0000 +#define mmVPMPCC_OGAM0_VPMPCC_GAMUT_REMAP_COEF_FORMAT_DEFAULT 0x0000 +#define mmVPMPCC_OGAM1_VPMPCC_GAMUT_REMAP_COEF_FORMAT_DEFAULT 0x0000 +#define mmVPMPCC_OGAM1_VPMPCC_GAMUT_REMAP_COEF_FORMAT_DEFAULT 0x0000 +#define mmVPMPCC_OGAM0_VPMPCC_GAMUT_REMAP_MODE_DEFAULT 0x0000 +#define mmVPMPCC_OGAM0_VPMPCC_GAMUT_REMAP_MODE_DEFAULT 0x0000 +#define mmVPMPCC_OGAM1_VPMPCC_GAMUT_REMAP_MODE_DEFAULT 0x0000 +#define mmVPMPCC_OGAM1_VPMPCC_GAMUT_REMAP_MODE_DEFAULT 0x0000 +#define mmVPMPCC_OGAM0_VPMPC_GAMUT_REMAP_C11_C12_A_DEFAULT 0x0000 +#define mmVPMPCC_OGAM0_VPMPC_GAMUT_REMAP_C11_C12_A_DEFAULT 0x0000 +#define mmVPMPCC_OGAM1_VPMPC_GAMUT_REMAP_C11_C12_A_DEFAULT 0x0000 +#define mmVPMPCC_OGAM1_VPMPC_GAMUT_REMAP_C11_C12_A_DEFAULT 0x0000 +#define mmVPMPCC_OGAM0_VPMPC_GAMUT_REMAP_C13_C14_A_DEFAULT 0x0000 +#define mmVPMPCC_OGAM0_VPMPC_GAMUT_REMAP_C13_C14_A_DEFAULT 0x0000 +#define mmVPMPCC_OGAM1_VPMPC_GAMUT_REMAP_C13_C14_A_DEFAULT 0x0000 +#define mmVPMPCC_OGAM1_VPMPC_GAMUT_REMAP_C13_C14_A_DEFAULT 0x0000 +#define mmVPMPCC_OGAM0_VPMPC_GAMUT_REMAP_C21_C22_A_DEFAULT 0x0000 +#define mmVPMPCC_OGAM0_VPMPC_GAMUT_REMAP_C21_C22_A_DEFAULT 0x0000 +#define mmVPMPCC_OGAM1_VPMPC_GAMUT_REMAP_C21_C22_A_DEFAULT 0x0000 +#define mmVPMPCC_OGAM1_VPMPC_GAMUT_REMAP_C21_C22_A_DEFAULT 0x0000 +#define mmVPMPCC_OGAM0_VPMPC_GAMUT_REMAP_C23_C24_A_DEFAULT 0x0000 +#define mmVPMPCC_OGAM0_VPMPC_GAMUT_REMAP_C23_C24_A_DEFAULT 0x0000 +#define mmVPMPCC_OGAM1_VPMPC_GAMUT_REMAP_C23_C24_A_DEFAULT 0x0000 +#define mmVPMPCC_OGAM1_VPMPC_GAMUT_REMAP_C23_C24_A_DEFAULT 0x0000 +#define mmVPMPCC_OGAM0_VPMPC_GAMUT_REMAP_C31_C32_A_DEFAULT 0x0000 +#define mmVPMPCC_OGAM0_VPMPC_GAMUT_REMAP_C31_C32_A_DEFAULT 0x0000 +#define mmVPMPCC_OGAM1_VPMPC_GAMUT_REMAP_C31_C32_A_DEFAULT 0x0000 +#define mmVPMPCC_OGAM1_VPMPC_GAMUT_REMAP_C31_C32_A_DEFAULT 0x0000 +#define mmVPMPCC_OGAM0_VPMPC_GAMUT_REMAP_C33_C34_A_DEFAULT 0x0000 +#define mmVPMPCC_OGAM0_VPMPC_GAMUT_REMAP_C33_C34_A_DEFAULT 0x0000 +#define mmVPMPCC_OGAM1_VPMPC_GAMUT_REMAP_C33_C34_A_DEFAULT 0x0000 +#define mmVPMPCC_OGAM1_VPMPC_GAMUT_REMAP_C33_C34_A_DEFAULT 0x0000 + + +// Registers from VPMPCC_MCM block + +#define mmVPMPCC_MCM0_VPMPCC_MCM_1DLUT_CONTROL_DEFAULT 0x0000 +#define mmVPMPCC_MCM0_VPMPCC_MCM_1DLUT_CONTROL_DEFAULT 0x0000 +#define mmVPMPCC_MCM1_VPMPCC_MCM_1DLUT_CONTROL_DEFAULT 0x0000 +#define mmVPMPCC_MCM1_VPMPCC_MCM_1DLUT_CONTROL_DEFAULT 0x0000 +#define mmVPMPCC_MCM0_VPMPCC_MCM_1DLUT_LUT_INDEX_DEFAULT 0x0000 +#define mmVPMPCC_MCM0_VPMPCC_MCM_1DLUT_LUT_INDEX_DEFAULT 0x0000 +#define mmVPMPCC_MCM1_VPMPCC_MCM_1DLUT_LUT_INDEX_DEFAULT 0x0000 +#define mmVPMPCC_MCM1_VPMPCC_MCM_1DLUT_LUT_INDEX_DEFAULT 0x0000 +#define mmVPMPCC_MCM0_VPMPCC_MCM_1DLUT_LUT_DATA_DEFAULT 0x0000 +#define mmVPMPCC_MCM0_VPMPCC_MCM_1DLUT_LUT_DATA_DEFAULT 0x0000 +#define mmVPMPCC_MCM1_VPMPCC_MCM_1DLUT_LUT_DATA_DEFAULT 0x0000 +#define mmVPMPCC_MCM1_VPMPCC_MCM_1DLUT_LUT_DATA_DEFAULT 0x0000 +#define mmVPMPCC_MCM0_VPMPCC_MCM_1DLUT_LUT_CONTROL_DEFAULT 0x0007 +#define mmVPMPCC_MCM0_VPMPCC_MCM_1DLUT_LUT_CONTROL_DEFAULT 0x0007 +#define mmVPMPCC_MCM1_VPMPCC_MCM_1DLUT_LUT_CONTROL_DEFAULT 0x0007 +#define mmVPMPCC_MCM1_VPMPCC_MCM_1DLUT_LUT_CONTROL_DEFAULT 0x0007 +#define mmVPMPCC_MCM0_VPMPCC_MCM_1DLUT_RAMA_START_CNTL_B_DEFAULT 0x0000 +#define mmVPMPCC_MCM0_VPMPCC_MCM_1DLUT_RAMA_START_CNTL_B_DEFAULT 0x0000 +#define mmVPMPCC_MCM1_VPMPCC_MCM_1DLUT_RAMA_START_CNTL_B_DEFAULT 0x0000 +#define mmVPMPCC_MCM1_VPMPCC_MCM_1DLUT_RAMA_START_CNTL_B_DEFAULT 0x0000 +#define mmVPMPCC_MCM0_VPMPCC_MCM_1DLUT_RAMA_START_CNTL_G_DEFAULT 0x0000 +#define mmVPMPCC_MCM0_VPMPCC_MCM_1DLUT_RAMA_START_CNTL_G_DEFAULT 0x0000 +#define mmVPMPCC_MCM1_VPMPCC_MCM_1DLUT_RAMA_START_CNTL_G_DEFAULT 0x0000 +#define mmVPMPCC_MCM1_VPMPCC_MCM_1DLUT_RAMA_START_CNTL_G_DEFAULT 0x0000 +#define mmVPMPCC_MCM0_VPMPCC_MCM_1DLUT_RAMA_START_CNTL_R_DEFAULT 0x0000 +#define mmVPMPCC_MCM0_VPMPCC_MCM_1DLUT_RAMA_START_CNTL_R_DEFAULT 0x0000 +#define mmVPMPCC_MCM1_VPMPCC_MCM_1DLUT_RAMA_START_CNTL_R_DEFAULT 0x0000 +#define mmVPMPCC_MCM1_VPMPCC_MCM_1DLUT_RAMA_START_CNTL_R_DEFAULT 0x0000 +#define mmVPMPCC_MCM0_VPMPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_B_DEFAULT 0x0000 +#define mmVPMPCC_MCM0_VPMPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_B_DEFAULT 0x0000 +#define mmVPMPCC_MCM1_VPMPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_B_DEFAULT 0x0000 +#define mmVPMPCC_MCM1_VPMPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_B_DEFAULT 0x0000 +#define mmVPMPCC_MCM0_VPMPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_G_DEFAULT 0x0000 +#define mmVPMPCC_MCM0_VPMPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_G_DEFAULT 0x0000 +#define mmVPMPCC_MCM1_VPMPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_G_DEFAULT 0x0000 +#define mmVPMPCC_MCM1_VPMPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_G_DEFAULT 0x0000 +#define mmVPMPCC_MCM0_VPMPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_R_DEFAULT 0x0000 +#define mmVPMPCC_MCM0_VPMPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_R_DEFAULT 0x0000 +#define mmVPMPCC_MCM1_VPMPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_R_DEFAULT 0x0000 +#define mmVPMPCC_MCM1_VPMPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_R_DEFAULT 0x0000 +#define mmVPMPCC_MCM0_VPMPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_B_DEFAULT 0x0000 +#define mmVPMPCC_MCM0_VPMPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_B_DEFAULT 0x0000 +#define mmVPMPCC_MCM1_VPMPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_B_DEFAULT 0x0000 +#define mmVPMPCC_MCM1_VPMPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_B_DEFAULT 0x0000 +#define mmVPMPCC_MCM0_VPMPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_G_DEFAULT 0x0000 +#define mmVPMPCC_MCM0_VPMPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_G_DEFAULT 0x0000 +#define mmVPMPCC_MCM1_VPMPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_G_DEFAULT 0x0000 +#define mmVPMPCC_MCM1_VPMPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_G_DEFAULT 0x0000 +#define mmVPMPCC_MCM0_VPMPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_R_DEFAULT 0x0000 +#define mmVPMPCC_MCM0_VPMPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_R_DEFAULT 0x0000 +#define mmVPMPCC_MCM1_VPMPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_R_DEFAULT 0x0000 +#define mmVPMPCC_MCM1_VPMPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_R_DEFAULT 0x0000 +#define mmVPMPCC_MCM0_VPMPCC_MCM_1DLUT_RAMA_END_CNTL1_B_DEFAULT 0x0000 +#define mmVPMPCC_MCM0_VPMPCC_MCM_1DLUT_RAMA_END_CNTL1_B_DEFAULT 0x0000 +#define mmVPMPCC_MCM1_VPMPCC_MCM_1DLUT_RAMA_END_CNTL1_B_DEFAULT 0x0000 +#define mmVPMPCC_MCM1_VPMPCC_MCM_1DLUT_RAMA_END_CNTL1_B_DEFAULT 0x0000 +#define mmVPMPCC_MCM0_VPMPCC_MCM_1DLUT_RAMA_END_CNTL2_B_DEFAULT 0x0000 +#define mmVPMPCC_MCM0_VPMPCC_MCM_1DLUT_RAMA_END_CNTL2_B_DEFAULT 0x0000 +#define mmVPMPCC_MCM1_VPMPCC_MCM_1DLUT_RAMA_END_CNTL2_B_DEFAULT 0x0000 +#define mmVPMPCC_MCM1_VPMPCC_MCM_1DLUT_RAMA_END_CNTL2_B_DEFAULT 0x0000 +#define mmVPMPCC_MCM0_VPMPCC_MCM_1DLUT_RAMA_END_CNTL1_G_DEFAULT 0x0000 +#define mmVPMPCC_MCM0_VPMPCC_MCM_1DLUT_RAMA_END_CNTL1_G_DEFAULT 0x0000 +#define mmVPMPCC_MCM1_VPMPCC_MCM_1DLUT_RAMA_END_CNTL1_G_DEFAULT 0x0000 +#define mmVPMPCC_MCM1_VPMPCC_MCM_1DLUT_RAMA_END_CNTL1_G_DEFAULT 0x0000 +#define mmVPMPCC_MCM0_VPMPCC_MCM_1DLUT_RAMA_END_CNTL2_G_DEFAULT 0x0000 +#define mmVPMPCC_MCM0_VPMPCC_MCM_1DLUT_RAMA_END_CNTL2_G_DEFAULT 0x0000 +#define mmVPMPCC_MCM1_VPMPCC_MCM_1DLUT_RAMA_END_CNTL2_G_DEFAULT 0x0000 +#define mmVPMPCC_MCM1_VPMPCC_MCM_1DLUT_RAMA_END_CNTL2_G_DEFAULT 0x0000 +#define mmVPMPCC_MCM0_VPMPCC_MCM_1DLUT_RAMA_END_CNTL1_R_DEFAULT 0x0000 +#define mmVPMPCC_MCM0_VPMPCC_MCM_1DLUT_RAMA_END_CNTL1_R_DEFAULT 0x0000 +#define mmVPMPCC_MCM1_VPMPCC_MCM_1DLUT_RAMA_END_CNTL1_R_DEFAULT 0x0000 +#define mmVPMPCC_MCM1_VPMPCC_MCM_1DLUT_RAMA_END_CNTL1_R_DEFAULT 0x0000 +#define mmVPMPCC_MCM0_VPMPCC_MCM_1DLUT_RAMA_END_CNTL2_R_DEFAULT 0x0000 +#define mmVPMPCC_MCM0_VPMPCC_MCM_1DLUT_RAMA_END_CNTL2_R_DEFAULT 0x0000 +#define mmVPMPCC_MCM1_VPMPCC_MCM_1DLUT_RAMA_END_CNTL2_R_DEFAULT 0x0000 +#define mmVPMPCC_MCM1_VPMPCC_MCM_1DLUT_RAMA_END_CNTL2_R_DEFAULT 0x0000 +#define mmVPMPCC_MCM0_VPMPCC_MCM_1DLUT_RAMA_OFFSET_B_DEFAULT 0x0000 +#define mmVPMPCC_MCM0_VPMPCC_MCM_1DLUT_RAMA_OFFSET_B_DEFAULT 0x0000 +#define mmVPMPCC_MCM1_VPMPCC_MCM_1DLUT_RAMA_OFFSET_B_DEFAULT 0x0000 +#define mmVPMPCC_MCM1_VPMPCC_MCM_1DLUT_RAMA_OFFSET_B_DEFAULT 0x0000 +#define mmVPMPCC_MCM0_VPMPCC_MCM_1DLUT_RAMA_OFFSET_G_DEFAULT 0x0000 +#define mmVPMPCC_MCM0_VPMPCC_MCM_1DLUT_RAMA_OFFSET_G_DEFAULT 0x0000 +#define mmVPMPCC_MCM1_VPMPCC_MCM_1DLUT_RAMA_OFFSET_G_DEFAULT 0x0000 +#define mmVPMPCC_MCM1_VPMPCC_MCM_1DLUT_RAMA_OFFSET_G_DEFAULT 0x0000 +#define mmVPMPCC_MCM0_VPMPCC_MCM_1DLUT_RAMA_OFFSET_R_DEFAULT 0x0000 +#define mmVPMPCC_MCM0_VPMPCC_MCM_1DLUT_RAMA_OFFSET_R_DEFAULT 0x0000 +#define mmVPMPCC_MCM1_VPMPCC_MCM_1DLUT_RAMA_OFFSET_R_DEFAULT 0x0000 +#define mmVPMPCC_MCM1_VPMPCC_MCM_1DLUT_RAMA_OFFSET_R_DEFAULT 0x0000 +#define mmVPMPCC_MCM0_VPMPCC_MCM_1DLUT_RAMA_REGION_0_1_DEFAULT 0x0000 +#define mmVPMPCC_MCM0_VPMPCC_MCM_1DLUT_RAMA_REGION_0_1_DEFAULT 0x0000 +#define mmVPMPCC_MCM1_VPMPCC_MCM_1DLUT_RAMA_REGION_0_1_DEFAULT 0x0000 +#define mmVPMPCC_MCM1_VPMPCC_MCM_1DLUT_RAMA_REGION_0_1_DEFAULT 0x0000 +#define mmVPMPCC_MCM0_VPMPCC_MCM_1DLUT_RAMA_REGION_2_3_DEFAULT 0x0000 +#define mmVPMPCC_MCM0_VPMPCC_MCM_1DLUT_RAMA_REGION_2_3_DEFAULT 0x0000 +#define mmVPMPCC_MCM1_VPMPCC_MCM_1DLUT_RAMA_REGION_2_3_DEFAULT 0x0000 +#define mmVPMPCC_MCM1_VPMPCC_MCM_1DLUT_RAMA_REGION_2_3_DEFAULT 0x0000 +#define mmVPMPCC_MCM0_VPMPCC_MCM_1DLUT_RAMA_REGION_4_5_DEFAULT 0x0000 +#define mmVPMPCC_MCM0_VPMPCC_MCM_1DLUT_RAMA_REGION_4_5_DEFAULT 0x0000 +#define mmVPMPCC_MCM1_VPMPCC_MCM_1DLUT_RAMA_REGION_4_5_DEFAULT 0x0000 +#define mmVPMPCC_MCM1_VPMPCC_MCM_1DLUT_RAMA_REGION_4_5_DEFAULT 0x0000 +#define mmVPMPCC_MCM0_VPMPCC_MCM_1DLUT_RAMA_REGION_6_7_DEFAULT 0x0000 +#define mmVPMPCC_MCM0_VPMPCC_MCM_1DLUT_RAMA_REGION_6_7_DEFAULT 0x0000 +#define mmVPMPCC_MCM1_VPMPCC_MCM_1DLUT_RAMA_REGION_6_7_DEFAULT 0x0000 +#define mmVPMPCC_MCM1_VPMPCC_MCM_1DLUT_RAMA_REGION_6_7_DEFAULT 0x0000 +#define mmVPMPCC_MCM0_VPMPCC_MCM_1DLUT_RAMA_REGION_8_9_DEFAULT 0x0000 +#define mmVPMPCC_MCM0_VPMPCC_MCM_1DLUT_RAMA_REGION_8_9_DEFAULT 0x0000 +#define mmVPMPCC_MCM1_VPMPCC_MCM_1DLUT_RAMA_REGION_8_9_DEFAULT 0x0000 +#define mmVPMPCC_MCM1_VPMPCC_MCM_1DLUT_RAMA_REGION_8_9_DEFAULT 0x0000 +#define mmVPMPCC_MCM0_VPMPCC_MCM_1DLUT_RAMA_REGION_10_11_DEFAULT 0x0000 +#define mmVPMPCC_MCM0_VPMPCC_MCM_1DLUT_RAMA_REGION_10_11_DEFAULT 0x0000 +#define mmVPMPCC_MCM1_VPMPCC_MCM_1DLUT_RAMA_REGION_10_11_DEFAULT 0x0000 +#define mmVPMPCC_MCM1_VPMPCC_MCM_1DLUT_RAMA_REGION_10_11_DEFAULT 0x0000 +#define mmVPMPCC_MCM0_VPMPCC_MCM_1DLUT_RAMA_REGION_12_13_DEFAULT 0x0000 +#define mmVPMPCC_MCM0_VPMPCC_MCM_1DLUT_RAMA_REGION_12_13_DEFAULT 0x0000 +#define mmVPMPCC_MCM1_VPMPCC_MCM_1DLUT_RAMA_REGION_12_13_DEFAULT 0x0000 +#define mmVPMPCC_MCM1_VPMPCC_MCM_1DLUT_RAMA_REGION_12_13_DEFAULT 0x0000 +#define mmVPMPCC_MCM0_VPMPCC_MCM_1DLUT_RAMA_REGION_14_15_DEFAULT 0x0000 +#define mmVPMPCC_MCM0_VPMPCC_MCM_1DLUT_RAMA_REGION_14_15_DEFAULT 0x0000 +#define mmVPMPCC_MCM1_VPMPCC_MCM_1DLUT_RAMA_REGION_14_15_DEFAULT 0x0000 +#define mmVPMPCC_MCM1_VPMPCC_MCM_1DLUT_RAMA_REGION_14_15_DEFAULT 0x0000 +#define mmVPMPCC_MCM0_VPMPCC_MCM_1DLUT_RAMA_REGION_16_17_DEFAULT 0x0000 +#define mmVPMPCC_MCM0_VPMPCC_MCM_1DLUT_RAMA_REGION_16_17_DEFAULT 0x0000 +#define mmVPMPCC_MCM1_VPMPCC_MCM_1DLUT_RAMA_REGION_16_17_DEFAULT 0x0000 +#define mmVPMPCC_MCM1_VPMPCC_MCM_1DLUT_RAMA_REGION_16_17_DEFAULT 0x0000 +#define mmVPMPCC_MCM0_VPMPCC_MCM_1DLUT_RAMA_REGION_18_19_DEFAULT 0x0000 +#define mmVPMPCC_MCM0_VPMPCC_MCM_1DLUT_RAMA_REGION_18_19_DEFAULT 0x0000 +#define mmVPMPCC_MCM1_VPMPCC_MCM_1DLUT_RAMA_REGION_18_19_DEFAULT 0x0000 +#define mmVPMPCC_MCM1_VPMPCC_MCM_1DLUT_RAMA_REGION_18_19_DEFAULT 0x0000 +#define mmVPMPCC_MCM0_VPMPCC_MCM_1DLUT_RAMA_REGION_20_21_DEFAULT 0x0000 +#define mmVPMPCC_MCM0_VPMPCC_MCM_1DLUT_RAMA_REGION_20_21_DEFAULT 0x0000 +#define mmVPMPCC_MCM1_VPMPCC_MCM_1DLUT_RAMA_REGION_20_21_DEFAULT 0x0000 +#define mmVPMPCC_MCM1_VPMPCC_MCM_1DLUT_RAMA_REGION_20_21_DEFAULT 0x0000 +#define mmVPMPCC_MCM0_VPMPCC_MCM_1DLUT_RAMA_REGION_22_23_DEFAULT 0x0000 +#define mmVPMPCC_MCM0_VPMPCC_MCM_1DLUT_RAMA_REGION_22_23_DEFAULT 0x0000 +#define mmVPMPCC_MCM1_VPMPCC_MCM_1DLUT_RAMA_REGION_22_23_DEFAULT 0x0000 +#define mmVPMPCC_MCM1_VPMPCC_MCM_1DLUT_RAMA_REGION_22_23_DEFAULT 0x0000 +#define mmVPMPCC_MCM0_VPMPCC_MCM_1DLUT_RAMA_REGION_24_25_DEFAULT 0x0000 +#define mmVPMPCC_MCM0_VPMPCC_MCM_1DLUT_RAMA_REGION_24_25_DEFAULT 0x0000 +#define mmVPMPCC_MCM1_VPMPCC_MCM_1DLUT_RAMA_REGION_24_25_DEFAULT 0x0000 +#define mmVPMPCC_MCM1_VPMPCC_MCM_1DLUT_RAMA_REGION_24_25_DEFAULT 0x0000 +#define mmVPMPCC_MCM0_VPMPCC_MCM_1DLUT_RAMA_REGION_26_27_DEFAULT 0x0000 +#define mmVPMPCC_MCM0_VPMPCC_MCM_1DLUT_RAMA_REGION_26_27_DEFAULT 0x0000 +#define mmVPMPCC_MCM1_VPMPCC_MCM_1DLUT_RAMA_REGION_26_27_DEFAULT 0x0000 +#define mmVPMPCC_MCM1_VPMPCC_MCM_1DLUT_RAMA_REGION_26_27_DEFAULT 0x0000 +#define mmVPMPCC_MCM0_VPMPCC_MCM_1DLUT_RAMA_REGION_28_29_DEFAULT 0x0000 +#define mmVPMPCC_MCM0_VPMPCC_MCM_1DLUT_RAMA_REGION_28_29_DEFAULT 0x0000 +#define mmVPMPCC_MCM1_VPMPCC_MCM_1DLUT_RAMA_REGION_28_29_DEFAULT 0x0000 +#define mmVPMPCC_MCM1_VPMPCC_MCM_1DLUT_RAMA_REGION_28_29_DEFAULT 0x0000 +#define mmVPMPCC_MCM0_VPMPCC_MCM_1DLUT_RAMA_REGION_30_31_DEFAULT 0x0000 +#define mmVPMPCC_MCM0_VPMPCC_MCM_1DLUT_RAMA_REGION_30_31_DEFAULT 0x0000 +#define mmVPMPCC_MCM1_VPMPCC_MCM_1DLUT_RAMA_REGION_30_31_DEFAULT 0x0000 +#define mmVPMPCC_MCM1_VPMPCC_MCM_1DLUT_RAMA_REGION_30_31_DEFAULT 0x0000 +#define mmVPMPCC_MCM0_VPMPCC_MCM_1DLUT_RAMA_REGION_32_33_DEFAULT 0x0000 +#define mmVPMPCC_MCM0_VPMPCC_MCM_1DLUT_RAMA_REGION_32_33_DEFAULT 0x0000 +#define mmVPMPCC_MCM1_VPMPCC_MCM_1DLUT_RAMA_REGION_32_33_DEFAULT 0x0000 +#define mmVPMPCC_MCM1_VPMPCC_MCM_1DLUT_RAMA_REGION_32_33_DEFAULT 0x0000 +#define mmVPMPCC_MCM0_VPMPCC_MCM_FIRST_GAMUT_REMAP_COEF_FORMAT_DEFAULT 0x0000 +#define mmVPMPCC_MCM0_VPMPCC_MCM_FIRST_GAMUT_REMAP_COEF_FORMAT_DEFAULT 0x0000 +#define mmVPMPCC_MCM1_VPMPCC_MCM_FIRST_GAMUT_REMAP_COEF_FORMAT_DEFAULT 0x0000 +#define mmVPMPCC_MCM1_VPMPCC_MCM_FIRST_GAMUT_REMAP_COEF_FORMAT_DEFAULT 0x0000 +#define mmVPMPCC_MCM0_VPMPCC_MCM_FIRST_GAMUT_REMAP_MODE_DEFAULT 0x0000 +#define mmVPMPCC_MCM0_VPMPCC_MCM_FIRST_GAMUT_REMAP_MODE_DEFAULT 0x0000 +#define mmVPMPCC_MCM1_VPMPCC_MCM_FIRST_GAMUT_REMAP_MODE_DEFAULT 0x0000 +#define mmVPMPCC_MCM1_VPMPCC_MCM_FIRST_GAMUT_REMAP_MODE_DEFAULT 0x0000 +#define mmVPMPCC_MCM0_VPMPC_MCM_FIRST_GAMUT_REMAP_C11_C12_SETA_DEFAULT 0x0000 +#define mmVPMPCC_MCM0_VPMPC_MCM_FIRST_GAMUT_REMAP_C11_C12_SETA_DEFAULT 0x0000 +#define mmVPMPCC_MCM1_VPMPC_MCM_FIRST_GAMUT_REMAP_C11_C12_SETA_DEFAULT 0x0000 +#define mmVPMPCC_MCM1_VPMPC_MCM_FIRST_GAMUT_REMAP_C11_C12_SETA_DEFAULT 0x0000 +#define mmVPMPCC_MCM0_VPMPC_MCM_FIRST_GAMUT_REMAP_C13_C14_SETA_DEFAULT 0x0000 +#define mmVPMPCC_MCM0_VPMPC_MCM_FIRST_GAMUT_REMAP_C13_C14_SETA_DEFAULT 0x0000 +#define mmVPMPCC_MCM1_VPMPC_MCM_FIRST_GAMUT_REMAP_C13_C14_SETA_DEFAULT 0x0000 +#define mmVPMPCC_MCM1_VPMPC_MCM_FIRST_GAMUT_REMAP_C13_C14_SETA_DEFAULT 0x0000 +#define mmVPMPCC_MCM0_VPMPC_MCM_FIRST_GAMUT_REMAP_C21_C22_SETA_DEFAULT 0x0000 +#define mmVPMPCC_MCM0_VPMPC_MCM_FIRST_GAMUT_REMAP_C21_C22_SETA_DEFAULT 0x0000 +#define mmVPMPCC_MCM1_VPMPC_MCM_FIRST_GAMUT_REMAP_C21_C22_SETA_DEFAULT 0x0000 +#define mmVPMPCC_MCM1_VPMPC_MCM_FIRST_GAMUT_REMAP_C21_C22_SETA_DEFAULT 0x0000 +#define mmVPMPCC_MCM0_VPMPC_MCM_FIRST_GAMUT_REMAP_C23_C24_SETA_DEFAULT 0x0000 +#define mmVPMPCC_MCM0_VPMPC_MCM_FIRST_GAMUT_REMAP_C23_C24_SETA_DEFAULT 0x0000 +#define mmVPMPCC_MCM1_VPMPC_MCM_FIRST_GAMUT_REMAP_C23_C24_SETA_DEFAULT 0x0000 +#define mmVPMPCC_MCM1_VPMPC_MCM_FIRST_GAMUT_REMAP_C23_C24_SETA_DEFAULT 0x0000 +#define mmVPMPCC_MCM0_VPMPC_MCM_FIRST_GAMUT_REMAP_C31_C32_SETA_DEFAULT 0x0000 +#define mmVPMPCC_MCM0_VPMPC_MCM_FIRST_GAMUT_REMAP_C31_C32_SETA_DEFAULT 0x0000 +#define mmVPMPCC_MCM1_VPMPC_MCM_FIRST_GAMUT_REMAP_C31_C32_SETA_DEFAULT 0x0000 +#define mmVPMPCC_MCM1_VPMPC_MCM_FIRST_GAMUT_REMAP_C31_C32_SETA_DEFAULT 0x0000 +#define mmVPMPCC_MCM0_VPMPC_MCM_FIRST_GAMUT_REMAP_C33_C34_SETA_DEFAULT 0x0000 +#define mmVPMPCC_MCM0_VPMPC_MCM_FIRST_GAMUT_REMAP_C33_C34_SETA_DEFAULT 0x0000 +#define mmVPMPCC_MCM1_VPMPC_MCM_FIRST_GAMUT_REMAP_C33_C34_SETA_DEFAULT 0x0000 +#define mmVPMPCC_MCM1_VPMPC_MCM_FIRST_GAMUT_REMAP_C33_C34_SETA_DEFAULT 0x0000 +#define mmVPMPCC_MCM0_VPMPCC_MCM_SECOND_GAMUT_REMAP_COEF_FORMAT_DEFAULT 0x0000 +#define mmVPMPCC_MCM0_VPMPCC_MCM_SECOND_GAMUT_REMAP_COEF_FORMAT_DEFAULT 0x0000 +#define mmVPMPCC_MCM1_VPMPCC_MCM_SECOND_GAMUT_REMAP_COEF_FORMAT_DEFAULT 0x0000 +#define mmVPMPCC_MCM1_VPMPCC_MCM_SECOND_GAMUT_REMAP_COEF_FORMAT_DEFAULT 0x0000 +#define mmVPMPCC_MCM0_VPMPCC_MCM_SECOND_GAMUT_REMAP_MODE_DEFAULT 0x0000 +#define mmVPMPCC_MCM0_VPMPCC_MCM_SECOND_GAMUT_REMAP_MODE_DEFAULT 0x0000 +#define mmVPMPCC_MCM1_VPMPCC_MCM_SECOND_GAMUT_REMAP_MODE_DEFAULT 0x0000 +#define mmVPMPCC_MCM1_VPMPCC_MCM_SECOND_GAMUT_REMAP_MODE_DEFAULT 0x0000 +#define mmVPMPCC_MCM0_VPMPC_MCM_SECOND_GAMUT_REMAP_C11_C12_SETA_DEFAULT 0x0000 +#define mmVPMPCC_MCM0_VPMPC_MCM_SECOND_GAMUT_REMAP_C11_C12_SETA_DEFAULT 0x0000 +#define mmVPMPCC_MCM1_VPMPC_MCM_SECOND_GAMUT_REMAP_C11_C12_SETA_DEFAULT 0x0000 +#define mmVPMPCC_MCM1_VPMPC_MCM_SECOND_GAMUT_REMAP_C11_C12_SETA_DEFAULT 0x0000 +#define mmVPMPCC_MCM0_VPMPC_MCM_SECOND_GAMUT_REMAP_C13_C14_SETA_DEFAULT 0x0000 +#define mmVPMPCC_MCM0_VPMPC_MCM_SECOND_GAMUT_REMAP_C13_C14_SETA_DEFAULT 0x0000 +#define mmVPMPCC_MCM1_VPMPC_MCM_SECOND_GAMUT_REMAP_C13_C14_SETA_DEFAULT 0x0000 +#define mmVPMPCC_MCM1_VPMPC_MCM_SECOND_GAMUT_REMAP_C13_C14_SETA_DEFAULT 0x0000 +#define mmVPMPCC_MCM0_VPMPC_MCM_SECOND_GAMUT_REMAP_C21_C22_SETA_DEFAULT 0x0000 +#define mmVPMPCC_MCM0_VPMPC_MCM_SECOND_GAMUT_REMAP_C21_C22_SETA_DEFAULT 0x0000 +#define mmVPMPCC_MCM1_VPMPC_MCM_SECOND_GAMUT_REMAP_C21_C22_SETA_DEFAULT 0x0000 +#define mmVPMPCC_MCM1_VPMPC_MCM_SECOND_GAMUT_REMAP_C21_C22_SETA_DEFAULT 0x0000 +#define mmVPMPCC_MCM0_VPMPC_MCM_SECOND_GAMUT_REMAP_C23_C24_SETA_DEFAULT 0x0000 +#define mmVPMPCC_MCM0_VPMPC_MCM_SECOND_GAMUT_REMAP_C23_C24_SETA_DEFAULT 0x0000 +#define mmVPMPCC_MCM1_VPMPC_MCM_SECOND_GAMUT_REMAP_C23_C24_SETA_DEFAULT 0x0000 +#define mmVPMPCC_MCM1_VPMPC_MCM_SECOND_GAMUT_REMAP_C23_C24_SETA_DEFAULT 0x0000 +#define mmVPMPCC_MCM0_VPMPC_MCM_SECOND_GAMUT_REMAP_C31_C32_SETA_DEFAULT 0x0000 +#define mmVPMPCC_MCM0_VPMPC_MCM_SECOND_GAMUT_REMAP_C31_C32_SETA_DEFAULT 0x0000 +#define mmVPMPCC_MCM1_VPMPC_MCM_SECOND_GAMUT_REMAP_C31_C32_SETA_DEFAULT 0x0000 +#define mmVPMPCC_MCM1_VPMPC_MCM_SECOND_GAMUT_REMAP_C31_C32_SETA_DEFAULT 0x0000 +#define mmVPMPCC_MCM0_VPMPC_MCM_SECOND_GAMUT_REMAP_C33_C34_SETA_DEFAULT 0x0000 +#define mmVPMPCC_MCM0_VPMPC_MCM_SECOND_GAMUT_REMAP_C33_C34_SETA_DEFAULT 0x0000 +#define mmVPMPCC_MCM1_VPMPC_MCM_SECOND_GAMUT_REMAP_C33_C34_SETA_DEFAULT 0x0000 +#define mmVPMPCC_MCM1_VPMPC_MCM_SECOND_GAMUT_REMAP_C33_C34_SETA_DEFAULT 0x0000 +#define mmVPMPCC_MCM0_VPMPCC_MCM_MEM_PWR_CTRL_DEFAULT 0x100000 +#define mmVPMPCC_MCM0_VPMPCC_MCM_MEM_PWR_CTRL_DEFAULT 0x100000 +#define mmVPMPCC_MCM1_VPMPCC_MCM_MEM_PWR_CTRL_DEFAULT 0x100000 +#define mmVPMPCC_MCM1_VPMPCC_MCM_MEM_PWR_CTRL_DEFAULT 0x100000 + + +// Registers from VPMPC_RMCM block + +#define mmVPMPC_RMCM_SHAPER_CONTROL_DEFAULT 0x0000 +#define mmVPMPC_RMCM_SHAPER_OFFSET_R_DEFAULT 0x0000 +#define mmVPMPC_RMCM_SHAPER_OFFSET_G_DEFAULT 0x0000 +#define mmVPMPC_RMCM_SHAPER_OFFSET_B_DEFAULT 0x0000 +#define mmVPMPC_RMCM_SHAPER_SCALE_R_DEFAULT 0x7000 +#define mmVPMPC_RMCM_SHAPER_SCALE_G_B_DEFAULT 0x70007000 +#define mmVPMPC_RMCM_SHAPER_LUT_INDEX_DEFAULT 0x0000 +#define mmVPMPC_RMCM_SHAPER_LUT_DATA_DEFAULT 0x0000 +#define mmVPMPC_RMCM_SHAPER_LUT_WRITE_EN_MASK_DEFAULT 0x0007 +#define mmVPMPC_RMCM_SHAPER_RAMA_START_CNTL_B_DEFAULT 0x0000 +#define mmVPMPC_RMCM_SHAPER_RAMA_START_CNTL_G_DEFAULT 0x0000 +#define mmVPMPC_RMCM_SHAPER_RAMA_START_CNTL_R_DEFAULT 0x0000 +#define mmVPMPC_RMCM_SHAPER_RAMA_END_CNTL_B_DEFAULT 0x0000 +#define mmVPMPC_RMCM_SHAPER_RAMA_END_CNTL_G_DEFAULT 0x0000 +#define mmVPMPC_RMCM_SHAPER_RAMA_END_CNTL_R_DEFAULT 0x0000 +#define mmVPMPC_RMCM_SHAPER_RAMA_REGION_0_1_DEFAULT 0x0000 +#define mmVPMPC_RMCM_SHAPER_RAMA_REGION_2_3_DEFAULT 0x0000 +#define mmVPMPC_RMCM_SHAPER_RAMA_REGION_4_5_DEFAULT 0x0000 +#define mmVPMPC_RMCM_SHAPER_RAMA_REGION_6_7_DEFAULT 0x0000 +#define mmVPMPC_RMCM_SHAPER_RAMA_REGION_8_9_DEFAULT 0x0000 +#define mmVPMPC_RMCM_SHAPER_RAMA_REGION_10_11_DEFAULT 0x0000 +#define mmVPMPC_RMCM_SHAPER_RAMA_REGION_12_13_DEFAULT 0x0000 +#define mmVPMPC_RMCM_SHAPER_RAMA_REGION_14_15_DEFAULT 0x0000 +#define mmVPMPC_RMCM_SHAPER_RAMA_REGION_16_17_DEFAULT 0x0000 +#define mmVPMPC_RMCM_SHAPER_RAMA_REGION_18_19_DEFAULT 0x0000 +#define mmVPMPC_RMCM_SHAPER_RAMA_REGION_20_21_DEFAULT 0x0000 +#define mmVPMPC_RMCM_SHAPER_RAMA_REGION_22_23_DEFAULT 0x0000 +#define mmVPMPC_RMCM_SHAPER_RAMA_REGION_24_25_DEFAULT 0x0000 +#define mmVPMPC_RMCM_SHAPER_RAMA_REGION_26_27_DEFAULT 0x0000 +#define mmVPMPC_RMCM_SHAPER_RAMA_REGION_28_29_DEFAULT 0x0000 +#define mmVPMPC_RMCM_SHAPER_RAMA_REGION_30_31_DEFAULT 0x0000 +#define mmVPMPC_RMCM_SHAPER_RAMA_REGION_32_33_DEFAULT 0x0000 +#define mmVPMPC_RMCM_3DLUT_MODE_DEFAULT 0x0000 +#define mmVPMPC_RMCM_3DLUT_INDEX_DEFAULT 0x0000 +#define mmVPMPC_RMCM_3DLUT_DATA_DEFAULT 0x0000 +#define mmVPMPC_RMCM_3DLUT_DATA_30BIT_DEFAULT 0x0000 +#define mmVPMPC_RMCM_3DLUT_READ_WRITE_CONTROL_DEFAULT 0x000F +#define mmVPMPC_RMCM_3DLUT_OUT_NORM_FACTOR_DEFAULT 0x8008 +#define mmVPMPC_RMCM_3DLUT_OUT_OFFSET_R_DEFAULT 0x3C000000 +#define mmVPMPC_RMCM_3DLUT_OUT_OFFSET_G_DEFAULT 0x3C000000 +#define mmVPMPC_RMCM_3DLUT_OUT_OFFSET_B_DEFAULT 0x3C000000 +#define mmVPMPC_RMCM_GAMUT_REMAP_COEF_FORMAT_DEFAULT 0x0000 +#define mmVPMPC_RMCM_GAMUT_REMAP_MODE_DEFAULT 0x0000 +#define mmVPMPC_RMCM_GAMUT_REMAP_C11_C12_SETA_DEFAULT 0x0000 +#define mmVPMPC_RMCM_GAMUT_REMAP_C13_C14_SETA_DEFAULT 0x0000 +#define mmVPMPC_RMCM_GAMUT_REMAP_C21_C22_SETA_DEFAULT 0x0000 +#define mmVPMPC_RMCM_GAMUT_REMAP_C23_C24_SETA_DEFAULT 0x0000 +#define mmVPMPC_RMCM_GAMUT_REMAP_C31_C32_SETA_DEFAULT 0x0000 +#define mmVPMPC_RMCM_GAMUT_REMAP_C33_C34_SETA_DEFAULT 0x0000 +#define mmVPMPC_RMCM_MEM_PWR_CTRL_DEFAULT 0x1010 +#define mmVPMPC_RMCM_3DLUT_FAST_LOAD_SELECT_DEFAULT 0x000F +#define mmVPMPC_RMCM_CNTL_DEFAULT 0x000F + + +// Registers from VPFMT block + +#define mmVPFMT0_VPFMT_CLAMP_COMPONENT_R_DEFAULT 0x0000 +#define mmVPFMT0_VPFMT_CLAMP_COMPONENT_R_DEFAULT 0x0000 +#define mmVPFMT1_VPFMT_CLAMP_COMPONENT_R_DEFAULT 0x0000 +#define mmVPFMT1_VPFMT_CLAMP_COMPONENT_R_DEFAULT 0x0000 +#define mmVPFMT0_VPFMT_CLAMP_COMPONENT_G_DEFAULT 0x0000 +#define mmVPFMT0_VPFMT_CLAMP_COMPONENT_G_DEFAULT 0x0000 +#define mmVPFMT1_VPFMT_CLAMP_COMPONENT_G_DEFAULT 0x0000 +#define mmVPFMT1_VPFMT_CLAMP_COMPONENT_G_DEFAULT 0x0000 +#define mmVPFMT0_VPFMT_CLAMP_COMPONENT_B_DEFAULT 0x0000 +#define mmVPFMT0_VPFMT_CLAMP_COMPONENT_B_DEFAULT 0x0000 +#define mmVPFMT1_VPFMT_CLAMP_COMPONENT_B_DEFAULT 0x0000 +#define mmVPFMT1_VPFMT_CLAMP_COMPONENT_B_DEFAULT 0x0000 +#define mmVPFMT0_VPFMT_DYNAMIC_EXP_CNTL_DEFAULT 0x0000 +#define mmVPFMT0_VPFMT_DYNAMIC_EXP_CNTL_DEFAULT 0x0000 +#define mmVPFMT1_VPFMT_DYNAMIC_EXP_CNTL_DEFAULT 0x0000 +#define mmVPFMT1_VPFMT_DYNAMIC_EXP_CNTL_DEFAULT 0x0000 +#define mmVPFMT0_VPFMT_CONTROL_DEFAULT 0x0000 +#define mmVPFMT0_VPFMT_CONTROL_DEFAULT 0x0000 +#define mmVPFMT1_VPFMT_CONTROL_DEFAULT 0x0000 +#define mmVPFMT1_VPFMT_CONTROL_DEFAULT 0x0000 +#define mmVPFMT0_VPFMT_BIT_DEPTH_CONTROL_DEFAULT 0x0000 +#define mmVPFMT0_VPFMT_BIT_DEPTH_CONTROL_DEFAULT 0x0000 +#define mmVPFMT1_VPFMT_BIT_DEPTH_CONTROL_DEFAULT 0x0000 +#define mmVPFMT1_VPFMT_BIT_DEPTH_CONTROL_DEFAULT 0x0000 +#define mmVPFMT0_VPFMT_DITHER_RAND_R_SEED_DEFAULT 0x0000 +#define mmVPFMT0_VPFMT_DITHER_RAND_R_SEED_DEFAULT 0x0000 +#define mmVPFMT1_VPFMT_DITHER_RAND_R_SEED_DEFAULT 0x0000 +#define mmVPFMT1_VPFMT_DITHER_RAND_R_SEED_DEFAULT 0x0000 +#define mmVPFMT0_VPFMT_DITHER_RAND_G_SEED_DEFAULT 0x0099 +#define mmVPFMT0_VPFMT_DITHER_RAND_G_SEED_DEFAULT 0x0099 +#define mmVPFMT1_VPFMT_DITHER_RAND_G_SEED_DEFAULT 0x0099 +#define mmVPFMT1_VPFMT_DITHER_RAND_G_SEED_DEFAULT 0x0099 +#define mmVPFMT0_VPFMT_DITHER_RAND_B_SEED_DEFAULT 0x00DD +#define mmVPFMT0_VPFMT_DITHER_RAND_B_SEED_DEFAULT 0x00DD +#define mmVPFMT1_VPFMT_DITHER_RAND_B_SEED_DEFAULT 0x00DD +#define mmVPFMT1_VPFMT_DITHER_RAND_B_SEED_DEFAULT 0x00DD +#define mmVPFMT0_VPFMT_CLAMP_CNTL_DEFAULT 0x0000 +#define mmVPFMT0_VPFMT_CLAMP_CNTL_DEFAULT 0x0000 +#define mmVPFMT1_VPFMT_CLAMP_CNTL_DEFAULT 0x0000 +#define mmVPFMT1_VPFMT_CLAMP_CNTL_DEFAULT 0x0000 +#define mmVPFMT0_VPFMT_SUBSAMPLER_MEMORY_CONTROL_DEFAULT 0x3000 +#define mmVPFMT0_VPFMT_SUBSAMPLER_MEMORY_CONTROL_DEFAULT 0x3000 +#define mmVPFMT1_VPFMT_SUBSAMPLER_MEMORY_CONTROL_DEFAULT 0x3000 +#define mmVPFMT1_VPFMT_SUBSAMPLER_MEMORY_CONTROL_DEFAULT 0x3000 + + +// Registers from VPOPP_PIPE block + +#define mmVPOPP_PIPE0_VPOPP_PIPE_CONTROL_DEFAULT 0x0000 +#define mmVPOPP_PIPE0_VPOPP_PIPE_CONTROL_DEFAULT 0x0000 +#define mmVPOPP_PIPE1_VPOPP_PIPE_CONTROL_DEFAULT 0x0000 +#define mmVPOPP_PIPE1_VPOPP_PIPE_CONTROL_DEFAULT 0x0000 +#define mmVPOPP_PIPE0_VPOPP_PIPE_OUTBG_EXT1_DEFAULT 0x0000 +#define mmVPOPP_PIPE0_VPOPP_PIPE_OUTBG_EXT1_DEFAULT 0x0000 +#define mmVPOPP_PIPE1_VPOPP_PIPE_OUTBG_EXT1_DEFAULT 0x0000 +#define mmVPOPP_PIPE1_VPOPP_PIPE_OUTBG_EXT1_DEFAULT 0x0000 +#define mmVPOPP_PIPE0_VPOPP_PIPE_OUTBG_EXT2_DEFAULT 0x0000 +#define mmVPOPP_PIPE0_VPOPP_PIPE_OUTBG_EXT2_DEFAULT 0x0000 +#define mmVPOPP_PIPE1_VPOPP_PIPE_OUTBG_EXT2_DEFAULT 0x0000 +#define mmVPOPP_PIPE1_VPOPP_PIPE_OUTBG_EXT2_DEFAULT 0x0000 +#define mmVPOPP_PIPE0_VPOPP_PIPE_OUTBG_COL1_DEFAULT 0x0000 +#define mmVPOPP_PIPE0_VPOPP_PIPE_OUTBG_COL1_DEFAULT 0x0000 +#define mmVPOPP_PIPE1_VPOPP_PIPE_OUTBG_COL1_DEFAULT 0x0000 +#define mmVPOPP_PIPE1_VPOPP_PIPE_OUTBG_COL1_DEFAULT 0x0000 +#define mmVPOPP_PIPE0_VPOPP_PIPE_OUTBG_COL2_DEFAULT 0x0000 +#define mmVPOPP_PIPE0_VPOPP_PIPE_OUTBG_COL2_DEFAULT 0x0000 +#define mmVPOPP_PIPE1_VPOPP_PIPE_OUTBG_COL2_DEFAULT 0x0000 +#define mmVPOPP_PIPE1_VPOPP_PIPE_OUTBG_COL2_DEFAULT 0x0000 + + +// Registers from VPOPP_TOP block + +#define mmVPOPP_TOP_CLK_CONTROL_DEFAULT 0x0000 +#define mmVPOPP_CRC_CONTROL_DEFAULT 0xFFFF00 +#define mmVPOPP_CRC_RESULT_RG_DEFAULT 0x0000 +#define mmVPOPP_CRC_RESULT_BC_DEFAULT 0x0000 +#define mmVPOPP_FROD_CONTROL_DEFAULT 0x0000 +#define mmVPOPP_FROD_MEM_PWR_CONTROL_DEFAULT 0x3000 + + +#endif diff --git a/src/amd/vpelib/src/chip/vpe22/inc/asic/chip_mask.h b/src/amd/vpelib/src/chip/vpe22/inc/asic/chip_mask.h new file mode 100644 index 00000000000..8d626def41e --- /dev/null +++ b/src/amd/vpelib/src/chip/vpe22/inc/asic/chip_mask.h @@ -0,0 +1,1892 @@ +// Copyright (c) 1994 - 2025 Advanced Micro Devices, Inc. All rights reserved. + +#ifndef _vpe22_MASK_HEADER +#define _vpe22_MASK_HEADER +/* + * chip_mask.h + * + * Register Spec Release: + * + * + * (c) 2021 Advanced Micro Devices, Inc. (unpublished) + * + * All rights reserved. This notice is intended as a precaution against + * inadvertent publication and does not imply publication or any waiver + * of confidentiality. The year included in the foregoing notice is the + * year of creation of the work. + * + */ + +// VPEP_MGCG_CNTL +#define VPEP_MGCG_CNTL__VPDPP0_CLK_GATE_DIS_MASK 0x00000007UL +#define VPEP_MGCG_CNTL__VPMPC_CLK_GATE_DIS_MASK 0x00003000UL +#define VPEP_MGCG_CNTL__VPOPP_CLK_GATE_DIS_MASK 0x000c0000UL +#define VPEP_MGCG_CNTL__VPCDC_SOCCLK_G_GATE_DIS_MASK 0x00100000UL +#define VPEP_MGCG_CNTL__VPCDC_SOCCLK_R_GATE_DIS_MASK 0x00200000UL +#define VPEP_MGCG_CNTL__VPCDC_VPECLK_G_GATE_DIS_MASK 0x00400000UL +#define VPEP_MGCG_CNTL__VPCDC_VPECLK_R_GATE_DIS_MASK 0x00800000UL + +// VPCDC_SOFT_RESET +#define VPCDC_SOFT_RESET__VPCDC_SOCCLK_SOFT_RESET_MASK 0x00000001UL +#define VPCDC_SOFT_RESET__VPCDC_VPECLK_SOFT_RESET_MASK 0x00000002UL + +// VPCDC_FE0_SURFACE_CONFIG +#define VPCDC_FE0_SURFACE_CONFIG__SURFACE_PIXEL_FORMAT_FE0_MASK 0x000001ffUL +#define VPCDC_FE0_SURFACE_CONFIG__ROTATION_ANGLE_FE0_MASK 0x00000600UL +#define VPCDC_FE0_SURFACE_CONFIG__H_MIRROR_EN_FE0_MASK 0x00001000UL +#define VPCDC_FE0_SURFACE_CONFIG__PIX_SURFACE_LINEAR_FE0_MASK 0x00002000UL + +// VPCDC_FE0_CROSSBAR_CONFIG +#define VPCDC_FE0_CROSSBAR_CONFIG__CROSSBAR_SRC_ALPHA_FE0_MASK 0x00000003UL +#define VPCDC_FE0_CROSSBAR_CONFIG__CROSSBAR_SRC_Y_G_FE0_MASK 0x0000000cUL +#define VPCDC_FE0_CROSSBAR_CONFIG__CROSSBAR_SRC_CB_B_FE0_MASK 0x00000030UL +#define VPCDC_FE0_CROSSBAR_CONFIG__CROSSBAR_SRC_CR_R_FE0_MASK 0x000000c0UL + +// VPCDC_FE0_VIEWPORT_START_CONFIG +#define VPCDC_FE0_VIEWPORT_START_CONFIG__VIEWPORT_X_START_FE0_MASK 0x00003fffUL +#define VPCDC_FE0_VIEWPORT_START_CONFIG__VIEWPORT_Y_START_FE0_MASK 0x3fff0000UL + +// VPCDC_FE0_VIEWPORT_DIMENSION_CONFIG +#define VPCDC_FE0_VIEWPORT_DIMENSION_CONFIG__VIEWPORT_WIDTH_FE0_MASK 0x00003fffUL +#define VPCDC_FE0_VIEWPORT_DIMENSION_CONFIG__VIEWPORT_HEIGHT_FE0_MASK 0x3fff0000UL + +// VPCDC_FE0_VIEWPORT_START_C_CONFIG +#define VPCDC_FE0_VIEWPORT_START_C_CONFIG__VIEWPORT_X_START_C_FE0_MASK 0x00003fffUL +#define VPCDC_FE0_VIEWPORT_START_C_CONFIG__VIEWPORT_Y_START_C_FE0_MASK 0x3fff0000UL + +// VPCDC_FE0_VIEWPORT_DIMENSION_C_CONFIG +#define VPCDC_FE0_VIEWPORT_DIMENSION_C_CONFIG__VIEWPORT_WIDTH_C_FE0_MASK 0x00003fffUL +#define VPCDC_FE0_VIEWPORT_DIMENSION_C_CONFIG__VIEWPORT_HEIGHT_C_FE0_MASK 0x3fff0000UL + +// VPCDC_BE0_P2B_CONFIG +#define VPCDC_BE0_P2B_CONFIG__VPCDC_BE0_P2B_XBAR_SEL0_MASK 0x00000003UL +#define VPCDC_BE0_P2B_CONFIG__VPCDC_BE0_P2B_XBAR_SEL1_MASK 0x0000000cUL +#define VPCDC_BE0_P2B_CONFIG__VPCDC_BE0_P2B_XBAR_SEL2_MASK 0x00000030UL +#define VPCDC_BE0_P2B_CONFIG__VPCDC_BE0_P2B_XBAR_SEL3_MASK 0x000000c0UL +#define VPCDC_BE0_P2B_CONFIG__VPCDC_BE0_P2B_FORMAT_SEL_MASK 0x0001ff00UL +#define VPCDC_BE0_P2B_CONFIG__VPCDC_BE0_P2B_TILED_MASK 0x00020000UL +#define VPCDC_BE0_P2B_CONFIG__VPCDC_BE0_P2B_X_START_PLANE0_MASK 0x007c0000UL +#define VPCDC_BE0_P2B_CONFIG__VPCDC_BE0_P2B_X_START_PLANE1_MASK 0x0f800000UL + +// VPCDC_BE0_GLOBAL_SYNC_CONFIG +#define VPCDC_BE0_GLOBAL_SYNC_CONFIG__BE0_VUPDATE_OFFSET_MASK 0x000003ffUL +#define VPCDC_BE0_GLOBAL_SYNC_CONFIG__BE0_VUPDATE_WIDTH_MASK 0x000ffc00UL +#define VPCDC_BE0_GLOBAL_SYNC_CONFIG__BE0_VREADY_OFFSET_MASK 0x3ff00000UL + +// VPCDC_GLOBAL_SYNC_TRIGGER +#define VPCDC_GLOBAL_SYNC_TRIGGER__VPBE_GS_TRIG_MASK 0x00000003UL + +// VPCDC_VREADY_STATUS +#define VPCDC_VREADY_STATUS__VPFE_VR_STATUS_MASK 0x00000003UL + +// VPEP_MEM_GLOBAL_PWR_REQ_CNTL +#define VPEP_MEM_GLOBAL_PWR_REQ_CNTL__MEM_GLOBAL_PWR_REQ_DIS_MASK 0x00000001UL + +// VPFE0_MEM_PWR_CNTL +#define VPFE0_MEM_PWR_CNTL__VPFE0_MEM_PWR_FORCE_MASK 0x00000003UL +#define VPFE0_MEM_PWR_CNTL__VPFE0_MEM_PWR_MODE_MASK 0x0000000cUL +#define VPFE0_MEM_PWR_CNTL__VPFE0_MEM_PWR_STATE_MASK 0x00000030UL +#define VPFE0_MEM_PWR_CNTL__VPFE0_MEM_PWR_DIS_MASK 0x00000040UL + +// VPBE0_MEM_PWR_CNTL +#define VPBE0_MEM_PWR_CNTL__VPBE0_MEM_PWR_FORCE_MASK 0x00000003UL +#define VPBE0_MEM_PWR_CNTL__VPBE0_MEM_PWR_MODE_MASK 0x0000000cUL +#define VPBE0_MEM_PWR_CNTL__VPBE0_MEM_PWR_STATE_MASK 0x00000030UL +#define VPBE0_MEM_PWR_CNTL__VPBE0_MEM_PWR_DIS_MASK 0x00000040UL + +// VPCDC_3DLUT_FL_CONFIG +#define VPCDC_3DLUT_FL_CONFIG__VPCDC_3DLUT_FL_MODE_MASK 0x00000003UL +#define VPCDC_3DLUT_FL_CONFIG__VPCDC_3DLUT_FL_CROSSBAR_SRC_G_MASK 0x0000000cUL +#define VPCDC_3DLUT_FL_CONFIG__VPCDC_3DLUT_FL_CROSSBAR_SRC_B_MASK 0x00000030UL +#define VPCDC_3DLUT_FL_CONFIG__VPCDC_3DLUT_FL_CROSSBAR_SRC_R_MASK 0x000000c0UL +#define VPCDC_3DLUT_FL_CONFIG__VPCDC_3DLUT_FL_SIZE_MASK 0x00000100UL + +// VPCDC_CONTROL +#define VPCDC_CONTROL__VPCDC_HISTOGRAM0_EN_MASK 0x00000003UL +#define VPCDC_CONTROL__VPCDC_HISTOGRAM1_EN_MASK 0x0000000cUL +#define VPCDC_CONTROL__VPCDC_FROD_EN_MASK 0x00000100UL + +// VPCNVC_SURFACE_PIXEL_FORMAT +#define VPCNVC_SURFACE_PIXEL_FORMAT__VPCNVC_SURFACE_PIXEL_FORMAT_MASK 0x0000007fUL + +// VPCNVC_FORMAT_CONTROL +#define VPCNVC_FORMAT_CONTROL__FORMAT_EXPANSION_MODE_MASK 0x00000001UL +#define VPCNVC_FORMAT_CONTROL__FORMAT_CNV16_MASK 0x00000010UL +#define VPCNVC_FORMAT_CONTROL__ALPHA_EN_MASK 0x00000100UL +#define VPCNVC_FORMAT_CONTROL__VPCNVC_BYPASS_MASK 0x00001000UL +#define VPCNVC_FORMAT_CONTROL__VPCNVC_BYPASS_MSB_ALIGN_MASK 0x00002000UL +#define VPCNVC_FORMAT_CONTROL__CLAMP_POSITIVE_MASK 0x00010000UL +#define VPCNVC_FORMAT_CONTROL__CLAMP_POSITIVE_C_MASK 0x00020000UL +#define VPCNVC_FORMAT_CONTROL__VPCNVC_UPDATE_PENDING_MASK 0x00100000UL + +// VPCNVC_FCNV_FP_BIAS_R +#define VPCNVC_FCNV_FP_BIAS_R__FCNV_FP_BIAS_R_MASK 0x0007ffffUL + +// VPCNVC_FCNV_FP_BIAS_G +#define VPCNVC_FCNV_FP_BIAS_G__FCNV_FP_BIAS_G_MASK 0x0007ffffUL + +// VPCNVC_FCNV_FP_BIAS_B +#define VPCNVC_FCNV_FP_BIAS_B__FCNV_FP_BIAS_B_MASK 0x0007ffffUL + +// VPCNVC_FCNV_FP_SCALE_R +#define VPCNVC_FCNV_FP_SCALE_R__FCNV_FP_SCALE_R_MASK 0x0007ffffUL + +// VPCNVC_FCNV_FP_SCALE_G +#define VPCNVC_FCNV_FP_SCALE_G__FCNV_FP_SCALE_G_MASK 0x0007ffffUL + +// VPCNVC_FCNV_FP_SCALE_B +#define VPCNVC_FCNV_FP_SCALE_B__FCNV_FP_SCALE_B_MASK 0x0007ffffUL + +// VPCNVC_COLOR_KEYER_CONTROL +#define VPCNVC_COLOR_KEYER_CONTROL__COLOR_KEYER_EN_MASK 0x00000001UL +#define VPCNVC_COLOR_KEYER_CONTROL__LUMA_KEYER_EN_MASK 0x00000002UL +#define VPCNVC_COLOR_KEYER_CONTROL__COLOR_KEYER_MODE_MASK 0x00000030UL + +// VPCNVC_COLOR_KEYER_ALPHA +#define VPCNVC_COLOR_KEYER_ALPHA__COLOR_KEYER_ALPHA_LOW_MASK 0x0000ffffUL +#define VPCNVC_COLOR_KEYER_ALPHA__COLOR_KEYER_ALPHA_HIGH_MASK 0xffff0000UL + +// VPCNVC_COLOR_KEYER_RED +#define VPCNVC_COLOR_KEYER_RED__COLOR_KEYER_RED_LOW_MASK 0x0000ffffUL +#define VPCNVC_COLOR_KEYER_RED__COLOR_KEYER_RED_HIGH_MASK 0xffff0000UL + +// VPCNVC_COLOR_KEYER_GREEN +#define VPCNVC_COLOR_KEYER_GREEN__COLOR_KEYER_GREEN_LOW_MASK 0x0000ffffUL +#define VPCNVC_COLOR_KEYER_GREEN__COLOR_KEYER_GREEN_HIGH_MASK 0xffff0000UL + +// VPCNVC_COLOR_KEYER_BLUE +#define VPCNVC_COLOR_KEYER_BLUE__COLOR_KEYER_BLUE_LOW_MASK 0x0000ffffUL +#define VPCNVC_COLOR_KEYER_BLUE__COLOR_KEYER_BLUE_HIGH_MASK 0xffff0000UL + +// VPCNVC_ALPHA_2BIT_LUT01 +#define VPCNVC_ALPHA_2BIT_LUT01__ALPHA_2BIT_LUT0_MASK 0x00000fffUL +#define VPCNVC_ALPHA_2BIT_LUT01__ALPHA_2BIT_LUT1_MASK 0x0fff0000UL + +// VPCNVC_ALPHA_2BIT_LUT23 +#define VPCNVC_ALPHA_2BIT_LUT23__ALPHA_2BIT_LUT2_MASK 0x00000fffUL +#define VPCNVC_ALPHA_2BIT_LUT23__ALPHA_2BIT_LUT3_MASK 0x0fff0000UL + +// VPCNVC_PRE_DEALPHA +#define VPCNVC_PRE_DEALPHA__PRE_DEALPHA_EN_MASK 0x00000001UL +#define VPCNVC_PRE_DEALPHA__PRE_DEALPHA_ABLND_EN_MASK 0x00000010UL + +// VPCNVC_PRE_CSC_MODE +#define VPCNVC_PRE_CSC_MODE__PRE_CSC_MODE_MASK 0x00000001UL +#define VPCNVC_PRE_CSC_MODE__PRE_CSC_MODE_CURRENT_MASK 0x00000004UL + +// VPCNVC_PRE_CSC_C11_C12 +#define VPCNVC_PRE_CSC_C11_C12__PRE_CSC_C11_MASK 0x0000ffffUL +#define VPCNVC_PRE_CSC_C11_C12__PRE_CSC_C12_MASK 0xffff0000UL + +// VPCNVC_PRE_CSC_C13_C14 +#define VPCNVC_PRE_CSC_C13_C14__PRE_CSC_C13_MASK 0x0000ffffUL +#define VPCNVC_PRE_CSC_C13_C14__PRE_CSC_C14_MASK 0xffff0000UL + +// VPCNVC_PRE_CSC_C21_C22 +#define VPCNVC_PRE_CSC_C21_C22__PRE_CSC_C21_MASK 0x0000ffffUL +#define VPCNVC_PRE_CSC_C21_C22__PRE_CSC_C22_MASK 0xffff0000UL + +// VPCNVC_PRE_CSC_C23_C24 +#define VPCNVC_PRE_CSC_C23_C24__PRE_CSC_C23_MASK 0x0000ffffUL +#define VPCNVC_PRE_CSC_C23_C24__PRE_CSC_C24_MASK 0xffff0000UL + +// VPCNVC_PRE_CSC_C31_C32 +#define VPCNVC_PRE_CSC_C31_C32__PRE_CSC_C31_MASK 0x0000ffffUL +#define VPCNVC_PRE_CSC_C31_C32__PRE_CSC_C32_MASK 0xffff0000UL + +// VPCNVC_PRE_CSC_C33_C34 +#define VPCNVC_PRE_CSC_C33_C34__PRE_CSC_C33_MASK 0x0000ffffUL +#define VPCNVC_PRE_CSC_C33_C34__PRE_CSC_C34_MASK 0xffff0000UL + +// VPCNVC_COEF_FORMAT +#define VPCNVC_COEF_FORMAT__PRE_CSC_COEF_FORMAT_MASK 0x00000001UL + +// VPCNVC_PRE_DEGAM +#define VPCNVC_PRE_DEGAM__PRE_DEGAM_MODE_MASK 0x00000003UL +#define VPCNVC_PRE_DEGAM__PRE_DEGAM_SELECT_MASK 0x00000070UL + +// VPCNVC_PRE_REALPHA +#define VPCNVC_PRE_REALPHA__PRE_REALPHA_EN_MASK 0x00000001UL +#define VPCNVC_PRE_REALPHA__PRE_REALPHA_ABLND_EN_MASK 0x00000010UL + +// VPDSCL_COEF_RAM_TAP_SELECT +#define VPDSCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_TAP_PAIR_IDX_MASK 0x00000003UL +#define VPDSCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_PHASE_MASK 0x00003f00UL +#define VPDSCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_FILTER_TYPE_MASK 0x00070000UL + +// VPDSCL_COEF_RAM_TAP_DATA +#define VPDSCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_EVEN_TAP_COEF_MASK 0x00003fffUL +#define VPDSCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_EVEN_TAP_COEF_EN_MASK 0x00008000UL +#define VPDSCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_ODD_TAP_COEF_MASK 0x3fff0000UL +#define VPDSCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_ODD_TAP_COEF_EN_MASK 0x80000000UL + +// VPDSCL_MODE +#define VPDSCL_MODE__VPDSCL_MODE_MASK 0x00000007UL +#define VPDSCL_MODE__SCL_COEF_RAM_SELECT_CURRENT_MASK 0x00001000UL +#define VPDSCL_MODE__SCL_CHROMA_COEF_MODE_MASK 0x00010000UL +#define VPDSCL_MODE__SCL_ALPHA_COEF_MODE_MASK 0x00100000UL +#define VPDSCL_MODE__SCL_COEF_RAM_SELECT_RD_MASK 0x01000000UL + +// VPDSCL_TAP_CONTROL +#define VPDSCL_TAP_CONTROL__SCL_V_NUM_TAPS_MASK 0x00000007UL +#define VPDSCL_TAP_CONTROL__SCL_H_NUM_TAPS_MASK 0x00000070UL +#define VPDSCL_TAP_CONTROL__SCL_V_NUM_TAPS_C_MASK 0x00000700UL +#define VPDSCL_TAP_CONTROL__SCL_H_NUM_TAPS_C_MASK 0x00007000UL + +// VPDSCL_CONTROL +#define VPDSCL_CONTROL__SCL_BOUNDARY_MODE_MASK 0x00000001UL + +// VPDSCL_2TAP_CONTROL +#define VPDSCL_2TAP_CONTROL__SCL_H_2TAP_HARDCODE_COEF_EN_MASK 0x00000001UL +#define VPDSCL_2TAP_CONTROL__SCL_H_2TAP_SHARP_EN_MASK 0x00000010UL +#define VPDSCL_2TAP_CONTROL__SCL_H_2TAP_SHARP_FACTOR_MASK 0x00000700UL +#define VPDSCL_2TAP_CONTROL__SCL_V_2TAP_HARDCODE_COEF_EN_MASK 0x00010000UL +#define VPDSCL_2TAP_CONTROL__SCL_V_2TAP_SHARP_EN_MASK 0x00100000UL +#define VPDSCL_2TAP_CONTROL__SCL_V_2TAP_SHARP_FACTOR_MASK 0x07000000UL + +// VPDSCL_MANUAL_REPLICATE_CONTROL +#define VPDSCL_MANUAL_REPLICATE_CONTROL__SCL_V_MANUAL_REPLICATE_FACTOR_MASK 0x0000000fUL +#define VPDSCL_MANUAL_REPLICATE_CONTROL__SCL_H_MANUAL_REPLICATE_FACTOR_MASK 0x00000f00UL + +// VPDSCL_HORZ_FILTER_SCALE_RATIO +#define VPDSCL_HORZ_FILTER_SCALE_RATIO__SCL_H_SCALE_RATIO_MASK 0x07ffffffUL + +// VPDSCL_HORZ_FILTER_INIT +#define VPDSCL_HORZ_FILTER_INIT__SCL_H_INIT_FRAC_MASK 0x00ffffffUL +#define VPDSCL_HORZ_FILTER_INIT__SCL_H_INIT_INT_MASK 0x0f000000UL + +// VPDSCL_HORZ_FILTER_SCALE_RATIO_C +#define VPDSCL_HORZ_FILTER_SCALE_RATIO_C__SCL_H_SCALE_RATIO_C_MASK 0x07ffffffUL + +// VPDSCL_HORZ_FILTER_INIT_C +#define VPDSCL_HORZ_FILTER_INIT_C__SCL_H_INIT_FRAC_C_MASK 0x00ffffffUL +#define VPDSCL_HORZ_FILTER_INIT_C__SCL_H_INIT_INT_C_MASK 0x0f000000UL + +// VPDSCL_VERT_FILTER_SCALE_RATIO +#define VPDSCL_VERT_FILTER_SCALE_RATIO__SCL_V_SCALE_RATIO_MASK 0x07ffffffUL + +// VPDSCL_VERT_FILTER_INIT +#define VPDSCL_VERT_FILTER_INIT__SCL_V_INIT_FRAC_MASK 0x00ffffffUL +#define VPDSCL_VERT_FILTER_INIT__SCL_V_INIT_INT_MASK 0x0f000000UL + +// VPDSCL_VERT_FILTER_INIT_BOT +#define VPDSCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_FRAC_BOT_MASK 0x00ffffffUL +#define VPDSCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_INT_BOT_MASK 0x0f000000UL + +// VPDSCL_VERT_FILTER_SCALE_RATIO_C +#define VPDSCL_VERT_FILTER_SCALE_RATIO_C__SCL_V_SCALE_RATIO_C_MASK 0x07ffffffUL + +// VPDSCL_VERT_FILTER_INIT_C +#define VPDSCL_VERT_FILTER_INIT_C__SCL_V_INIT_FRAC_C_MASK 0x00ffffffUL +#define VPDSCL_VERT_FILTER_INIT_C__SCL_V_INIT_INT_C_MASK 0x0f000000UL + +// VPDSCL_VERT_FILTER_INIT_BOT_C +#define VPDSCL_VERT_FILTER_INIT_BOT_C__SCL_V_INIT_FRAC_BOT_C_MASK 0x00ffffffUL +#define VPDSCL_VERT_FILTER_INIT_BOT_C__SCL_V_INIT_INT_BOT_C_MASK 0x0f000000UL + +// VPDSCL_BLACK_COLOR +#define VPDSCL_BLACK_COLOR__SCL_BLACK_COLOR_RGB_Y_MASK 0x0000ffffUL +#define VPDSCL_BLACK_COLOR__SCL_BLACK_COLOR_CBCR_MASK 0xffff0000UL + +// VPDSCL_UPDATE +#define VPDSCL_UPDATE__SCL_UPDATE_PENDING_MASK 0x00000001UL + +// VPDSCL_AUTOCAL +#define VPDSCL_AUTOCAL__AUTOCAL_MODE_MASK 0x00000003UL + +// VPDSCL_EXT_OVERSCAN_LEFT_RIGHT +#define VPDSCL_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_RIGHT_MASK 0x00001fffUL +#define VPDSCL_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_LEFT_MASK 0x1fff0000UL + +// VPDSCL_EXT_OVERSCAN_TOP_BOTTOM +#define VPDSCL_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_BOTTOM_MASK 0x00001fffUL +#define VPDSCL_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_TOP_MASK 0x1fff0000UL + +// VPOTG_H_BLANK +#define VPOTG_H_BLANK__OTG_H_BLANK_START_MASK 0x00003fffUL +#define VPOTG_H_BLANK__OTG_H_BLANK_END_MASK 0x3fff0000UL + +// VPOTG_V_BLANK +#define VPOTG_V_BLANK__OTG_V_BLANK_START_MASK 0x00003fffUL +#define VPOTG_V_BLANK__OTG_V_BLANK_END_MASK 0x3fff0000UL + +// VPDSCL_RECOUT_START +#define VPDSCL_RECOUT_START__RECOUT_START_X_MASK 0x00001fffUL +#define VPDSCL_RECOUT_START__RECOUT_START_Y_MASK 0x1fff0000UL + +// VPDSCL_RECOUT_SIZE +#define VPDSCL_RECOUT_SIZE__RECOUT_WIDTH_MASK 0x00003fffUL +#define VPDSCL_RECOUT_SIZE__RECOUT_HEIGHT_MASK 0x3fff0000UL + +// VPMPC_SIZE +#define VPMPC_SIZE__VPMPC_WIDTH_MASK 0x00003fffUL +#define VPMPC_SIZE__VPMPC_HEIGHT_MASK 0x3fff0000UL + +// VPLB_DATA_FORMAT +#define VPLB_DATA_FORMAT__ALPHA_EN_MASK 0x00000010UL + +// VPLB_MEMORY_CTRL +#define VPLB_MEMORY_CTRL__LB_MAX_PARTITIONS_MASK 0x00003f00UL +#define VPLB_MEMORY_CTRL__LB_NUM_PARTITIONS_MASK 0x007f0000UL +#define VPLB_MEMORY_CTRL__LB_NUM_PARTITIONS_C_MASK 0x7f000000UL + +// VPLB_V_COUNTER +#define VPLB_V_COUNTER__V_COUNTER_MASK 0x00001fffUL +#define VPLB_V_COUNTER__V_COUNTER_C_MASK 0x1fff0000UL + +// VPDSCL_MEM_PWR_CTRL +#define VPDSCL_MEM_PWR_CTRL__LUT_MEM_PWR_FORCE_MASK 0x00000003UL +#define VPDSCL_MEM_PWR_CTRL__LUT_MEM_PWR_DIS_MASK 0x00000004UL +#define VPDSCL_MEM_PWR_CTRL__LB_G1_MEM_PWR_FORCE_MASK 0x00000030UL +#define VPDSCL_MEM_PWR_CTRL__LB_G1_MEM_PWR_DIS_MASK 0x00000040UL +#define VPDSCL_MEM_PWR_CTRL__LB_G2_MEM_PWR_FORCE_MASK 0x00000300UL +#define VPDSCL_MEM_PWR_CTRL__LB_G2_MEM_PWR_DIS_MASK 0x00000400UL +#define VPDSCL_MEM_PWR_CTRL__LB_MEM_PWR_MODE_MASK 0x10000000UL + +// VPDSCL_MEM_PWR_STATUS +#define VPDSCL_MEM_PWR_STATUS__LUT_MEM_PWR_STATE_MASK 0x00000003UL +#define VPDSCL_MEM_PWR_STATUS__LB_G1_MEM_PWR_STATE_MASK 0x0000000cUL +#define VPDSCL_MEM_PWR_STATUS__LB_G2_MEM_PWR_STATE_MASK 0x00000030UL + +// VPDSCL_EASF_H_MODE +#define VPDSCL_EASF_H_MODE__SCL_EASF_H_EN_MASK 0x00000001UL +#define VPDSCL_EASF_H_MODE__SCL_EASF_H_RINGEST_FORCE_EN_MASK 0x00000010UL +#define VPDSCL_EASF_H_MODE__SCL_EASF_H_2TAP_SHARP_FACTOR_MASK 0x00003f00UL + +// VPDSCL_EASF_V_MODE +#define VPDSCL_EASF_V_MODE__SCL_EASF_V_EN_MASK 0x00000001UL +#define VPDSCL_EASF_V_MODE__SCL_EASF_V_RINGEST_FORCE_EN_MASK 0x00000010UL +#define VPDSCL_EASF_V_MODE__SCL_EASF_V_2TAP_SHARP_FACTOR_MASK 0x00003f00UL + +// VPDSCL_SC_MODE +#define VPDSCL_SC_MODE__SCL_SC_MATRIX_MODE_MASK 0x00000001UL +#define VPDSCL_SC_MODE__SCL_SC_LTONL_EN_MASK 0x00000100UL + +// VPDSCL_SC_MATRIX_C0C1 +#define VPDSCL_SC_MATRIX_C0C1__SCL_SC_MATRIX_C0_MASK 0x0000ffffUL +#define VPDSCL_SC_MATRIX_C0C1__SCL_SC_MATRIX_C1_MASK 0xffff0000UL + +// VPDSCL_SC_MATRIX_C2C3 +#define VPDSCL_SC_MATRIX_C2C3__SCL_SC_MATRIX_C2_MASK 0x0000ffffUL +#define VPDSCL_SC_MATRIX_C2C3__SCL_SC_MATRIX_C3_MASK 0xffff0000UL + +// VPDSCL_EASF_H_RINGEST_EVENTAP_GAIN +#define VPDSCL_EASF_H_RINGEST_EVENTAP_GAIN__SCL_EASF_H_RINGEST_EVENTAP_GAIN1_MASK 0x0000ffffUL +#define VPDSCL_EASF_H_RINGEST_EVENTAP_GAIN__SCL_EASF_H_RINGEST_EVENTAP_GAIN2_MASK 0xffff0000UL + +// VPDSCL_EASF_H_RINGEST_EVENTAP_REDUCE +#define VPDSCL_EASF_H_RINGEST_EVENTAP_REDUCE__SCL_EASF_H_RINGEST_EVENTAP_REDUCEG1_MASK 0x0000ffffUL +#define VPDSCL_EASF_H_RINGEST_EVENTAP_REDUCE__SCL_EASF_H_RINGEST_EVENTAP_REDUCEG2_MASK 0xffff0000UL + +// VPDSCL_EASF_V_RINGEST_EVENTAP_GAIN +#define VPDSCL_EASF_V_RINGEST_EVENTAP_GAIN__SCL_EASF_V_RINGEST_EVENTAP_GAIN1_MASK 0x0000ffffUL +#define VPDSCL_EASF_V_RINGEST_EVENTAP_GAIN__SCL_EASF_V_RINGEST_EVENTAP_GAIN2_MASK 0xffff0000UL + +// VPDSCL_EASF_V_RINGEST_EVENTAP_REDUCE +#define VPDSCL_EASF_V_RINGEST_EVENTAP_REDUCE__SCL_EASF_V_RINGEST_EVENTAP_REDUCEG1_MASK 0x0000ffffUL +#define VPDSCL_EASF_V_RINGEST_EVENTAP_REDUCE__SCL_EASF_V_RINGEST_EVENTAP_REDUCEG2_MASK 0xffff0000UL + +// VPDSCL_EASF_V_RINGEST_3TAP_CNTL1 +#define VPDSCL_EASF_V_RINGEST_3TAP_CNTL1__SCL_EASF_V_RINGEST_3TAP_DNTILT_UPTILT_MASK 0x0000ffffUL +#define VPDSCL_EASF_V_RINGEST_3TAP_CNTL1__SCL_EASF_V_RINGEST_3TAP_UPTILT_MAXVAL_MASK 0xffff0000UL + +// VPDSCL_EASF_V_RINGEST_3TAP_CNTL2 +#define VPDSCL_EASF_V_RINGEST_3TAP_CNTL2__SCL_EASF_V_RINGEST_3TAP_DNTILT_SLOPE_MASK 0x0000ffffUL +#define VPDSCL_EASF_V_RINGEST_3TAP_CNTL2__SCL_EASF_V_RINGEST_3TAP_UPTILT1_SLOPE_MASK 0xffff0000UL + +// VPDSCL_EASF_V_RINGEST_3TAP_CNTL3 +#define VPDSCL_EASF_V_RINGEST_3TAP_CNTL3__SCL_EASF_V_RINGEST_3TAP_UPTILT2_SLOPE_MASK 0x0000ffffUL +#define VPDSCL_EASF_V_RINGEST_3TAP_CNTL3__SCL_EASF_V_RINGEST_3TAP_UPTILT2_OFFSET_MASK 0xffff0000UL + +// VPDSCL_EASF_RINGEST_FORCE +#define VPDSCL_EASF_RINGEST_FORCE__SCL_EASF_H_RINGEST_FORCE_MASK 0x0000ffffUL +#define VPDSCL_EASF_RINGEST_FORCE__SCL_EASF_V_RINGEST_FORCE_MASK 0xffff0000UL + +// VPDSCL_EASF_H_BF_CNTL +#define VPDSCL_EASF_H_BF_CNTL__SCL_EASF_H_BF1_EN_MASK 0x00000001UL +#define VPDSCL_EASF_H_BF_CNTL__SCL_EASF_H_BF2_MODE_MASK 0x00000f00UL +#define VPDSCL_EASF_H_BF_CNTL__SCL_EASF_H_BF3_MODE_MASK 0x00030000UL +#define VPDSCL_EASF_H_BF_CNTL__SCL_EASF_H_BF2_FLAT1_GAIN_MASK 0x00f00000UL +#define VPDSCL_EASF_H_BF_CNTL__SCL_EASF_H_BF2_FLAT2_GAIN_MASK 0x0f000000UL +#define VPDSCL_EASF_H_BF_CNTL__SCL_EASF_H_BF2_ROC_GAIN_MASK 0xf0000000UL + +// VPDSCL_EASF_H_BF_FINAL_MAX_MIN +#define VPDSCL_EASF_H_BF_FINAL_MAX_MIN__SCL_EASF_H_BF_MAXA_MASK 0x0000003fUL +#define VPDSCL_EASF_H_BF_FINAL_MAX_MIN__SCL_EASF_H_BF_MAXB_MASK 0x00003f00UL +#define VPDSCL_EASF_H_BF_FINAL_MAX_MIN__SCL_EASF_H_BF_MINA_MASK 0x003f0000UL +#define VPDSCL_EASF_H_BF_FINAL_MAX_MIN__SCL_EASF_H_BF_MINB_MASK 0x3f000000UL + +// VPDSCL_EASF_V_BF_CNTL +#define VPDSCL_EASF_V_BF_CNTL__SCL_EASF_V_BF1_EN_MASK 0x00000001UL +#define VPDSCL_EASF_V_BF_CNTL__SCL_EASF_V_BF2_MODE_MASK 0x00000f00UL +#define VPDSCL_EASF_V_BF_CNTL__SCL_EASF_V_BF3_MODE_MASK 0x00030000UL +#define VPDSCL_EASF_V_BF_CNTL__SCL_EASF_V_BF2_FLAT1_GAIN_MASK 0x00f00000UL +#define VPDSCL_EASF_V_BF_CNTL__SCL_EASF_V_BF2_FLAT2_GAIN_MASK 0x0f000000UL +#define VPDSCL_EASF_V_BF_CNTL__SCL_EASF_V_BF2_ROC_GAIN_MASK 0xf0000000UL + +// VPDSCL_EASF_H_BF1_PWL_SEG0 +#define VPDSCL_EASF_H_BF1_PWL_SEG0__SCL_EASF_H_BF1_PWL_IN_SEG0_MASK 0x000007ffUL +#define VPDSCL_EASF_H_BF1_PWL_SEG0__SCL_EASF_H_BF1_PWL_BASE_SEG0_MASK 0x0003f000UL +#define VPDSCL_EASF_H_BF1_PWL_SEG0__SCL_EASF_H_BF1_PWL_SLOPE_SEG0_MASK 0x7ff00000UL + +// VPDSCL_EASF_H_BF1_PWL_SEG1 +#define VPDSCL_EASF_H_BF1_PWL_SEG1__SCL_EASF_H_BF1_PWL_IN_SEG1_MASK 0x000007ffUL +#define VPDSCL_EASF_H_BF1_PWL_SEG1__SCL_EASF_H_BF1_PWL_BASE_SEG1_MASK 0x0003f000UL +#define VPDSCL_EASF_H_BF1_PWL_SEG1__SCL_EASF_H_BF1_PWL_SLOPE_SEG1_MASK 0x7ff00000UL + +// VPDSCL_EASF_H_BF1_PWL_SEG2 +#define VPDSCL_EASF_H_BF1_PWL_SEG2__SCL_EASF_H_BF1_PWL_IN_SEG2_MASK 0x000007ffUL +#define VPDSCL_EASF_H_BF1_PWL_SEG2__SCL_EASF_H_BF1_PWL_BASE_SEG2_MASK 0x0003f000UL +#define VPDSCL_EASF_H_BF1_PWL_SEG2__SCL_EASF_H_BF1_PWL_SLOPE_SEG2_MASK 0x7ff00000UL + +// VPDSCL_EASF_H_BF1_PWL_SEG3 +#define VPDSCL_EASF_H_BF1_PWL_SEG3__SCL_EASF_H_BF1_PWL_IN_SEG3_MASK 0x000007ffUL +#define VPDSCL_EASF_H_BF1_PWL_SEG3__SCL_EASF_H_BF1_PWL_BASE_SEG3_MASK 0x0003f000UL +#define VPDSCL_EASF_H_BF1_PWL_SEG3__SCL_EASF_H_BF1_PWL_SLOPE_SEG3_MASK 0x7ff00000UL + +// VPDSCL_EASF_H_BF1_PWL_SEG4 +#define VPDSCL_EASF_H_BF1_PWL_SEG4__SCL_EASF_H_BF1_PWL_IN_SEG4_MASK 0x000007ffUL +#define VPDSCL_EASF_H_BF1_PWL_SEG4__SCL_EASF_H_BF1_PWL_BASE_SEG4_MASK 0x0003f000UL +#define VPDSCL_EASF_H_BF1_PWL_SEG4__SCL_EASF_H_BF1_PWL_SLOPE_SEG4_MASK 0x7ff00000UL + +// VPDSCL_EASF_H_BF1_PWL_SEG5 +#define VPDSCL_EASF_H_BF1_PWL_SEG5__SCL_EASF_H_BF1_PWL_IN_SEG5_MASK 0x000007ffUL +#define VPDSCL_EASF_H_BF1_PWL_SEG5__SCL_EASF_H_BF1_PWL_BASE_SEG5_MASK 0x0003f000UL +#define VPDSCL_EASF_H_BF1_PWL_SEG5__SCL_EASF_H_BF1_PWL_SLOPE_SEG5_MASK 0x7ff00000UL + +// VPDSCL_EASF_H_BF1_PWL_SEG6 +#define VPDSCL_EASF_H_BF1_PWL_SEG6__SCL_EASF_H_BF1_PWL_IN_SEG6_MASK 0x000007ffUL +#define VPDSCL_EASF_H_BF1_PWL_SEG6__SCL_EASF_H_BF1_PWL_BASE_SEG6_MASK 0x0003f000UL +#define VPDSCL_EASF_H_BF1_PWL_SEG6__SCL_EASF_H_BF1_PWL_SLOPE_SEG6_MASK 0x7ff00000UL + +// VPDSCL_EASF_H_BF1_PWL_SEG7 +#define VPDSCL_EASF_H_BF1_PWL_SEG7__SCL_EASF_H_BF1_PWL_IN_SEG7_MASK 0x000007ffUL +#define VPDSCL_EASF_H_BF1_PWL_SEG7__SCL_EASF_H_BF1_PWL_BASE_SEG7_MASK 0x0003f000UL + +// VPDSCL_EASF_V_BF1_PWL_SEG0 +#define VPDSCL_EASF_V_BF1_PWL_SEG0__SCL_EASF_V_BF1_PWL_IN_SEG0_MASK 0x000007ffUL +#define VPDSCL_EASF_V_BF1_PWL_SEG0__SCL_EASF_V_BF1_PWL_BASE_SEG0_MASK 0x0003f000UL +#define VPDSCL_EASF_V_BF1_PWL_SEG0__SCL_EASF_V_BF1_PWL_SLOPE_SEG0_MASK 0x7ff00000UL + +// VPDSCL_EASF_V_BF1_PWL_SEG1 +#define VPDSCL_EASF_V_BF1_PWL_SEG1__SCL_EASF_V_BF1_PWL_IN_SEG1_MASK 0x000007ffUL +#define VPDSCL_EASF_V_BF1_PWL_SEG1__SCL_EASF_V_BF1_PWL_BASE_SEG1_MASK 0x0003f000UL +#define VPDSCL_EASF_V_BF1_PWL_SEG1__SCL_EASF_V_BF1_PWL_SLOPE_SEG1_MASK 0x7ff00000UL + +// VPDSCL_EASF_V_BF1_PWL_SEG2 +#define VPDSCL_EASF_V_BF1_PWL_SEG2__SCL_EASF_V_BF1_PWL_IN_SEG2_MASK 0x000007ffUL +#define VPDSCL_EASF_V_BF1_PWL_SEG2__SCL_EASF_V_BF1_PWL_BASE_SEG2_MASK 0x0003f000UL +#define VPDSCL_EASF_V_BF1_PWL_SEG2__SCL_EASF_V_BF1_PWL_SLOPE_SEG2_MASK 0x7ff00000UL + +// VPDSCL_EASF_V_BF1_PWL_SEG3 +#define VPDSCL_EASF_V_BF1_PWL_SEG3__SCL_EASF_V_BF1_PWL_IN_SEG3_MASK 0x000007ffUL +#define VPDSCL_EASF_V_BF1_PWL_SEG3__SCL_EASF_V_BF1_PWL_BASE_SEG3_MASK 0x0003f000UL +#define VPDSCL_EASF_V_BF1_PWL_SEG3__SCL_EASF_V_BF1_PWL_SLOPE_SEG3_MASK 0x7ff00000UL + +// VPDSCL_EASF_V_BF1_PWL_SEG4 +#define VPDSCL_EASF_V_BF1_PWL_SEG4__SCL_EASF_V_BF1_PWL_IN_SEG4_MASK 0x000007ffUL +#define VPDSCL_EASF_V_BF1_PWL_SEG4__SCL_EASF_V_BF1_PWL_BASE_SEG4_MASK 0x0003f000UL +#define VPDSCL_EASF_V_BF1_PWL_SEG4__SCL_EASF_V_BF1_PWL_SLOPE_SEG4_MASK 0x7ff00000UL + +// VPDSCL_EASF_V_BF1_PWL_SEG5 +#define VPDSCL_EASF_V_BF1_PWL_SEG5__SCL_EASF_V_BF1_PWL_IN_SEG5_MASK 0x000007ffUL +#define VPDSCL_EASF_V_BF1_PWL_SEG5__SCL_EASF_V_BF1_PWL_BASE_SEG5_MASK 0x0003f000UL +#define VPDSCL_EASF_V_BF1_PWL_SEG5__SCL_EASF_V_BF1_PWL_SLOPE_SEG5_MASK 0x7ff00000UL + +// VPDSCL_EASF_V_BF1_PWL_SEG6 +#define VPDSCL_EASF_V_BF1_PWL_SEG6__SCL_EASF_V_BF1_PWL_IN_SEG6_MASK 0x000007ffUL +#define VPDSCL_EASF_V_BF1_PWL_SEG6__SCL_EASF_V_BF1_PWL_BASE_SEG6_MASK 0x0003f000UL +#define VPDSCL_EASF_V_BF1_PWL_SEG6__SCL_EASF_V_BF1_PWL_SLOPE_SEG6_MASK 0x7ff00000UL + +// VPDSCL_EASF_V_BF1_PWL_SEG7 +#define VPDSCL_EASF_V_BF1_PWL_SEG7__SCL_EASF_V_BF1_PWL_IN_SEG7_MASK 0x000007ffUL +#define VPDSCL_EASF_V_BF1_PWL_SEG7__SCL_EASF_V_BF1_PWL_BASE_SEG7_MASK 0x0003f000UL + +// VPDSCL_EASF_H_BF3_PWL_SEG0 +#define VPDSCL_EASF_H_BF3_PWL_SEG0__SCL_EASF_H_BF3_PWL_IN_SEG0_MASK 0x00000fffUL +#define VPDSCL_EASF_H_BF3_PWL_SEG0__SCL_EASF_H_BF3_PWL_BASE_SEG0_MASK 0x0007f000UL +#define VPDSCL_EASF_H_BF3_PWL_SEG0__SCL_EASF_H_BF3_PWL_SLOPE_SEG0_MASK 0xfff80000UL + +// VPDSCL_EASF_H_BF3_PWL_SEG1 +#define VPDSCL_EASF_H_BF3_PWL_SEG1__SCL_EASF_H_BF3_PWL_IN_SEG1_MASK 0x00000fffUL +#define VPDSCL_EASF_H_BF3_PWL_SEG1__SCL_EASF_H_BF3_PWL_BASE_SEG1_MASK 0x0007f000UL +#define VPDSCL_EASF_H_BF3_PWL_SEG1__SCL_EASF_H_BF3_PWL_SLOPE_SEG1_MASK 0xfff80000UL + +// VPDSCL_EASF_H_BF3_PWL_SEG2 +#define VPDSCL_EASF_H_BF3_PWL_SEG2__SCL_EASF_H_BF3_PWL_IN_SEG2_MASK 0x00000fffUL +#define VPDSCL_EASF_H_BF3_PWL_SEG2__SCL_EASF_H_BF3_PWL_BASE_SEG2_MASK 0x0007f000UL +#define VPDSCL_EASF_H_BF3_PWL_SEG2__SCL_EASF_H_BF3_PWL_SLOPE_SEG2_MASK 0xfff80000UL + +// VPDSCL_EASF_H_BF3_PWL_SEG3 +#define VPDSCL_EASF_H_BF3_PWL_SEG3__SCL_EASF_H_BF3_PWL_IN_SEG3_MASK 0x00000fffUL +#define VPDSCL_EASF_H_BF3_PWL_SEG3__SCL_EASF_H_BF3_PWL_BASE_SEG3_MASK 0x0007f000UL +#define VPDSCL_EASF_H_BF3_PWL_SEG3__SCL_EASF_H_BF3_PWL_SLOPE_SEG3_MASK 0xfff80000UL + +// VPDSCL_EASF_H_BF3_PWL_SEG4 +#define VPDSCL_EASF_H_BF3_PWL_SEG4__SCL_EASF_H_BF3_PWL_IN_SEG4_MASK 0x00000fffUL +#define VPDSCL_EASF_H_BF3_PWL_SEG4__SCL_EASF_H_BF3_PWL_BASE_SEG4_MASK 0x0007f000UL +#define VPDSCL_EASF_H_BF3_PWL_SEG4__SCL_EASF_H_BF3_PWL_SLOPE_SEG4_MASK 0xfff80000UL + +// VPDSCL_EASF_H_BF3_PWL_SEG5 +#define VPDSCL_EASF_H_BF3_PWL_SEG5__SCL_EASF_H_BF3_PWL_IN_SEG5_MASK 0x00000fffUL +#define VPDSCL_EASF_H_BF3_PWL_SEG5__SCL_EASF_H_BF3_PWL_BASE_SEG5_MASK 0x0007f000UL + +// VPDSCL_EASF_V_BF3_PWL_SEG0 +#define VPDSCL_EASF_V_BF3_PWL_SEG0__SCL_EASF_V_BF3_PWL_IN_SEG0_MASK 0x00000fffUL +#define VPDSCL_EASF_V_BF3_PWL_SEG0__SCL_EASF_V_BF3_PWL_BASE_SEG0_MASK 0x0007f000UL +#define VPDSCL_EASF_V_BF3_PWL_SEG0__SCL_EASF_V_BF3_PWL_SLOPE_SEG0_MASK 0xfff80000UL + +// VPDSCL_EASF_V_BF3_PWL_SEG1 +#define VPDSCL_EASF_V_BF3_PWL_SEG1__SCL_EASF_V_BF3_PWL_IN_SEG1_MASK 0x00000fffUL +#define VPDSCL_EASF_V_BF3_PWL_SEG1__SCL_EASF_V_BF3_PWL_BASE_SEG1_MASK 0x0007f000UL +#define VPDSCL_EASF_V_BF3_PWL_SEG1__SCL_EASF_V_BF3_PWL_SLOPE_SEG1_MASK 0xfff80000UL + +// VPDSCL_EASF_V_BF3_PWL_SEG2 +#define VPDSCL_EASF_V_BF3_PWL_SEG2__SCL_EASF_V_BF3_PWL_IN_SEG2_MASK 0x00000fffUL +#define VPDSCL_EASF_V_BF3_PWL_SEG2__SCL_EASF_V_BF3_PWL_BASE_SEG2_MASK 0x0007f000UL +#define VPDSCL_EASF_V_BF3_PWL_SEG2__SCL_EASF_V_BF3_PWL_SLOPE_SEG2_MASK 0xfff80000UL + +// VPDSCL_EASF_V_BF3_PWL_SEG3 +#define VPDSCL_EASF_V_BF3_PWL_SEG3__SCL_EASF_V_BF3_PWL_IN_SEG3_MASK 0x00000fffUL +#define VPDSCL_EASF_V_BF3_PWL_SEG3__SCL_EASF_V_BF3_PWL_BASE_SEG3_MASK 0x0007f000UL +#define VPDSCL_EASF_V_BF3_PWL_SEG3__SCL_EASF_V_BF3_PWL_SLOPE_SEG3_MASK 0xfff80000UL + +// VPDSCL_EASF_V_BF3_PWL_SEG4 +#define VPDSCL_EASF_V_BF3_PWL_SEG4__SCL_EASF_V_BF3_PWL_IN_SEG4_MASK 0x00000fffUL +#define VPDSCL_EASF_V_BF3_PWL_SEG4__SCL_EASF_V_BF3_PWL_BASE_SEG4_MASK 0x0007f000UL +#define VPDSCL_EASF_V_BF3_PWL_SEG4__SCL_EASF_V_BF3_PWL_SLOPE_SEG4_MASK 0xfff80000UL + +// VPDSCL_EASF_V_BF3_PWL_SEG5 +#define VPDSCL_EASF_V_BF3_PWL_SEG5__SCL_EASF_V_BF3_PWL_IN_SEG5_MASK 0x00000fffUL +#define VPDSCL_EASF_V_BF3_PWL_SEG5__SCL_EASF_V_BF3_PWL_BASE_SEG5_MASK 0x0007f000UL + +// VPISHARP_MODE +#define VPISHARP_MODE__ISHARP_EN_MASK 0x00000001UL +#define VPISHARP_MODE__ISHARP_NOISEDET_EN_MASK 0x00000010UL +#define VPISHARP_MODE__ISHARP_NOISEDET_MODE_MASK 0x00000060UL +#define VPISHARP_MODE__ISHARP_LBA_MODE_MASK 0x00000200UL +#define VPISHARP_MODE__ISHARP_FMT_MODE_MASK 0x00000800UL +#define VPISHARP_MODE__ISHARP_FMT_NORM_MASK 0x0ffff000UL +#define VPISHARP_MODE__ISHARP_DELTA_LUT_SELECT_CURRENT_MASK 0x10000000UL + +// VPISHARP_DELTA_CTRL +#define VPISHARP_DELTA_CTRL__ISHARP_DELTA_LUT_HOST_SELECT_MASK 0x00000001UL + +// VPISHARP_DELTA_INDEX +#define VPISHARP_DELTA_INDEX__ISHARP_DELTA_INDEX_MASK 0x0000001fUL + +// VPISHARP_DELTA_DATA +#define VPISHARP_DELTA_DATA__ISHARP_DELTA_DATA_MASK 0xffffffffUL + +// VPISHARP_NLDELTA_SOFT_CLIP +#define VPISHARP_NLDELTA_SOFT_CLIP__ISHARP_NLDELTA_SCLIP_EN_P_MASK 0x00000001UL +#define VPISHARP_NLDELTA_SOFT_CLIP__ISHARP_NLDELTA_SCLIP_PIVOT_P_MASK 0x000000feUL +#define VPISHARP_NLDELTA_SOFT_CLIP__ISHARP_NLDELTA_SCLIP_SLOPE_P_MASK 0x0000ff00UL +#define VPISHARP_NLDELTA_SOFT_CLIP__ISHARP_NLDELTA_SCLIP_EN_N_MASK 0x00010000UL +#define VPISHARP_NLDELTA_SOFT_CLIP__ISHARP_NLDELTA_SCLIP_PIVOT_N_MASK 0x00fe0000UL +#define VPISHARP_NLDELTA_SOFT_CLIP__ISHARP_NLDELTA_SCLIP_SLOPE_N_MASK 0xff000000UL + +// VPISHARP_NOISEDET_THRESHOLD +#define VPISHARP_NOISEDET_THRESHOLD__ISHARP_NOISEDET_UTHRE_MASK 0x000003ffUL +#define VPISHARP_NOISEDET_THRESHOLD__ISHARP_NOISEDET_DTHRE_MASK 0x03ff0000UL + +// VPISHARP_NOISE_GAIN_PWL +#define VPISHARP_NOISE_GAIN_PWL__ISHARP_NOISEDET_PWL_START_IN_MASK 0x0000001fUL +#define VPISHARP_NOISE_GAIN_PWL__ISHARP_NOISEDET_PWL_END_IN_MASK 0x00001f00UL +#define VPISHARP_NOISE_GAIN_PWL__ISHARP_NOISEDET_PWL_SLOPE_MASK 0x3fff0000UL + +// VPISHARP_LBA_PWL_SEG0 +#define VPISHARP_LBA_PWL_SEG0__ISHARP_LBA_PWL_IN_SEG0_MASK 0x000003ffUL +#define VPISHARP_LBA_PWL_SEG0__ISHARP_LBA_PWL_BASE_SEG0_MASK 0x0003f000UL +#define VPISHARP_LBA_PWL_SEG0__ISHARP_LBA_PWL_SLOPE_SEG0_MASK 0x1ff00000UL + +// VPISHARP_LBA_PWL_SEG1 +#define VPISHARP_LBA_PWL_SEG1__ISHARP_LBA_PWL_IN_SEG1_MASK 0x000003ffUL +#define VPISHARP_LBA_PWL_SEG1__ISHARP_LBA_PWL_BASE_SEG1_MASK 0x0003f000UL +#define VPISHARP_LBA_PWL_SEG1__ISHARP_LBA_PWL_SLOPE_SEG1_MASK 0x1ff00000UL + +// VPISHARP_LBA_PWL_SEG2 +#define VPISHARP_LBA_PWL_SEG2__ISHARP_LBA_PWL_IN_SEG2_MASK 0x000003ffUL +#define VPISHARP_LBA_PWL_SEG2__ISHARP_LBA_PWL_BASE_SEG2_MASK 0x0003f000UL +#define VPISHARP_LBA_PWL_SEG2__ISHARP_LBA_PWL_SLOPE_SEG2_MASK 0x1ff00000UL + +// VPISHARP_LBA_PWL_SEG3 +#define VPISHARP_LBA_PWL_SEG3__ISHARP_LBA_PWL_IN_SEG3_MASK 0x000003ffUL +#define VPISHARP_LBA_PWL_SEG3__ISHARP_LBA_PWL_BASE_SEG3_MASK 0x0003f000UL +#define VPISHARP_LBA_PWL_SEG3__ISHARP_LBA_PWL_SLOPE_SEG3_MASK 0x1ff00000UL + +// VPISHARP_LBA_PWL_SEG4 +#define VPISHARP_LBA_PWL_SEG4__ISHARP_LBA_PWL_IN_SEG4_MASK 0x000003ffUL +#define VPISHARP_LBA_PWL_SEG4__ISHARP_LBA_PWL_BASE_SEG4_MASK 0x0003f000UL +#define VPISHARP_LBA_PWL_SEG4__ISHARP_LBA_PWL_SLOPE_SEG4_MASK 0x1ff00000UL + +// VPISHARP_LBA_PWL_SEG5 +#define VPISHARP_LBA_PWL_SEG5__ISHARP_LBA_PWL_IN_SEG5_MASK 0x000003ffUL +#define VPISHARP_LBA_PWL_SEG5__ISHARP_LBA_PWL_BASE_SEG5_MASK 0x0003f000UL + +// VPISHARP_DELTA_LUT_MEM_PWR_CTRL +#define VPISHARP_DELTA_LUT_MEM_PWR_CTRL__ISHARP_DELTA_LUT_MEM_PWR_FORCE_MASK 0x00000003UL +#define VPISHARP_DELTA_LUT_MEM_PWR_CTRL__ISHARP_DELTA_LUT_MEM_PWR_DIS_MASK 0x00000004UL +#define VPISHARP_DELTA_LUT_MEM_PWR_CTRL__ISHARP_DELTA_LUT_MEM_PWR_STATE_MASK 0x00000030UL + +// VPCM_CONTROL +#define VPCM_CONTROL__VPCM_BYPASS_MASK 0x00000001UL +#define VPCM_CONTROL__VPCM_UPDATE_PENDING_MASK 0x00000100UL + +// VPCM_POST_CSC_CONTROL +#define VPCM_POST_CSC_CONTROL__VPCM_POST_CSC_MODE_MASK 0x00000001UL +#define VPCM_POST_CSC_CONTROL__VPCM_POST_CSC_MODE_CURRENT_MASK 0x00000004UL + +// VPCM_POST_CSC_C11_C12 +#define VPCM_POST_CSC_C11_C12__VPCM_POST_CSC_C11_MASK 0x0000ffffUL +#define VPCM_POST_CSC_C11_C12__VPCM_POST_CSC_C12_MASK 0xffff0000UL + +// VPCM_POST_CSC_C13_C14 +#define VPCM_POST_CSC_C13_C14__VPCM_POST_CSC_C13_MASK 0x0000ffffUL +#define VPCM_POST_CSC_C13_C14__VPCM_POST_CSC_C14_MASK 0xffff0000UL + +// VPCM_POST_CSC_C21_C22 +#define VPCM_POST_CSC_C21_C22__VPCM_POST_CSC_C21_MASK 0x0000ffffUL +#define VPCM_POST_CSC_C21_C22__VPCM_POST_CSC_C22_MASK 0xffff0000UL + +// VPCM_POST_CSC_C23_C24 +#define VPCM_POST_CSC_C23_C24__VPCM_POST_CSC_C23_MASK 0x0000ffffUL +#define VPCM_POST_CSC_C23_C24__VPCM_POST_CSC_C24_MASK 0xffff0000UL + +// VPCM_POST_CSC_C31_C32 +#define VPCM_POST_CSC_C31_C32__VPCM_POST_CSC_C31_MASK 0x0000ffffUL +#define VPCM_POST_CSC_C31_C32__VPCM_POST_CSC_C32_MASK 0xffff0000UL + +// VPCM_POST_CSC_C33_C34 +#define VPCM_POST_CSC_C33_C34__VPCM_POST_CSC_C33_MASK 0x0000ffffUL +#define VPCM_POST_CSC_C33_C34__VPCM_POST_CSC_C34_MASK 0xffff0000UL + +// VPCM_BIAS_CR_R +#define VPCM_BIAS_CR_R__VPCM_BIAS_CR_R_MASK 0x0000ffffUL + +// VPCM_BIAS_Y_G_CB_B +#define VPCM_BIAS_Y_G_CB_B__VPCM_BIAS_Y_G_MASK 0x0000ffffUL +#define VPCM_BIAS_Y_G_CB_B__VPCM_BIAS_CB_B_MASK 0xffff0000UL + +// VPCM_GAMCOR_CONTROL +#define VPCM_GAMCOR_CONTROL__VPCM_GAMCOR_MODE_MASK 0x00000003UL +#define VPCM_GAMCOR_CONTROL__VPCM_GAMCOR_PWL_DISABLE_MASK 0x00000008UL +#define VPCM_GAMCOR_CONTROL__VPCM_GAMCOR_MODE_CURRENT_MASK 0x00000030UL +#define VPCM_GAMCOR_CONTROL__VPCM_GAMCOR_SELECT_CURRENT_MASK 0x00000040UL + +// VPCM_GAMCOR_LUT_INDEX +#define VPCM_GAMCOR_LUT_INDEX__VPCM_GAMCOR_LUT_INDEX_MASK 0x000001ffUL + +// VPCM_GAMCOR_LUT_DATA +#define VPCM_GAMCOR_LUT_DATA__VPCM_GAMCOR_LUT_DATA_MASK 0x0003ffffUL + +// VPCM_GAMCOR_LUT_CONTROL +#define VPCM_GAMCOR_LUT_CONTROL__VPCM_GAMCOR_LUT_WRITE_COLOR_MASK_MASK 0x00000007UL +#define VPCM_GAMCOR_LUT_CONTROL__VPCM_GAMCOR_LUT_READ_COLOR_SEL_MASK 0x00000018UL +#define VPCM_GAMCOR_LUT_CONTROL__VPCM_GAMCOR_LUT_READ_DBG_MASK 0x00000020UL +#define VPCM_GAMCOR_LUT_CONTROL__VPCM_GAMCOR_LUT_HOST_SEL_MASK 0x00000040UL +#define VPCM_GAMCOR_LUT_CONTROL__VPCM_GAMCOR_LUT_CONFIG_MODE_MASK 0x00000080UL + +// VPCM_GAMCOR_RAMA_START_CNTL_B +#define VPCM_GAMCOR_RAMA_START_CNTL_B__VPCM_GAMCOR_RAMA_EXP_REGION_START_B_MASK 0x0003ffffUL +#define VPCM_GAMCOR_RAMA_START_CNTL_B__VPCM_GAMCOR_RAMA_EXP_REGION_START_SEGMENT_B_MASK 0x07f00000UL + +// VPCM_GAMCOR_RAMA_START_CNTL_G +#define VPCM_GAMCOR_RAMA_START_CNTL_G__VPCM_GAMCOR_RAMA_EXP_REGION_START_G_MASK 0x0003ffffUL +#define VPCM_GAMCOR_RAMA_START_CNTL_G__VPCM_GAMCOR_RAMA_EXP_REGION_START_SEGMENT_G_MASK 0x07f00000UL + +// VPCM_GAMCOR_RAMA_START_CNTL_R +#define VPCM_GAMCOR_RAMA_START_CNTL_R__VPCM_GAMCOR_RAMA_EXP_REGION_START_R_MASK 0x0003ffffUL +#define VPCM_GAMCOR_RAMA_START_CNTL_R__VPCM_GAMCOR_RAMA_EXP_REGION_START_SEGMENT_R_MASK 0x07f00000UL + +// VPCM_GAMCOR_RAMA_START_SLOPE_CNTL_B +#define VPCM_GAMCOR_RAMA_START_SLOPE_CNTL_B__VPCM_GAMCOR_RAMA_EXP_REGION_START_SLOPE_B_MASK 0x0003ffffUL + +// VPCM_GAMCOR_RAMA_START_SLOPE_CNTL_G +#define VPCM_GAMCOR_RAMA_START_SLOPE_CNTL_G__VPCM_GAMCOR_RAMA_EXP_REGION_START_SLOPE_G_MASK 0x0003ffffUL + +// VPCM_GAMCOR_RAMA_START_SLOPE_CNTL_R +#define VPCM_GAMCOR_RAMA_START_SLOPE_CNTL_R__VPCM_GAMCOR_RAMA_EXP_REGION_START_SLOPE_R_MASK 0x0003ffffUL + +// VPCM_GAMCOR_RAMA_START_BASE_CNTL_B +#define VPCM_GAMCOR_RAMA_START_BASE_CNTL_B__VPCM_GAMCOR_RAMA_EXP_REGION_START_BASE_B_MASK 0x0003ffffUL + +// VPCM_GAMCOR_RAMA_START_BASE_CNTL_G +#define VPCM_GAMCOR_RAMA_START_BASE_CNTL_G__VPCM_GAMCOR_RAMA_EXP_REGION_START_BASE_G_MASK 0x0003ffffUL + +// VPCM_GAMCOR_RAMA_START_BASE_CNTL_R +#define VPCM_GAMCOR_RAMA_START_BASE_CNTL_R__VPCM_GAMCOR_RAMA_EXP_REGION_START_BASE_R_MASK 0x0003ffffUL + +// VPCM_GAMCOR_RAMA_END_CNTL1_B +#define VPCM_GAMCOR_RAMA_END_CNTL1_B__VPCM_GAMCOR_RAMA_EXP_REGION_END_BASE_B_MASK 0x0003ffffUL + +// VPCM_GAMCOR_RAMA_END_CNTL2_B +#define VPCM_GAMCOR_RAMA_END_CNTL2_B__VPCM_GAMCOR_RAMA_EXP_REGION_END_B_MASK 0x0000ffffUL +#define VPCM_GAMCOR_RAMA_END_CNTL2_B__VPCM_GAMCOR_RAMA_EXP_REGION_END_SLOPE_B_MASK 0xffff0000UL + +// VPCM_GAMCOR_RAMA_END_CNTL1_G +#define VPCM_GAMCOR_RAMA_END_CNTL1_G__VPCM_GAMCOR_RAMA_EXP_REGION_END_BASE_G_MASK 0x0003ffffUL + +// VPCM_GAMCOR_RAMA_END_CNTL2_G +#define VPCM_GAMCOR_RAMA_END_CNTL2_G__VPCM_GAMCOR_RAMA_EXP_REGION_END_G_MASK 0x0000ffffUL +#define VPCM_GAMCOR_RAMA_END_CNTL2_G__VPCM_GAMCOR_RAMA_EXP_REGION_END_SLOPE_G_MASK 0xffff0000UL + +// VPCM_GAMCOR_RAMA_END_CNTL1_R +#define VPCM_GAMCOR_RAMA_END_CNTL1_R__VPCM_GAMCOR_RAMA_EXP_REGION_END_BASE_R_MASK 0x0003ffffUL + +// VPCM_GAMCOR_RAMA_END_CNTL2_R +#define VPCM_GAMCOR_RAMA_END_CNTL2_R__VPCM_GAMCOR_RAMA_EXP_REGION_END_R_MASK 0x0000ffffUL +#define VPCM_GAMCOR_RAMA_END_CNTL2_R__VPCM_GAMCOR_RAMA_EXP_REGION_END_SLOPE_R_MASK 0xffff0000UL + +// VPCM_GAMCOR_RAMA_OFFSET_B +#define VPCM_GAMCOR_RAMA_OFFSET_B__VPCM_GAMCOR_RAMA_OFFSET_B_MASK 0x0007ffffUL + +// VPCM_GAMCOR_RAMA_OFFSET_G +#define VPCM_GAMCOR_RAMA_OFFSET_G__VPCM_GAMCOR_RAMA_OFFSET_G_MASK 0x0007ffffUL + +// VPCM_GAMCOR_RAMA_OFFSET_R +#define VPCM_GAMCOR_RAMA_OFFSET_R__VPCM_GAMCOR_RAMA_OFFSET_R_MASK 0x0007ffffUL + +// VPCM_GAMCOR_RAMA_REGION_0_1 +#define VPCM_GAMCOR_RAMA_REGION_0_1__VPCM_GAMCOR_RAMA_EXP_REGION0_LUT_OFFSET_MASK 0x000001ffUL +#define VPCM_GAMCOR_RAMA_REGION_0_1__VPCM_GAMCOR_RAMA_EXP_REGION0_NUM_SEGMENTS_MASK 0x00007000UL +#define VPCM_GAMCOR_RAMA_REGION_0_1__VPCM_GAMCOR_RAMA_EXP_REGION1_LUT_OFFSET_MASK 0x01ff0000UL +#define VPCM_GAMCOR_RAMA_REGION_0_1__VPCM_GAMCOR_RAMA_EXP_REGION1_NUM_SEGMENTS_MASK 0x70000000UL + +// VPCM_GAMCOR_RAMA_REGION_2_3 +#define VPCM_GAMCOR_RAMA_REGION_2_3__VPCM_GAMCOR_RAMA_EXP_REGION2_LUT_OFFSET_MASK 0x000001ffUL +#define VPCM_GAMCOR_RAMA_REGION_2_3__VPCM_GAMCOR_RAMA_EXP_REGION2_NUM_SEGMENTS_MASK 0x00007000UL +#define VPCM_GAMCOR_RAMA_REGION_2_3__VPCM_GAMCOR_RAMA_EXP_REGION3_LUT_OFFSET_MASK 0x01ff0000UL +#define VPCM_GAMCOR_RAMA_REGION_2_3__VPCM_GAMCOR_RAMA_EXP_REGION3_NUM_SEGMENTS_MASK 0x70000000UL + +// VPCM_GAMCOR_RAMA_REGION_4_5 +#define VPCM_GAMCOR_RAMA_REGION_4_5__VPCM_GAMCOR_RAMA_EXP_REGION4_LUT_OFFSET_MASK 0x000001ffUL +#define VPCM_GAMCOR_RAMA_REGION_4_5__VPCM_GAMCOR_RAMA_EXP_REGION4_NUM_SEGMENTS_MASK 0x00007000UL +#define VPCM_GAMCOR_RAMA_REGION_4_5__VPCM_GAMCOR_RAMA_EXP_REGION5_LUT_OFFSET_MASK 0x01ff0000UL +#define VPCM_GAMCOR_RAMA_REGION_4_5__VPCM_GAMCOR_RAMA_EXP_REGION5_NUM_SEGMENTS_MASK 0x70000000UL + +// VPCM_GAMCOR_RAMA_REGION_6_7 +#define VPCM_GAMCOR_RAMA_REGION_6_7__VPCM_GAMCOR_RAMA_EXP_REGION6_LUT_OFFSET_MASK 0x000001ffUL +#define VPCM_GAMCOR_RAMA_REGION_6_7__VPCM_GAMCOR_RAMA_EXP_REGION6_NUM_SEGMENTS_MASK 0x00007000UL +#define VPCM_GAMCOR_RAMA_REGION_6_7__VPCM_GAMCOR_RAMA_EXP_REGION7_LUT_OFFSET_MASK 0x01ff0000UL +#define VPCM_GAMCOR_RAMA_REGION_6_7__VPCM_GAMCOR_RAMA_EXP_REGION7_NUM_SEGMENTS_MASK 0x70000000UL + +// VPCM_GAMCOR_RAMA_REGION_8_9 +#define VPCM_GAMCOR_RAMA_REGION_8_9__VPCM_GAMCOR_RAMA_EXP_REGION8_LUT_OFFSET_MASK 0x000001ffUL +#define VPCM_GAMCOR_RAMA_REGION_8_9__VPCM_GAMCOR_RAMA_EXP_REGION8_NUM_SEGMENTS_MASK 0x00007000UL +#define VPCM_GAMCOR_RAMA_REGION_8_9__VPCM_GAMCOR_RAMA_EXP_REGION9_LUT_OFFSET_MASK 0x01ff0000UL +#define VPCM_GAMCOR_RAMA_REGION_8_9__VPCM_GAMCOR_RAMA_EXP_REGION9_NUM_SEGMENTS_MASK 0x70000000UL + +// VPCM_GAMCOR_RAMA_REGION_10_11 +#define VPCM_GAMCOR_RAMA_REGION_10_11__VPCM_GAMCOR_RAMA_EXP_REGION10_LUT_OFFSET_MASK 0x000001ffUL +#define VPCM_GAMCOR_RAMA_REGION_10_11__VPCM_GAMCOR_RAMA_EXP_REGION10_NUM_SEGMENTS_MASK 0x00007000UL +#define VPCM_GAMCOR_RAMA_REGION_10_11__VPCM_GAMCOR_RAMA_EXP_REGION11_LUT_OFFSET_MASK 0x01ff0000UL +#define VPCM_GAMCOR_RAMA_REGION_10_11__VPCM_GAMCOR_RAMA_EXP_REGION11_NUM_SEGMENTS_MASK 0x70000000UL + +// VPCM_GAMCOR_RAMA_REGION_12_13 +#define VPCM_GAMCOR_RAMA_REGION_12_13__VPCM_GAMCOR_RAMA_EXP_REGION12_LUT_OFFSET_MASK 0x000001ffUL +#define VPCM_GAMCOR_RAMA_REGION_12_13__VPCM_GAMCOR_RAMA_EXP_REGION12_NUM_SEGMENTS_MASK 0x00007000UL +#define VPCM_GAMCOR_RAMA_REGION_12_13__VPCM_GAMCOR_RAMA_EXP_REGION13_LUT_OFFSET_MASK 0x01ff0000UL +#define VPCM_GAMCOR_RAMA_REGION_12_13__VPCM_GAMCOR_RAMA_EXP_REGION13_NUM_SEGMENTS_MASK 0x70000000UL + +// VPCM_GAMCOR_RAMA_REGION_14_15 +#define VPCM_GAMCOR_RAMA_REGION_14_15__VPCM_GAMCOR_RAMA_EXP_REGION14_LUT_OFFSET_MASK 0x000001ffUL +#define VPCM_GAMCOR_RAMA_REGION_14_15__VPCM_GAMCOR_RAMA_EXP_REGION14_NUM_SEGMENTS_MASK 0x00007000UL +#define VPCM_GAMCOR_RAMA_REGION_14_15__VPCM_GAMCOR_RAMA_EXP_REGION15_LUT_OFFSET_MASK 0x01ff0000UL +#define VPCM_GAMCOR_RAMA_REGION_14_15__VPCM_GAMCOR_RAMA_EXP_REGION15_NUM_SEGMENTS_MASK 0x70000000UL + +// VPCM_GAMCOR_RAMA_REGION_16_17 +#define VPCM_GAMCOR_RAMA_REGION_16_17__VPCM_GAMCOR_RAMA_EXP_REGION16_LUT_OFFSET_MASK 0x000001ffUL +#define VPCM_GAMCOR_RAMA_REGION_16_17__VPCM_GAMCOR_RAMA_EXP_REGION16_NUM_SEGMENTS_MASK 0x00007000UL +#define VPCM_GAMCOR_RAMA_REGION_16_17__VPCM_GAMCOR_RAMA_EXP_REGION17_LUT_OFFSET_MASK 0x01ff0000UL +#define VPCM_GAMCOR_RAMA_REGION_16_17__VPCM_GAMCOR_RAMA_EXP_REGION17_NUM_SEGMENTS_MASK 0x70000000UL + +// VPCM_GAMCOR_RAMA_REGION_18_19 +#define VPCM_GAMCOR_RAMA_REGION_18_19__VPCM_GAMCOR_RAMA_EXP_REGION18_LUT_OFFSET_MASK 0x000001ffUL +#define VPCM_GAMCOR_RAMA_REGION_18_19__VPCM_GAMCOR_RAMA_EXP_REGION18_NUM_SEGMENTS_MASK 0x00007000UL +#define VPCM_GAMCOR_RAMA_REGION_18_19__VPCM_GAMCOR_RAMA_EXP_REGION19_LUT_OFFSET_MASK 0x01ff0000UL +#define VPCM_GAMCOR_RAMA_REGION_18_19__VPCM_GAMCOR_RAMA_EXP_REGION19_NUM_SEGMENTS_MASK 0x70000000UL + +// VPCM_GAMCOR_RAMA_REGION_20_21 +#define VPCM_GAMCOR_RAMA_REGION_20_21__VPCM_GAMCOR_RAMA_EXP_REGION20_LUT_OFFSET_MASK 0x000001ffUL +#define VPCM_GAMCOR_RAMA_REGION_20_21__VPCM_GAMCOR_RAMA_EXP_REGION20_NUM_SEGMENTS_MASK 0x00007000UL +#define VPCM_GAMCOR_RAMA_REGION_20_21__VPCM_GAMCOR_RAMA_EXP_REGION21_LUT_OFFSET_MASK 0x01ff0000UL +#define VPCM_GAMCOR_RAMA_REGION_20_21__VPCM_GAMCOR_RAMA_EXP_REGION21_NUM_SEGMENTS_MASK 0x70000000UL + +// VPCM_GAMCOR_RAMA_REGION_22_23 +#define VPCM_GAMCOR_RAMA_REGION_22_23__VPCM_GAMCOR_RAMA_EXP_REGION22_LUT_OFFSET_MASK 0x000001ffUL +#define VPCM_GAMCOR_RAMA_REGION_22_23__VPCM_GAMCOR_RAMA_EXP_REGION22_NUM_SEGMENTS_MASK 0x00007000UL +#define VPCM_GAMCOR_RAMA_REGION_22_23__VPCM_GAMCOR_RAMA_EXP_REGION23_LUT_OFFSET_MASK 0x01ff0000UL +#define VPCM_GAMCOR_RAMA_REGION_22_23__VPCM_GAMCOR_RAMA_EXP_REGION23_NUM_SEGMENTS_MASK 0x70000000UL + +// VPCM_GAMCOR_RAMA_REGION_24_25 +#define VPCM_GAMCOR_RAMA_REGION_24_25__VPCM_GAMCOR_RAMA_EXP_REGION24_LUT_OFFSET_MASK 0x000001ffUL +#define VPCM_GAMCOR_RAMA_REGION_24_25__VPCM_GAMCOR_RAMA_EXP_REGION24_NUM_SEGMENTS_MASK 0x00007000UL +#define VPCM_GAMCOR_RAMA_REGION_24_25__VPCM_GAMCOR_RAMA_EXP_REGION25_LUT_OFFSET_MASK 0x01ff0000UL +#define VPCM_GAMCOR_RAMA_REGION_24_25__VPCM_GAMCOR_RAMA_EXP_REGION25_NUM_SEGMENTS_MASK 0x70000000UL + +// VPCM_GAMCOR_RAMA_REGION_26_27 +#define VPCM_GAMCOR_RAMA_REGION_26_27__VPCM_GAMCOR_RAMA_EXP_REGION26_LUT_OFFSET_MASK 0x000001ffUL +#define VPCM_GAMCOR_RAMA_REGION_26_27__VPCM_GAMCOR_RAMA_EXP_REGION26_NUM_SEGMENTS_MASK 0x00007000UL +#define VPCM_GAMCOR_RAMA_REGION_26_27__VPCM_GAMCOR_RAMA_EXP_REGION27_LUT_OFFSET_MASK 0x01ff0000UL +#define VPCM_GAMCOR_RAMA_REGION_26_27__VPCM_GAMCOR_RAMA_EXP_REGION27_NUM_SEGMENTS_MASK 0x70000000UL + +// VPCM_GAMCOR_RAMA_REGION_28_29 +#define VPCM_GAMCOR_RAMA_REGION_28_29__VPCM_GAMCOR_RAMA_EXP_REGION28_LUT_OFFSET_MASK 0x000001ffUL +#define VPCM_GAMCOR_RAMA_REGION_28_29__VPCM_GAMCOR_RAMA_EXP_REGION28_NUM_SEGMENTS_MASK 0x00007000UL +#define VPCM_GAMCOR_RAMA_REGION_28_29__VPCM_GAMCOR_RAMA_EXP_REGION29_LUT_OFFSET_MASK 0x01ff0000UL +#define VPCM_GAMCOR_RAMA_REGION_28_29__VPCM_GAMCOR_RAMA_EXP_REGION29_NUM_SEGMENTS_MASK 0x70000000UL + +// VPCM_GAMCOR_RAMA_REGION_30_31 +#define VPCM_GAMCOR_RAMA_REGION_30_31__VPCM_GAMCOR_RAMA_EXP_REGION30_LUT_OFFSET_MASK 0x000001ffUL +#define VPCM_GAMCOR_RAMA_REGION_30_31__VPCM_GAMCOR_RAMA_EXP_REGION30_NUM_SEGMENTS_MASK 0x00007000UL +#define VPCM_GAMCOR_RAMA_REGION_30_31__VPCM_GAMCOR_RAMA_EXP_REGION31_LUT_OFFSET_MASK 0x01ff0000UL +#define VPCM_GAMCOR_RAMA_REGION_30_31__VPCM_GAMCOR_RAMA_EXP_REGION31_NUM_SEGMENTS_MASK 0x70000000UL + +// VPCM_GAMCOR_RAMA_REGION_32_33 +#define VPCM_GAMCOR_RAMA_REGION_32_33__VPCM_GAMCOR_RAMA_EXP_REGION32_LUT_OFFSET_MASK 0x000001ffUL +#define VPCM_GAMCOR_RAMA_REGION_32_33__VPCM_GAMCOR_RAMA_EXP_REGION32_NUM_SEGMENTS_MASK 0x00007000UL +#define VPCM_GAMCOR_RAMA_REGION_32_33__VPCM_GAMCOR_RAMA_EXP_REGION33_LUT_OFFSET_MASK 0x01ff0000UL +#define VPCM_GAMCOR_RAMA_REGION_32_33__VPCM_GAMCOR_RAMA_EXP_REGION33_NUM_SEGMENTS_MASK 0x70000000UL + +// VPCM_HDR_MULT_COEF +#define VPCM_HDR_MULT_COEF__VPCM_HDR_MULT_COEF_MASK 0x0007ffffUL + +// VPCM_MEM_PWR_CTRL +#define VPCM_MEM_PWR_CTRL__GAMCOR_MEM_PWR_FORCE_MASK 0x00000003UL +#define VPCM_MEM_PWR_CTRL__GAMCOR_MEM_PWR_DIS_MASK 0x00000004UL + +// VPCM_MEM_PWR_STATUS +#define VPCM_MEM_PWR_STATUS__GAMCOR_MEM_PWR_STATE_MASK 0x00000003UL + +// VPCM_DEALPHA +#define VPCM_DEALPHA__VPCM_DEALPHA_EN_MASK 0x00000001UL +#define VPCM_DEALPHA__VPCM_DEALPHA_ABLND_MASK 0x00000002UL + +// VPCM_COEF_FORMAT +#define VPCM_COEF_FORMAT__VPCM_BIAS_FORMAT_MASK 0x00000001UL +#define VPCM_COEF_FORMAT__VPCM_POST_CSC_COEF_FORMAT_MASK 0x00000010UL + +// VPCM_HIST_CNTL +#define VPCM_HIST_CNTL__VPCM_HIST_SEL_MASK 0x00000003UL +#define VPCM_HIST_CNTL__VPCM_HIST_CH_EN_MASK 0x0000000cUL +#define VPCM_HIST_CNTL__VPCM_HIST_SRC1_SEL_MASK 0x00000010UL +#define VPCM_HIST_CNTL__VPCM_HIST_SRC2_SEL_MASK 0x00000020UL +#define VPCM_HIST_CNTL__VPCM_HIST_SRC3_SEL_MASK 0x00000040UL +#define VPCM_HIST_CNTL__VPCM_HIST_CH1_XBAR_MASK 0x00000180UL +#define VPCM_HIST_CNTL__VPCM_HIST_CH2_XBAR_MASK 0x00000600UL +#define VPCM_HIST_CNTL__VPCM_HIST_CH3_XBAR_MASK 0x00001800UL +#define VPCM_HIST_CNTL__VPCM_HIST_FORMAT_MASK 0x00006000UL +#define VPCM_HIST_CNTL__VPCM_HIST_READ_CHANNEL_MASK_MASK 0x00038000UL + +// VPCM_HIST_SCALE_SRC1 +#define VPCM_HIST_SCALE_SRC1__VPCM_HIST_SCALE_SRC1_MASK 0x0007ffffUL + +// VPCM_HIST_COEFA_SRC2 +#define VPCM_HIST_COEFA_SRC2__VPCM_HIST_COEFA_SRC2_MASK 0x0007ffffUL + +// VPCM_HIST_COEFB_SRC2 +#define VPCM_HIST_COEFB_SRC2__VPCM_HIST_COEFB_SRC2_MASK 0x0007ffffUL + +// VPCM_HIST_COEFC_SRC2 +#define VPCM_HIST_COEFC_SRC2__VPCM_HIST_COEFC_SRC2_MASK 0x0007ffffUL + +// VPCM_HIST_SCALE_SRC3 +#define VPCM_HIST_SCALE_SRC3__VPCM_HIST_SCALE_SRC3_MASK 0x0007ffffUL + +// VPCM_HIST_BIAS_SRC1 +#define VPCM_HIST_BIAS_SRC1__VPCM_HIST_BIAS_SRC1_MASK 0x0007ffffUL + +// VPCM_HIST_BIAS_SRC2 +#define VPCM_HIST_BIAS_SRC2__VPCM_HIST_BIAS_SRC2_MASK 0x0007ffffUL + +// VPCM_HIST_BIAS_SRC3 +#define VPCM_HIST_BIAS_SRC3__VPCM_HIST_BIAS_SRC3_MASK 0x0007ffffUL + +// VPDPP_CONTROL +#define VPDPP_CONTROL__VPECLK_G_GATE_DISABLE_MASK 0x00000100UL +#define VPDPP_CONTROL__VPECLK_G_VPDSCL_GATE_DISABLE_MASK 0x00001000UL +#define VPDPP_CONTROL__VPDPP_FGCG_REP_DIS_MASK 0x01000000UL + +// VPDPP_CRC_CTRL +#define VPDPP_CRC_CTRL__VPDPP_CRC_EN_MASK 0x00000001UL +#define VPDPP_CRC_CTRL__VPDPP_CRC_CONT_EN_MASK 0x00000002UL +#define VPDPP_CRC_CTRL__VPDPP_CRC_420_COMP_SEL_MASK 0x00000008UL +#define VPDPP_CRC_CTRL__VPDPP_CRC_SRC_SEL_MASK 0x00000030UL +#define VPDPP_CRC_CTRL__VPDPP_CRC_PIX_FORMAT_SEL_MASK 0x00003800UL +#define VPDPP_CRC_CTRL__VPDPP_CRC_MASK_MASK 0xffff0000UL + +// VPMPC_CLOCK_CONTROL +#define VPMPC_CLOCK_CONTROL__VPECLK_R_GATE_DISABLE_MASK 0x00000002UL + +// VPMPC_SOFT_RESET +#define VPMPC_SOFT_RESET__VPMPCC0_SOFT_RESET_MASK 0x00000001UL +#define VPMPC_SOFT_RESET__VPMPC_SFR0_SOFT_RESET_MASK 0x00000400UL +#define VPMPC_SOFT_RESET__VPMPC_SFT0_SOFT_RESET_MASK 0x00100000UL +#define VPMPC_SOFT_RESET__VPMPC_SOFT_RESET_MASK 0x80000000UL + +// VPMPC_CRC_CTRL +#define VPMPC_CRC_CTRL__VPMPC_CRC_EN_MASK 0x00000001UL +#define VPMPC_CRC_CTRL__VPMPC_CRC_CONT_EN_MASK 0x00000010UL +#define VPMPC_CRC_CTRL__VPMPC_CRC_SRC_SEL_MASK 0x03000000UL +#define VPMPC_CRC_CTRL__VPMPC_CRC_ONE_SHOT_PENDING_MASK 0x10000000UL +#define VPMPC_CRC_CTRL__VPMPC_CRC_UPDATE_ENABLED_MASK 0x40000000UL +#define VPMPC_CRC_CTRL__VPMPC_CRC_UPDATE_LOCK_MASK 0x80000000UL + +// VPMPC_CRC_SEL_CONTROL +#define VPMPC_CRC_SEL_CONTROL__VPMPC_CRC_VPDPP_SEL_MASK 0x0000000fUL +#define VPMPC_CRC_SEL_CONTROL__VPMPC_CRC_VPOPP_SEL_MASK 0x000000f0UL +#define VPMPC_CRC_SEL_CONTROL__VPMPC_CRC_MASK_MASK 0xffff0000UL + +// VPMPC_CRC_RESULT_AR +#define VPMPC_CRC_RESULT_AR__VPMPC_CRC_RESULT_A_MASK 0x0000ffffUL +#define VPMPC_CRC_RESULT_AR__VPMPC_CRC_RESULT_R_MASK 0xffff0000UL + +// VPMPC_CRC_RESULT_GB +#define VPMPC_CRC_RESULT_GB__VPMPC_CRC_RESULT_G_MASK 0x0000ffffUL +#define VPMPC_CRC_RESULT_GB__VPMPC_CRC_RESULT_B_MASK 0xffff0000UL + +// VPMPC_CRC_RESULT_C +#define VPMPC_CRC_RESULT_C__VPMPC_CRC_RESULT_C_MASK 0x0000ffffUL + +// VPMPC_BYPASS_BG_AR +#define VPMPC_BYPASS_BG_AR__VPMPC_BYPASS_BG_ALPHA_MASK 0x0000ffffUL +#define VPMPC_BYPASS_BG_AR__VPMPC_BYPASS_BG_R_CR_MASK 0xffff0000UL + +// VPMPC_BYPASS_BG_GB +#define VPMPC_BYPASS_BG_GB__VPMPC_BYPASS_BG_G_Y_MASK 0x0000ffffUL +#define VPMPC_BYPASS_BG_GB__VPMPC_BYPASS_BG_B_CB_MASK 0xffff0000UL + +// VPMPC_HOST_READ_CONTROL +#define VPMPC_HOST_READ_CONTROL__HOST_READ_RATE_CONTROL_MASK 0x000000ffUL + +// VPMPC_PENDING_STATUS_MISC +#define VPMPC_PENDING_STATUS_MISC__VPMPCC0_CONFIG_UPDATE_PENDING_MASK 0x00000100UL + +// VPMPC_VPCDC0_3DLUT_FL_CONFIG +#define VPMPC_VPCDC0_3DLUT_FL_CONFIG__VPCDC0_3DLUT_FL_MODE_MASK 0x00000003UL +#define VPMPC_VPCDC0_3DLUT_FL_CONFIG__VPCDC0_3DLUT_FL_FORMAT_MASK 0x00000030UL + +// VPMPC_VPCDC0_3DLUT_FL_BIAS_SCALE +#define VPMPC_VPCDC0_3DLUT_FL_BIAS_SCALE__VPCDC0_3DLUT_FL_BIAS_MASK 0x0000ffffUL +#define VPMPC_VPCDC0_3DLUT_FL_BIAS_SCALE__VPCDC0_3DLUT_FL_SCALE_MASK 0xffff0000UL + +// VPMPC_OUT0_MUX +#define VPMPC_OUT0_MUX__VPMPC_OUT_MUX_MASK 0x0000000fUL + +// VPMPC_OUT0_FLOAT_CONTROL +#define VPMPC_OUT0_FLOAT_CONTROL__VPMPC_OUT_FLOAT_EN_MASK 0x00000001UL + +// VPMPC_OUT0_DENORM_CONTROL +#define VPMPC_OUT0_DENORM_CONTROL__VPMPC_OUT_DENORM_CLAMP_MIN_R_CR_MASK 0x00000fffUL +#define VPMPC_OUT0_DENORM_CONTROL__VPMPC_OUT_DENORM_CLAMP_MAX_R_CR_MASK 0x00fff000UL +#define VPMPC_OUT0_DENORM_CONTROL__VPMPC_OUT_DENORM_MODE_MASK 0x07000000UL + +// VPMPC_OUT0_DENORM_CLAMP_G_Y +#define VPMPC_OUT0_DENORM_CLAMP_G_Y__VPMPC_OUT_DENORM_CLAMP_MIN_G_Y_MASK 0x00000fffUL +#define VPMPC_OUT0_DENORM_CLAMP_G_Y__VPMPC_OUT_DENORM_CLAMP_MAX_G_Y_MASK 0x00fff000UL + +// VPMPC_OUT0_DENORM_CLAMP_B_CB +#define VPMPC_OUT0_DENORM_CLAMP_B_CB__VPMPC_OUT_DENORM_CLAMP_MIN_B_CB_MASK 0x00000fffUL +#define VPMPC_OUT0_DENORM_CLAMP_B_CB__VPMPC_OUT_DENORM_CLAMP_MAX_B_CB_MASK 0x00fff000UL + +// VPMPC_OUT_CSC_COEF_FORMAT +#define VPMPC_OUT_CSC_COEF_FORMAT__VPMPC_OCSC0_COEF_FORMAT_MASK 0x00000001UL + +// VPMPC_OUT0_CSC_MODE +#define VPMPC_OUT0_CSC_MODE__VPMPC_OCSC_MODE_MASK 0x00000001UL +#define VPMPC_OUT0_CSC_MODE__VPMPC_OCSC_MODE_CURRENT_MASK 0x00000080UL + +// VPMPC_OUT0_CSC_C11_C12_A +#define VPMPC_OUT0_CSC_C11_C12_A__VPMPC_OCSC_C11_A_MASK 0x0000ffffUL +#define VPMPC_OUT0_CSC_C11_C12_A__VPMPC_OCSC_C12_A_MASK 0xffff0000UL + +// VPMPC_OUT0_CSC_C13_C14_A +#define VPMPC_OUT0_CSC_C13_C14_A__VPMPC_OCSC_C13_A_MASK 0x0000ffffUL +#define VPMPC_OUT0_CSC_C13_C14_A__VPMPC_OCSC_C14_A_MASK 0xffff0000UL + +// VPMPC_OUT0_CSC_C21_C22_A +#define VPMPC_OUT0_CSC_C21_C22_A__VPMPC_OCSC_C21_A_MASK 0x0000ffffUL +#define VPMPC_OUT0_CSC_C21_C22_A__VPMPC_OCSC_C22_A_MASK 0xffff0000UL + +// VPMPC_OUT0_CSC_C23_C24_A +#define VPMPC_OUT0_CSC_C23_C24_A__VPMPC_OCSC_C23_A_MASK 0x0000ffffUL +#define VPMPC_OUT0_CSC_C23_C24_A__VPMPC_OCSC_C24_A_MASK 0xffff0000UL + +// VPMPC_OUT0_CSC_C31_C32_A +#define VPMPC_OUT0_CSC_C31_C32_A__VPMPC_OCSC_C31_A_MASK 0x0000ffffUL +#define VPMPC_OUT0_CSC_C31_C32_A__VPMPC_OCSC_C32_A_MASK 0xffff0000UL + +// VPMPC_OUT0_CSC_C33_C34_A +#define VPMPC_OUT0_CSC_C33_C34_A__VPMPC_OCSC_C33_A_MASK 0x0000ffffUL +#define VPMPC_OUT0_CSC_C33_C34_A__VPMPC_OCSC_C34_A_MASK 0xffff0000UL + +// VPMPCC_TOP_SEL +#define VPMPCC_TOP_SEL__VPMPCC_TOP_SEL_MASK 0x0000000fUL + +// VPMPCC_BOT_SEL +#define VPMPCC_BOT_SEL__VPMPCC_BOT_SEL_MASK 0x0000000fUL + +// VPMPCC_VPOPP_ID +#define VPMPCC_VPOPP_ID__VPMPCC_VPOPP_ID_MASK 0x0000000fUL + +// VPMPCC_CONTROL +#define VPMPCC_CONTROL__VPMPCC_MODE_MASK 0x00000003UL +#define VPMPCC_CONTROL__VPMPCC_ALPHA_BLND_MODE_MASK 0x00000030UL +#define VPMPCC_CONTROL__VPMPCC_ALPHA_MULTIPLIED_MODE_MASK 0x00000040UL +#define VPMPCC_CONTROL__VPMPCC_BLND_ACTIVE_OVERLAP_ONLY_MASK 0x00000080UL +#define VPMPCC_CONTROL__VPMPCC_BOT_GAIN_MODE_MASK 0x00000800UL + +// VPMPCC_CONTROL2 +#define VPMPCC_CONTROL2__VPMPCC_GLOBAL_ALPHA_MASK 0x00000fffUL +#define VPMPCC_CONTROL2__VPMPCC_GLOBAL_GAIN_MASK 0x0fff0000UL + +// VPMPCC_TOP_GAIN +#define VPMPCC_TOP_GAIN__VPMPCC_TOP_GAIN_MASK 0x0007ffffUL + +// VPMPCC_BOT_GAIN_INSIDE +#define VPMPCC_BOT_GAIN_INSIDE__VPMPCC_BOT_GAIN_INSIDE_MASK 0x0007ffffUL + +// VPMPCC_BOT_GAIN_OUTSIDE +#define VPMPCC_BOT_GAIN_OUTSIDE__VPMPCC_BOT_GAIN_OUTSIDE_MASK 0x0007ffffUL + +// VPMPCC_MOVABLE_CM_LOCATION_CONTROL +#define VPMPCC_MOVABLE_CM_LOCATION_CONTROL__VPMPCC_MOVABLE_CM_LOCATION_CNTL_MASK 0x00000001UL +#define VPMPCC_MOVABLE_CM_LOCATION_CONTROL__VPMPCC_MOVABLE_CM_LOCATION_CNTL_CURRENT_MASK 0x00000010UL + +// VPMPCC_BG_R_CR +#define VPMPCC_BG_R_CR__VPMPCC_BG_R_CR_MASK 0x0007ffffUL + +// VPMPCC_BG_G_Y +#define VPMPCC_BG_G_Y__VPMPCC_BG_G_Y_MASK 0x0007ffffUL + +// VPMPCC_BG_B_CB +#define VPMPCC_BG_B_CB__VPMPCC_BG_B_CB_MASK 0x0007ffffUL + +// VPMPCC_MEM_PWR_CTRL +#define VPMPCC_MEM_PWR_CTRL__VPMPCC_OGAM_MEM_PWR_FORCE_MASK 0x00000003UL +#define VPMPCC_MEM_PWR_CTRL__VPMPCC_OGAM_MEM_PWR_DIS_MASK 0x00000004UL +#define VPMPCC_MEM_PWR_CTRL__VPMPCC_OGAM_MEM_LOW_PWR_MODE_MASK 0x00000030UL +#define VPMPCC_MEM_PWR_CTRL__VPMPCC_OGAM_MEM_PWR_STATE_MASK 0x00000300UL + +// VPMPCC_STATUS +#define VPMPCC_STATUS__VPMPCC_IDLE_MASK 0x00000001UL +#define VPMPCC_STATUS__VPMPCC_BUSY_MASK 0x00000002UL +#define VPMPCC_STATUS__VPMPCC_DISABLED_MASK 0x00000004UL + +// VPMPCC_OGAM_CONTROL +#define VPMPCC_OGAM_CONTROL__VPMPCC_OGAM_MODE_MASK 0x00000003UL +#define VPMPCC_OGAM_CONTROL__VPMPCC_OGAM_PWL_DISABLE_MASK 0x00000008UL +#define VPMPCC_OGAM_CONTROL__VPMPCC_OGAM_MODE_CURRENT_MASK 0x00000180UL +#define VPMPCC_OGAM_CONTROL__VPMPCC_OGAM_SELECT_CURRENT_MASK 0x00000200UL + +// VPMPCC_OGAM_LUT_INDEX +#define VPMPCC_OGAM_LUT_INDEX__VPMPCC_OGAM_LUT_INDEX_MASK 0x000001ffUL + +// VPMPCC_OGAM_LUT_DATA +#define VPMPCC_OGAM_LUT_DATA__VPMPCC_OGAM_LUT_DATA_MASK 0x0003ffffUL + +// VPMPCC_OGAM_LUT_CONTROL +#define VPMPCC_OGAM_LUT_CONTROL__VPMPCC_OGAM_LUT_WRITE_COLOR_MASK_MASK 0x00000007UL +#define VPMPCC_OGAM_LUT_CONTROL__VPMPCC_OGAM_LUT_READ_COLOR_SEL_MASK 0x00000018UL +#define VPMPCC_OGAM_LUT_CONTROL__VPMPCC_OGAM_LUT_READ_DBG_MASK 0x00000020UL +#define VPMPCC_OGAM_LUT_CONTROL__VPMPCC_OGAM_LUT_HOST_SEL_MASK 0x00000040UL +#define VPMPCC_OGAM_LUT_CONTROL__VPMPCC_OGAM_LUT_CONFIG_MODE_MASK 0x00000080UL + +// VPMPCC_OGAM_RAMA_START_CNTL_B +#define VPMPCC_OGAM_RAMA_START_CNTL_B__VPMPCC_OGAM_RAMA_EXP_REGION_START_B_MASK 0x0003ffffUL +#define VPMPCC_OGAM_RAMA_START_CNTL_B__VPMPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_B_MASK 0x07f00000UL + +// VPMPCC_OGAM_RAMA_START_CNTL_G +#define VPMPCC_OGAM_RAMA_START_CNTL_G__VPMPCC_OGAM_RAMA_EXP_REGION_START_G_MASK 0x0003ffffUL +#define VPMPCC_OGAM_RAMA_START_CNTL_G__VPMPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_G_MASK 0x07f00000UL + +// VPMPCC_OGAM_RAMA_START_CNTL_R +#define VPMPCC_OGAM_RAMA_START_CNTL_R__VPMPCC_OGAM_RAMA_EXP_REGION_START_R_MASK 0x0003ffffUL +#define VPMPCC_OGAM_RAMA_START_CNTL_R__VPMPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_R_MASK 0x07f00000UL + +// VPMPCC_OGAM_RAMA_START_SLOPE_CNTL_B +#define VPMPCC_OGAM_RAMA_START_SLOPE_CNTL_B__VPMPCC_OGAM_RAMA_EXP_REGION_START_SLOPE_B_MASK 0x0003ffffUL + +// VPMPCC_OGAM_RAMA_START_SLOPE_CNTL_G +#define VPMPCC_OGAM_RAMA_START_SLOPE_CNTL_G__VPMPCC_OGAM_RAMA_EXP_REGION_START_SLOPE_G_MASK 0x0003ffffUL + +// VPMPCC_OGAM_RAMA_START_SLOPE_CNTL_R +#define VPMPCC_OGAM_RAMA_START_SLOPE_CNTL_R__VPMPCC_OGAM_RAMA_EXP_REGION_START_SLOPE_R_MASK 0x0003ffffUL + +// VPMPCC_OGAM_RAMA_START_BASE_CNTL_B +#define VPMPCC_OGAM_RAMA_START_BASE_CNTL_B__VPMPCC_OGAM_RAMA_EXP_REGION_START_BASE_B_MASK 0x0003ffffUL + +// VPMPCC_OGAM_RAMA_START_BASE_CNTL_G +#define VPMPCC_OGAM_RAMA_START_BASE_CNTL_G__VPMPCC_OGAM_RAMA_EXP_REGION_START_BASE_G_MASK 0x0003ffffUL + +// VPMPCC_OGAM_RAMA_START_BASE_CNTL_R +#define VPMPCC_OGAM_RAMA_START_BASE_CNTL_R__VPMPCC_OGAM_RAMA_EXP_REGION_START_BASE_R_MASK 0x0003ffffUL + +// VPMPCC_OGAM_RAMA_END_CNTL1_B +#define VPMPCC_OGAM_RAMA_END_CNTL1_B__VPMPCC_OGAM_RAMA_EXP_REGION_END_BASE_B_MASK 0x0003ffffUL + +// VPMPCC_OGAM_RAMA_END_CNTL2_B +#define VPMPCC_OGAM_RAMA_END_CNTL2_B__VPMPCC_OGAM_RAMA_EXP_REGION_END_B_MASK 0x0000ffffUL +#define VPMPCC_OGAM_RAMA_END_CNTL2_B__VPMPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_B_MASK 0xffff0000UL + +// VPMPCC_OGAM_RAMA_END_CNTL1_G +#define VPMPCC_OGAM_RAMA_END_CNTL1_G__VPMPCC_OGAM_RAMA_EXP_REGION_END_BASE_G_MASK 0x0003ffffUL + +// VPMPCC_OGAM_RAMA_END_CNTL2_G +#define VPMPCC_OGAM_RAMA_END_CNTL2_G__VPMPCC_OGAM_RAMA_EXP_REGION_END_G_MASK 0x0000ffffUL +#define VPMPCC_OGAM_RAMA_END_CNTL2_G__VPMPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_G_MASK 0xffff0000UL + +// VPMPCC_OGAM_RAMA_END_CNTL1_R +#define VPMPCC_OGAM_RAMA_END_CNTL1_R__VPMPCC_OGAM_RAMA_EXP_REGION_END_BASE_R_MASK 0x0003ffffUL + +// VPMPCC_OGAM_RAMA_END_CNTL2_R +#define VPMPCC_OGAM_RAMA_END_CNTL2_R__VPMPCC_OGAM_RAMA_EXP_REGION_END_R_MASK 0x0000ffffUL +#define VPMPCC_OGAM_RAMA_END_CNTL2_R__VPMPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_R_MASK 0xffff0000UL + +// VPMPCC_OGAM_RAMA_OFFSET_B +#define VPMPCC_OGAM_RAMA_OFFSET_B__VPMPCC_OGAM_RAMA_OFFSET_B_MASK 0x0007ffffUL + +// VPMPCC_OGAM_RAMA_OFFSET_G +#define VPMPCC_OGAM_RAMA_OFFSET_G__VPMPCC_OGAM_RAMA_OFFSET_G_MASK 0x0007ffffUL + +// VPMPCC_OGAM_RAMA_OFFSET_R +#define VPMPCC_OGAM_RAMA_OFFSET_R__VPMPCC_OGAM_RAMA_OFFSET_R_MASK 0x0007ffffUL + +// VPMPCC_OGAM_RAMA_REGION_0_1 +#define VPMPCC_OGAM_RAMA_REGION_0_1__VPMPCC_OGAM_RAMA_EXP_REGION0_LUT_OFFSET_MASK 0x000001ffUL +#define VPMPCC_OGAM_RAMA_REGION_0_1__VPMPCC_OGAM_RAMA_EXP_REGION0_NUM_SEGMENTS_MASK 0x00007000UL +#define VPMPCC_OGAM_RAMA_REGION_0_1__VPMPCC_OGAM_RAMA_EXP_REGION1_LUT_OFFSET_MASK 0x01ff0000UL +#define VPMPCC_OGAM_RAMA_REGION_0_1__VPMPCC_OGAM_RAMA_EXP_REGION1_NUM_SEGMENTS_MASK 0x70000000UL + +// VPMPCC_OGAM_RAMA_REGION_2_3 +#define VPMPCC_OGAM_RAMA_REGION_2_3__VPMPCC_OGAM_RAMA_EXP_REGION2_LUT_OFFSET_MASK 0x000001ffUL +#define VPMPCC_OGAM_RAMA_REGION_2_3__VPMPCC_OGAM_RAMA_EXP_REGION2_NUM_SEGMENTS_MASK 0x00007000UL +#define VPMPCC_OGAM_RAMA_REGION_2_3__VPMPCC_OGAM_RAMA_EXP_REGION3_LUT_OFFSET_MASK 0x01ff0000UL +#define VPMPCC_OGAM_RAMA_REGION_2_3__VPMPCC_OGAM_RAMA_EXP_REGION3_NUM_SEGMENTS_MASK 0x70000000UL + +// VPMPCC_OGAM_RAMA_REGION_4_5 +#define VPMPCC_OGAM_RAMA_REGION_4_5__VPMPCC_OGAM_RAMA_EXP_REGION4_LUT_OFFSET_MASK 0x000001ffUL +#define VPMPCC_OGAM_RAMA_REGION_4_5__VPMPCC_OGAM_RAMA_EXP_REGION4_NUM_SEGMENTS_MASK 0x00007000UL +#define VPMPCC_OGAM_RAMA_REGION_4_5__VPMPCC_OGAM_RAMA_EXP_REGION5_LUT_OFFSET_MASK 0x01ff0000UL +#define VPMPCC_OGAM_RAMA_REGION_4_5__VPMPCC_OGAM_RAMA_EXP_REGION5_NUM_SEGMENTS_MASK 0x70000000UL + +// VPMPCC_OGAM_RAMA_REGION_6_7 +#define VPMPCC_OGAM_RAMA_REGION_6_7__VPMPCC_OGAM_RAMA_EXP_REGION6_LUT_OFFSET_MASK 0x000001ffUL +#define VPMPCC_OGAM_RAMA_REGION_6_7__VPMPCC_OGAM_RAMA_EXP_REGION6_NUM_SEGMENTS_MASK 0x00007000UL +#define VPMPCC_OGAM_RAMA_REGION_6_7__VPMPCC_OGAM_RAMA_EXP_REGION7_LUT_OFFSET_MASK 0x01ff0000UL +#define VPMPCC_OGAM_RAMA_REGION_6_7__VPMPCC_OGAM_RAMA_EXP_REGION7_NUM_SEGMENTS_MASK 0x70000000UL + +// VPMPCC_OGAM_RAMA_REGION_8_9 +#define VPMPCC_OGAM_RAMA_REGION_8_9__VPMPCC_OGAM_RAMA_EXP_REGION8_LUT_OFFSET_MASK 0x000001ffUL +#define VPMPCC_OGAM_RAMA_REGION_8_9__VPMPCC_OGAM_RAMA_EXP_REGION8_NUM_SEGMENTS_MASK 0x00007000UL +#define VPMPCC_OGAM_RAMA_REGION_8_9__VPMPCC_OGAM_RAMA_EXP_REGION9_LUT_OFFSET_MASK 0x01ff0000UL +#define VPMPCC_OGAM_RAMA_REGION_8_9__VPMPCC_OGAM_RAMA_EXP_REGION9_NUM_SEGMENTS_MASK 0x70000000UL + +// VPMPCC_OGAM_RAMA_REGION_10_11 +#define VPMPCC_OGAM_RAMA_REGION_10_11__VPMPCC_OGAM_RAMA_EXP_REGION10_LUT_OFFSET_MASK 0x000001ffUL +#define VPMPCC_OGAM_RAMA_REGION_10_11__VPMPCC_OGAM_RAMA_EXP_REGION10_NUM_SEGMENTS_MASK 0x00007000UL +#define VPMPCC_OGAM_RAMA_REGION_10_11__VPMPCC_OGAM_RAMA_EXP_REGION11_LUT_OFFSET_MASK 0x01ff0000UL +#define VPMPCC_OGAM_RAMA_REGION_10_11__VPMPCC_OGAM_RAMA_EXP_REGION11_NUM_SEGMENTS_MASK 0x70000000UL + +// VPMPCC_OGAM_RAMA_REGION_12_13 +#define VPMPCC_OGAM_RAMA_REGION_12_13__VPMPCC_OGAM_RAMA_EXP_REGION12_LUT_OFFSET_MASK 0x000001ffUL +#define VPMPCC_OGAM_RAMA_REGION_12_13__VPMPCC_OGAM_RAMA_EXP_REGION12_NUM_SEGMENTS_MASK 0x00007000UL +#define VPMPCC_OGAM_RAMA_REGION_12_13__VPMPCC_OGAM_RAMA_EXP_REGION13_LUT_OFFSET_MASK 0x01ff0000UL +#define VPMPCC_OGAM_RAMA_REGION_12_13__VPMPCC_OGAM_RAMA_EXP_REGION13_NUM_SEGMENTS_MASK 0x70000000UL + +// VPMPCC_OGAM_RAMA_REGION_14_15 +#define VPMPCC_OGAM_RAMA_REGION_14_15__VPMPCC_OGAM_RAMA_EXP_REGION14_LUT_OFFSET_MASK 0x000001ffUL +#define VPMPCC_OGAM_RAMA_REGION_14_15__VPMPCC_OGAM_RAMA_EXP_REGION14_NUM_SEGMENTS_MASK 0x00007000UL +#define VPMPCC_OGAM_RAMA_REGION_14_15__VPMPCC_OGAM_RAMA_EXP_REGION15_LUT_OFFSET_MASK 0x01ff0000UL +#define VPMPCC_OGAM_RAMA_REGION_14_15__VPMPCC_OGAM_RAMA_EXP_REGION15_NUM_SEGMENTS_MASK 0x70000000UL + +// VPMPCC_OGAM_RAMA_REGION_16_17 +#define VPMPCC_OGAM_RAMA_REGION_16_17__VPMPCC_OGAM_RAMA_EXP_REGION16_LUT_OFFSET_MASK 0x000001ffUL +#define VPMPCC_OGAM_RAMA_REGION_16_17__VPMPCC_OGAM_RAMA_EXP_REGION16_NUM_SEGMENTS_MASK 0x00007000UL +#define VPMPCC_OGAM_RAMA_REGION_16_17__VPMPCC_OGAM_RAMA_EXP_REGION17_LUT_OFFSET_MASK 0x01ff0000UL +#define VPMPCC_OGAM_RAMA_REGION_16_17__VPMPCC_OGAM_RAMA_EXP_REGION17_NUM_SEGMENTS_MASK 0x70000000UL + +// VPMPCC_OGAM_RAMA_REGION_18_19 +#define VPMPCC_OGAM_RAMA_REGION_18_19__VPMPCC_OGAM_RAMA_EXP_REGION18_LUT_OFFSET_MASK 0x000001ffUL +#define VPMPCC_OGAM_RAMA_REGION_18_19__VPMPCC_OGAM_RAMA_EXP_REGION18_NUM_SEGMENTS_MASK 0x00007000UL +#define VPMPCC_OGAM_RAMA_REGION_18_19__VPMPCC_OGAM_RAMA_EXP_REGION19_LUT_OFFSET_MASK 0x01ff0000UL +#define VPMPCC_OGAM_RAMA_REGION_18_19__VPMPCC_OGAM_RAMA_EXP_REGION19_NUM_SEGMENTS_MASK 0x70000000UL + +// VPMPCC_OGAM_RAMA_REGION_20_21 +#define VPMPCC_OGAM_RAMA_REGION_20_21__VPMPCC_OGAM_RAMA_EXP_REGION20_LUT_OFFSET_MASK 0x000001ffUL +#define VPMPCC_OGAM_RAMA_REGION_20_21__VPMPCC_OGAM_RAMA_EXP_REGION20_NUM_SEGMENTS_MASK 0x00007000UL +#define VPMPCC_OGAM_RAMA_REGION_20_21__VPMPCC_OGAM_RAMA_EXP_REGION21_LUT_OFFSET_MASK 0x01ff0000UL +#define VPMPCC_OGAM_RAMA_REGION_20_21__VPMPCC_OGAM_RAMA_EXP_REGION21_NUM_SEGMENTS_MASK 0x70000000UL + +// VPMPCC_OGAM_RAMA_REGION_22_23 +#define VPMPCC_OGAM_RAMA_REGION_22_23__VPMPCC_OGAM_RAMA_EXP_REGION22_LUT_OFFSET_MASK 0x000001ffUL +#define VPMPCC_OGAM_RAMA_REGION_22_23__VPMPCC_OGAM_RAMA_EXP_REGION22_NUM_SEGMENTS_MASK 0x00007000UL +#define VPMPCC_OGAM_RAMA_REGION_22_23__VPMPCC_OGAM_RAMA_EXP_REGION23_LUT_OFFSET_MASK 0x01ff0000UL +#define VPMPCC_OGAM_RAMA_REGION_22_23__VPMPCC_OGAM_RAMA_EXP_REGION23_NUM_SEGMENTS_MASK 0x70000000UL + +// VPMPCC_OGAM_RAMA_REGION_24_25 +#define VPMPCC_OGAM_RAMA_REGION_24_25__VPMPCC_OGAM_RAMA_EXP_REGION24_LUT_OFFSET_MASK 0x000001ffUL +#define VPMPCC_OGAM_RAMA_REGION_24_25__VPMPCC_OGAM_RAMA_EXP_REGION24_NUM_SEGMENTS_MASK 0x00007000UL +#define VPMPCC_OGAM_RAMA_REGION_24_25__VPMPCC_OGAM_RAMA_EXP_REGION25_LUT_OFFSET_MASK 0x01ff0000UL +#define VPMPCC_OGAM_RAMA_REGION_24_25__VPMPCC_OGAM_RAMA_EXP_REGION25_NUM_SEGMENTS_MASK 0x70000000UL + +// VPMPCC_OGAM_RAMA_REGION_26_27 +#define VPMPCC_OGAM_RAMA_REGION_26_27__VPMPCC_OGAM_RAMA_EXP_REGION26_LUT_OFFSET_MASK 0x000001ffUL +#define VPMPCC_OGAM_RAMA_REGION_26_27__VPMPCC_OGAM_RAMA_EXP_REGION26_NUM_SEGMENTS_MASK 0x00007000UL +#define VPMPCC_OGAM_RAMA_REGION_26_27__VPMPCC_OGAM_RAMA_EXP_REGION27_LUT_OFFSET_MASK 0x01ff0000UL +#define VPMPCC_OGAM_RAMA_REGION_26_27__VPMPCC_OGAM_RAMA_EXP_REGION27_NUM_SEGMENTS_MASK 0x70000000UL + +// VPMPCC_OGAM_RAMA_REGION_28_29 +#define VPMPCC_OGAM_RAMA_REGION_28_29__VPMPCC_OGAM_RAMA_EXP_REGION28_LUT_OFFSET_MASK 0x000001ffUL +#define VPMPCC_OGAM_RAMA_REGION_28_29__VPMPCC_OGAM_RAMA_EXP_REGION28_NUM_SEGMENTS_MASK 0x00007000UL +#define VPMPCC_OGAM_RAMA_REGION_28_29__VPMPCC_OGAM_RAMA_EXP_REGION29_LUT_OFFSET_MASK 0x01ff0000UL +#define VPMPCC_OGAM_RAMA_REGION_28_29__VPMPCC_OGAM_RAMA_EXP_REGION29_NUM_SEGMENTS_MASK 0x70000000UL + +// VPMPCC_OGAM_RAMA_REGION_30_31 +#define VPMPCC_OGAM_RAMA_REGION_30_31__VPMPCC_OGAM_RAMA_EXP_REGION30_LUT_OFFSET_MASK 0x000001ffUL +#define VPMPCC_OGAM_RAMA_REGION_30_31__VPMPCC_OGAM_RAMA_EXP_REGION30_NUM_SEGMENTS_MASK 0x00007000UL +#define VPMPCC_OGAM_RAMA_REGION_30_31__VPMPCC_OGAM_RAMA_EXP_REGION31_LUT_OFFSET_MASK 0x01ff0000UL +#define VPMPCC_OGAM_RAMA_REGION_30_31__VPMPCC_OGAM_RAMA_EXP_REGION31_NUM_SEGMENTS_MASK 0x70000000UL + +// VPMPCC_OGAM_RAMA_REGION_32_33 +#define VPMPCC_OGAM_RAMA_REGION_32_33__VPMPCC_OGAM_RAMA_EXP_REGION32_LUT_OFFSET_MASK 0x000001ffUL +#define VPMPCC_OGAM_RAMA_REGION_32_33__VPMPCC_OGAM_RAMA_EXP_REGION32_NUM_SEGMENTS_MASK 0x00007000UL +#define VPMPCC_OGAM_RAMA_REGION_32_33__VPMPCC_OGAM_RAMA_EXP_REGION33_LUT_OFFSET_MASK 0x01ff0000UL +#define VPMPCC_OGAM_RAMA_REGION_32_33__VPMPCC_OGAM_RAMA_EXP_REGION33_NUM_SEGMENTS_MASK 0x70000000UL + +// VPMPCC_GAMUT_REMAP_COEF_FORMAT +#define VPMPCC_GAMUT_REMAP_COEF_FORMAT__VPMPCC_GAMUT_REMAP_COEF_FORMAT_MASK 0x00000001UL + +// VPMPCC_GAMUT_REMAP_MODE +#define VPMPCC_GAMUT_REMAP_MODE__VPMPCC_GAMUT_REMAP_MODE_MASK 0x00000001UL +#define VPMPCC_GAMUT_REMAP_MODE__VPMPCC_GAMUT_REMAP_MODE_CURRENT_MASK 0x00000080UL + +// VPMPC_GAMUT_REMAP_C11_C12_A +#define VPMPC_GAMUT_REMAP_C11_C12_A__VPMPCC_GAMUT_REMAP_C11_A_MASK 0x0000ffffUL +#define VPMPC_GAMUT_REMAP_C11_C12_A__VPMPCC_GAMUT_REMAP_C12_A_MASK 0xffff0000UL + +// VPMPC_GAMUT_REMAP_C13_C14_A +#define VPMPC_GAMUT_REMAP_C13_C14_A__VPMPCC_GAMUT_REMAP_C13_A_MASK 0x0000ffffUL +#define VPMPC_GAMUT_REMAP_C13_C14_A__VPMPCC_GAMUT_REMAP_C14_A_MASK 0xffff0000UL + +// VPMPC_GAMUT_REMAP_C21_C22_A +#define VPMPC_GAMUT_REMAP_C21_C22_A__VPMPCC_GAMUT_REMAP_C21_A_MASK 0x0000ffffUL +#define VPMPC_GAMUT_REMAP_C21_C22_A__VPMPCC_GAMUT_REMAP_C22_A_MASK 0xffff0000UL + +// VPMPC_GAMUT_REMAP_C23_C24_A +#define VPMPC_GAMUT_REMAP_C23_C24_A__VPMPCC_GAMUT_REMAP_C23_A_MASK 0x0000ffffUL +#define VPMPC_GAMUT_REMAP_C23_C24_A__VPMPCC_GAMUT_REMAP_C24_A_MASK 0xffff0000UL + +// VPMPC_GAMUT_REMAP_C31_C32_A +#define VPMPC_GAMUT_REMAP_C31_C32_A__VPMPCC_GAMUT_REMAP_C31_A_MASK 0x0000ffffUL +#define VPMPC_GAMUT_REMAP_C31_C32_A__VPMPCC_GAMUT_REMAP_C32_A_MASK 0xffff0000UL + +// VPMPC_GAMUT_REMAP_C33_C34_A +#define VPMPC_GAMUT_REMAP_C33_C34_A__VPMPCC_GAMUT_REMAP_C33_A_MASK 0x0000ffffUL +#define VPMPC_GAMUT_REMAP_C33_C34_A__VPMPCC_GAMUT_REMAP_C34_A_MASK 0xffff0000UL + +// VPMPCC_MCM_1DLUT_CONTROL +#define VPMPCC_MCM_1DLUT_CONTROL__VPMPCC_MCM_1DLUT_MODE_MASK 0x00000003UL +#define VPMPCC_MCM_1DLUT_CONTROL__VPMPCC_MCM_1DLUT_PWL_DISABLE_MASK 0x00000008UL +#define VPMPCC_MCM_1DLUT_CONTROL__VPMPCC_MCM_1DLUT_MODE_CURRENT_MASK 0x00000030UL +#define VPMPCC_MCM_1DLUT_CONTROL__VPMPCC_MCM_1DLUT_SELECT_CURRENT_MASK 0x00000040UL + +// VPMPCC_MCM_1DLUT_LUT_INDEX +#define VPMPCC_MCM_1DLUT_LUT_INDEX__VPMPCC_MCM_1DLUT_LUT_INDEX_MASK 0x000001ffUL + +// VPMPCC_MCM_1DLUT_LUT_DATA +#define VPMPCC_MCM_1DLUT_LUT_DATA__VPMPCC_MCM_1DLUT_LUT_DATA_MASK 0x0003ffffUL + +// VPMPCC_MCM_1DLUT_LUT_CONTROL +#define VPMPCC_MCM_1DLUT_LUT_CONTROL__VPMPCC_MCM_1DLUT_LUT_WRITE_COLOR_MASK_MASK 0x00000007UL +#define VPMPCC_MCM_1DLUT_LUT_CONTROL__VPMPCC_MCM_1DLUT_LUT_READ_COLOR_SEL_MASK 0x00000018UL +#define VPMPCC_MCM_1DLUT_LUT_CONTROL__VPMPCC_MCM_1DLUT_LUT_READ_DBG_MASK 0x00000020UL +#define VPMPCC_MCM_1DLUT_LUT_CONTROL__VPMPCC_MCM_1DLUT_LUT_HOST_SEL_MASK 0x00000040UL +#define VPMPCC_MCM_1DLUT_LUT_CONTROL__VPMPCC_MCM_1DLUT_LUT_CONFIG_MODE_MASK 0x00000080UL + +// VPMPCC_MCM_1DLUT_RAMA_START_CNTL_B +#define VPMPCC_MCM_1DLUT_RAMA_START_CNTL_B__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION_START_B_MASK 0x0003ffffUL +#define VPMPCC_MCM_1DLUT_RAMA_START_CNTL_B__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SEGMENT_B_MASK 0x07f00000UL + +// VPMPCC_MCM_1DLUT_RAMA_START_CNTL_G +#define VPMPCC_MCM_1DLUT_RAMA_START_CNTL_G__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION_START_G_MASK 0x0003ffffUL +#define VPMPCC_MCM_1DLUT_RAMA_START_CNTL_G__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SEGMENT_G_MASK 0x07f00000UL + +// VPMPCC_MCM_1DLUT_RAMA_START_CNTL_R +#define VPMPCC_MCM_1DLUT_RAMA_START_CNTL_R__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION_START_R_MASK 0x0003ffffUL +#define VPMPCC_MCM_1DLUT_RAMA_START_CNTL_R__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SEGMENT_R_MASK 0x07f00000UL + +// VPMPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_B +#define VPMPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_B__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SLOPE_B_MASK 0x0003ffffUL + +// VPMPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_G +#define VPMPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_G__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SLOPE_G_MASK 0x0003ffffUL + +// VPMPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_R +#define VPMPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_R__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SLOPE_R_MASK 0x0003ffffUL + +// VPMPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_B +#define VPMPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_B__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION_START_BASE_B_MASK 0x0003ffffUL + +// VPMPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_G +#define VPMPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_G__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION_START_BASE_G_MASK 0x0003ffffUL + +// VPMPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_R +#define VPMPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_R__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION_START_BASE_R_MASK 0x0003ffffUL + +// VPMPCC_MCM_1DLUT_RAMA_END_CNTL1_B +#define VPMPCC_MCM_1DLUT_RAMA_END_CNTL1_B__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION_END_BASE_B_MASK 0x0003ffffUL + +// VPMPCC_MCM_1DLUT_RAMA_END_CNTL2_B +#define VPMPCC_MCM_1DLUT_RAMA_END_CNTL2_B__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION_END_B_MASK 0x0000ffffUL +#define VPMPCC_MCM_1DLUT_RAMA_END_CNTL2_B__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION_END_SLOPE_B_MASK 0xffff0000UL + +// VPMPCC_MCM_1DLUT_RAMA_END_CNTL1_G +#define VPMPCC_MCM_1DLUT_RAMA_END_CNTL1_G__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION_END_BASE_G_MASK 0x0003ffffUL + +// VPMPCC_MCM_1DLUT_RAMA_END_CNTL2_G +#define VPMPCC_MCM_1DLUT_RAMA_END_CNTL2_G__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION_END_G_MASK 0x0000ffffUL +#define VPMPCC_MCM_1DLUT_RAMA_END_CNTL2_G__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION_END_SLOPE_G_MASK 0xffff0000UL + +// VPMPCC_MCM_1DLUT_RAMA_END_CNTL1_R +#define VPMPCC_MCM_1DLUT_RAMA_END_CNTL1_R__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION_END_BASE_R_MASK 0x0003ffffUL + +// VPMPCC_MCM_1DLUT_RAMA_END_CNTL2_R +#define VPMPCC_MCM_1DLUT_RAMA_END_CNTL2_R__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION_END_R_MASK 0x0000ffffUL +#define VPMPCC_MCM_1DLUT_RAMA_END_CNTL2_R__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION_END_SLOPE_R_MASK 0xffff0000UL + +// VPMPCC_MCM_1DLUT_RAMA_OFFSET_B +#define VPMPCC_MCM_1DLUT_RAMA_OFFSET_B__VPMPCC_MCM_1DLUT_RAMA_OFFSET_B_MASK 0x0007ffffUL + +// VPMPCC_MCM_1DLUT_RAMA_OFFSET_G +#define VPMPCC_MCM_1DLUT_RAMA_OFFSET_G__VPMPCC_MCM_1DLUT_RAMA_OFFSET_G_MASK 0x0007ffffUL + +// VPMPCC_MCM_1DLUT_RAMA_OFFSET_R +#define VPMPCC_MCM_1DLUT_RAMA_OFFSET_R__VPMPCC_MCM_1DLUT_RAMA_OFFSET_R_MASK 0x0007ffffUL + +// VPMPCC_MCM_1DLUT_RAMA_REGION_0_1 +#define VPMPCC_MCM_1DLUT_RAMA_REGION_0_1__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION0_LUT_OFFSET_MASK 0x000001ffUL +#define VPMPCC_MCM_1DLUT_RAMA_REGION_0_1__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION0_NUM_SEGMENTS_MASK 0x00007000UL +#define VPMPCC_MCM_1DLUT_RAMA_REGION_0_1__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION1_LUT_OFFSET_MASK 0x01ff0000UL +#define VPMPCC_MCM_1DLUT_RAMA_REGION_0_1__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION1_NUM_SEGMENTS_MASK 0x70000000UL + +// VPMPCC_MCM_1DLUT_RAMA_REGION_2_3 +#define VPMPCC_MCM_1DLUT_RAMA_REGION_2_3__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION2_LUT_OFFSET_MASK 0x000001ffUL +#define VPMPCC_MCM_1DLUT_RAMA_REGION_2_3__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION2_NUM_SEGMENTS_MASK 0x00007000UL +#define VPMPCC_MCM_1DLUT_RAMA_REGION_2_3__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION3_LUT_OFFSET_MASK 0x01ff0000UL +#define VPMPCC_MCM_1DLUT_RAMA_REGION_2_3__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION3_NUM_SEGMENTS_MASK 0x70000000UL + +// VPMPCC_MCM_1DLUT_RAMA_REGION_4_5 +#define VPMPCC_MCM_1DLUT_RAMA_REGION_4_5__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION4_LUT_OFFSET_MASK 0x000001ffUL +#define VPMPCC_MCM_1DLUT_RAMA_REGION_4_5__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION4_NUM_SEGMENTS_MASK 0x00007000UL +#define VPMPCC_MCM_1DLUT_RAMA_REGION_4_5__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION5_LUT_OFFSET_MASK 0x01ff0000UL +#define VPMPCC_MCM_1DLUT_RAMA_REGION_4_5__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION5_NUM_SEGMENTS_MASK 0x70000000UL + +// VPMPCC_MCM_1DLUT_RAMA_REGION_6_7 +#define VPMPCC_MCM_1DLUT_RAMA_REGION_6_7__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION6_LUT_OFFSET_MASK 0x000001ffUL +#define VPMPCC_MCM_1DLUT_RAMA_REGION_6_7__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION6_NUM_SEGMENTS_MASK 0x00007000UL +#define VPMPCC_MCM_1DLUT_RAMA_REGION_6_7__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION7_LUT_OFFSET_MASK 0x01ff0000UL +#define VPMPCC_MCM_1DLUT_RAMA_REGION_6_7__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION7_NUM_SEGMENTS_MASK 0x70000000UL + +// VPMPCC_MCM_1DLUT_RAMA_REGION_8_9 +#define VPMPCC_MCM_1DLUT_RAMA_REGION_8_9__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION8_LUT_OFFSET_MASK 0x000001ffUL +#define VPMPCC_MCM_1DLUT_RAMA_REGION_8_9__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION8_NUM_SEGMENTS_MASK 0x00007000UL +#define VPMPCC_MCM_1DLUT_RAMA_REGION_8_9__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION9_LUT_OFFSET_MASK 0x01ff0000UL +#define VPMPCC_MCM_1DLUT_RAMA_REGION_8_9__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION9_NUM_SEGMENTS_MASK 0x70000000UL + +// VPMPCC_MCM_1DLUT_RAMA_REGION_10_11 +#define VPMPCC_MCM_1DLUT_RAMA_REGION_10_11__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION10_LUT_OFFSET_MASK 0x000001ffUL +#define VPMPCC_MCM_1DLUT_RAMA_REGION_10_11__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION10_NUM_SEGMENTS_MASK 0x00007000UL +#define VPMPCC_MCM_1DLUT_RAMA_REGION_10_11__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION11_LUT_OFFSET_MASK 0x01ff0000UL +#define VPMPCC_MCM_1DLUT_RAMA_REGION_10_11__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION11_NUM_SEGMENTS_MASK 0x70000000UL + +// VPMPCC_MCM_1DLUT_RAMA_REGION_12_13 +#define VPMPCC_MCM_1DLUT_RAMA_REGION_12_13__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION12_LUT_OFFSET_MASK 0x000001ffUL +#define VPMPCC_MCM_1DLUT_RAMA_REGION_12_13__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION12_NUM_SEGMENTS_MASK 0x00007000UL +#define VPMPCC_MCM_1DLUT_RAMA_REGION_12_13__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION13_LUT_OFFSET_MASK 0x01ff0000UL +#define VPMPCC_MCM_1DLUT_RAMA_REGION_12_13__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION13_NUM_SEGMENTS_MASK 0x70000000UL + +// VPMPCC_MCM_1DLUT_RAMA_REGION_14_15 +#define VPMPCC_MCM_1DLUT_RAMA_REGION_14_15__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION14_LUT_OFFSET_MASK 0x000001ffUL +#define VPMPCC_MCM_1DLUT_RAMA_REGION_14_15__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION14_NUM_SEGMENTS_MASK 0x00007000UL +#define VPMPCC_MCM_1DLUT_RAMA_REGION_14_15__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION15_LUT_OFFSET_MASK 0x01ff0000UL +#define VPMPCC_MCM_1DLUT_RAMA_REGION_14_15__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION15_NUM_SEGMENTS_MASK 0x70000000UL + +// VPMPCC_MCM_1DLUT_RAMA_REGION_16_17 +#define VPMPCC_MCM_1DLUT_RAMA_REGION_16_17__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION16_LUT_OFFSET_MASK 0x000001ffUL +#define VPMPCC_MCM_1DLUT_RAMA_REGION_16_17__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION16_NUM_SEGMENTS_MASK 0x00007000UL +#define VPMPCC_MCM_1DLUT_RAMA_REGION_16_17__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION17_LUT_OFFSET_MASK 0x01ff0000UL +#define VPMPCC_MCM_1DLUT_RAMA_REGION_16_17__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION17_NUM_SEGMENTS_MASK 0x70000000UL + +// VPMPCC_MCM_1DLUT_RAMA_REGION_18_19 +#define VPMPCC_MCM_1DLUT_RAMA_REGION_18_19__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION18_LUT_OFFSET_MASK 0x000001ffUL +#define VPMPCC_MCM_1DLUT_RAMA_REGION_18_19__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION18_NUM_SEGMENTS_MASK 0x00007000UL +#define VPMPCC_MCM_1DLUT_RAMA_REGION_18_19__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION19_LUT_OFFSET_MASK 0x01ff0000UL +#define VPMPCC_MCM_1DLUT_RAMA_REGION_18_19__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION19_NUM_SEGMENTS_MASK 0x70000000UL + +// VPMPCC_MCM_1DLUT_RAMA_REGION_20_21 +#define VPMPCC_MCM_1DLUT_RAMA_REGION_20_21__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION20_LUT_OFFSET_MASK 0x000001ffUL +#define VPMPCC_MCM_1DLUT_RAMA_REGION_20_21__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION20_NUM_SEGMENTS_MASK 0x00007000UL +#define VPMPCC_MCM_1DLUT_RAMA_REGION_20_21__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION21_LUT_OFFSET_MASK 0x01ff0000UL +#define VPMPCC_MCM_1DLUT_RAMA_REGION_20_21__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION21_NUM_SEGMENTS_MASK 0x70000000UL + +// VPMPCC_MCM_1DLUT_RAMA_REGION_22_23 +#define VPMPCC_MCM_1DLUT_RAMA_REGION_22_23__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION22_LUT_OFFSET_MASK 0x000001ffUL +#define VPMPCC_MCM_1DLUT_RAMA_REGION_22_23__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION22_NUM_SEGMENTS_MASK 0x00007000UL +#define VPMPCC_MCM_1DLUT_RAMA_REGION_22_23__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION23_LUT_OFFSET_MASK 0x01ff0000UL +#define VPMPCC_MCM_1DLUT_RAMA_REGION_22_23__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION23_NUM_SEGMENTS_MASK 0x70000000UL + +// VPMPCC_MCM_1DLUT_RAMA_REGION_24_25 +#define VPMPCC_MCM_1DLUT_RAMA_REGION_24_25__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION24_LUT_OFFSET_MASK 0x000001ffUL +#define VPMPCC_MCM_1DLUT_RAMA_REGION_24_25__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION24_NUM_SEGMENTS_MASK 0x00007000UL +#define VPMPCC_MCM_1DLUT_RAMA_REGION_24_25__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION25_LUT_OFFSET_MASK 0x01ff0000UL +#define VPMPCC_MCM_1DLUT_RAMA_REGION_24_25__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION25_NUM_SEGMENTS_MASK 0x70000000UL + +// VPMPCC_MCM_1DLUT_RAMA_REGION_26_27 +#define VPMPCC_MCM_1DLUT_RAMA_REGION_26_27__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION26_LUT_OFFSET_MASK 0x000001ffUL +#define VPMPCC_MCM_1DLUT_RAMA_REGION_26_27__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION26_NUM_SEGMENTS_MASK 0x00007000UL +#define VPMPCC_MCM_1DLUT_RAMA_REGION_26_27__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION27_LUT_OFFSET_MASK 0x01ff0000UL +#define VPMPCC_MCM_1DLUT_RAMA_REGION_26_27__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION27_NUM_SEGMENTS_MASK 0x70000000UL + +// VPMPCC_MCM_1DLUT_RAMA_REGION_28_29 +#define VPMPCC_MCM_1DLUT_RAMA_REGION_28_29__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION28_LUT_OFFSET_MASK 0x000001ffUL +#define VPMPCC_MCM_1DLUT_RAMA_REGION_28_29__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION28_NUM_SEGMENTS_MASK 0x00007000UL +#define VPMPCC_MCM_1DLUT_RAMA_REGION_28_29__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION29_LUT_OFFSET_MASK 0x01ff0000UL +#define VPMPCC_MCM_1DLUT_RAMA_REGION_28_29__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION29_NUM_SEGMENTS_MASK 0x70000000UL + +// VPMPCC_MCM_1DLUT_RAMA_REGION_30_31 +#define VPMPCC_MCM_1DLUT_RAMA_REGION_30_31__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION30_LUT_OFFSET_MASK 0x000001ffUL +#define VPMPCC_MCM_1DLUT_RAMA_REGION_30_31__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION30_NUM_SEGMENTS_MASK 0x00007000UL +#define VPMPCC_MCM_1DLUT_RAMA_REGION_30_31__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION31_LUT_OFFSET_MASK 0x01ff0000UL +#define VPMPCC_MCM_1DLUT_RAMA_REGION_30_31__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION31_NUM_SEGMENTS_MASK 0x70000000UL + +// VPMPCC_MCM_1DLUT_RAMA_REGION_32_33 +#define VPMPCC_MCM_1DLUT_RAMA_REGION_32_33__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION32_LUT_OFFSET_MASK 0x000001ffUL +#define VPMPCC_MCM_1DLUT_RAMA_REGION_32_33__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION32_NUM_SEGMENTS_MASK 0x00007000UL +#define VPMPCC_MCM_1DLUT_RAMA_REGION_32_33__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION33_LUT_OFFSET_MASK 0x01ff0000UL +#define VPMPCC_MCM_1DLUT_RAMA_REGION_32_33__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION33_NUM_SEGMENTS_MASK 0x70000000UL + +// VPMPCC_MCM_FIRST_GAMUT_REMAP_COEF_FORMAT +#define VPMPCC_MCM_FIRST_GAMUT_REMAP_COEF_FORMAT__VPMPCC_MCM_FIRST_GAMUT_REMAP_COEF_FORMAT_MASK 0x00000001UL + +// VPMPCC_MCM_FIRST_GAMUT_REMAP_MODE +#define VPMPCC_MCM_FIRST_GAMUT_REMAP_MODE__VPMPCC_MCM_FIRST_GAMUT_REMAP_MODE_MASK 0x00000003UL +#define VPMPCC_MCM_FIRST_GAMUT_REMAP_MODE__VPMPCC_MCM_FIRST_GAMUT_REMAP_MODE_CURRENT_MASK 0x00000180UL + +// VPMPC_MCM_FIRST_GAMUT_REMAP_C11_C12_SETA +#define VPMPC_MCM_FIRST_GAMUT_REMAP_C11_C12_SETA__VPMPCC_MCM_FIRST_GAMUT_REMAP_C11_SETA_MASK 0x0000ffffUL +#define VPMPC_MCM_FIRST_GAMUT_REMAP_C11_C12_SETA__VPMPCC_MCM_FIRST_GAMUT_REMAP_C12_SETA_MASK 0xffff0000UL + +// VPMPC_MCM_FIRST_GAMUT_REMAP_C13_C14_SETA +#define VPMPC_MCM_FIRST_GAMUT_REMAP_C13_C14_SETA__VPMPCC_MCM_FIRST_GAMUT_REMAP_C13_SETA_MASK 0x0000ffffUL +#define VPMPC_MCM_FIRST_GAMUT_REMAP_C13_C14_SETA__VPMPCC_MCM_FIRST_GAMUT_REMAP_C14_SETA_MASK 0xffff0000UL + +// VPMPC_MCM_FIRST_GAMUT_REMAP_C21_C22_SETA +#define VPMPC_MCM_FIRST_GAMUT_REMAP_C21_C22_SETA__VPMPCC_MCM_FIRST_GAMUT_REMAP_C21_SETA_MASK 0x0000ffffUL +#define VPMPC_MCM_FIRST_GAMUT_REMAP_C21_C22_SETA__VPMPCC_MCM_FIRST_GAMUT_REMAP_C22_SETA_MASK 0xffff0000UL + +// VPMPC_MCM_FIRST_GAMUT_REMAP_C23_C24_SETA +#define VPMPC_MCM_FIRST_GAMUT_REMAP_C23_C24_SETA__VPMPCC_MCM_FIRST_GAMUT_REMAP_C23_SETA_MASK 0x0000ffffUL +#define VPMPC_MCM_FIRST_GAMUT_REMAP_C23_C24_SETA__VPMPCC_MCM_FIRST_GAMUT_REMAP_C24_SETA_MASK 0xffff0000UL + +// VPMPC_MCM_FIRST_GAMUT_REMAP_C31_C32_SETA +#define VPMPC_MCM_FIRST_GAMUT_REMAP_C31_C32_SETA__VPMPCC_MCM_FIRST_GAMUT_REMAP_C31_SETA_MASK 0x0000ffffUL +#define VPMPC_MCM_FIRST_GAMUT_REMAP_C31_C32_SETA__VPMPCC_MCM_FIRST_GAMUT_REMAP_C32_SETA_MASK 0xffff0000UL + +// VPMPC_MCM_FIRST_GAMUT_REMAP_C33_C34_SETA +#define VPMPC_MCM_FIRST_GAMUT_REMAP_C33_C34_SETA__VPMPCC_MCM_FIRST_GAMUT_REMAP_C33_SETA_MASK 0x0000ffffUL +#define VPMPC_MCM_FIRST_GAMUT_REMAP_C33_C34_SETA__VPMPCC_MCM_FIRST_GAMUT_REMAP_C34_SETA_MASK 0xffff0000UL + +// VPMPCC_MCM_SECOND_GAMUT_REMAP_COEF_FORMAT +#define VPMPCC_MCM_SECOND_GAMUT_REMAP_COEF_FORMAT__VPMPCC_MCM_SECOND_GAMUT_REMAP_COEF_FORMAT_MASK 0x00000001UL + +// VPMPCC_MCM_SECOND_GAMUT_REMAP_MODE +#define VPMPCC_MCM_SECOND_GAMUT_REMAP_MODE__VPMPCC_MCM_SECOND_GAMUT_REMAP_MODE_MASK 0x00000003UL +#define VPMPCC_MCM_SECOND_GAMUT_REMAP_MODE__VPMPCC_MCM_SECOND_GAMUT_REMAP_MODE_CURRENT_MASK 0x00000180UL + +// VPMPC_MCM_SECOND_GAMUT_REMAP_C11_C12_SETA +#define VPMPC_MCM_SECOND_GAMUT_REMAP_C11_C12_SETA__VPMPCC_MCM_SECOND_GAMUT_REMAP_C11_SETA_MASK 0x0000ffffUL +#define VPMPC_MCM_SECOND_GAMUT_REMAP_C11_C12_SETA__VPMPCC_MCM_SECOND_GAMUT_REMAP_C12_SETA_MASK 0xffff0000UL + +// VPMPC_MCM_SECOND_GAMUT_REMAP_C13_C14_SETA +#define VPMPC_MCM_SECOND_GAMUT_REMAP_C13_C14_SETA__VPMPCC_MCM_SECOND_GAMUT_REMAP_C13_SETA_MASK 0x0000ffffUL +#define VPMPC_MCM_SECOND_GAMUT_REMAP_C13_C14_SETA__VPMPCC_MCM_SECOND_GAMUT_REMAP_C14_SETA_MASK 0xffff0000UL + +// VPMPC_MCM_SECOND_GAMUT_REMAP_C21_C22_SETA +#define VPMPC_MCM_SECOND_GAMUT_REMAP_C21_C22_SETA__VPMPCC_MCM_SECOND_GAMUT_REMAP_C21_SETA_MASK 0x0000ffffUL +#define VPMPC_MCM_SECOND_GAMUT_REMAP_C21_C22_SETA__VPMPCC_MCM_SECOND_GAMUT_REMAP_C22_SETA_MASK 0xffff0000UL + +// VPMPC_MCM_SECOND_GAMUT_REMAP_C23_C24_SETA +#define VPMPC_MCM_SECOND_GAMUT_REMAP_C23_C24_SETA__VPMPCC_MCM_SECOND_GAMUT_REMAP_C23_SETA_MASK 0x0000ffffUL +#define VPMPC_MCM_SECOND_GAMUT_REMAP_C23_C24_SETA__VPMPCC_MCM_SECOND_GAMUT_REMAP_C24_SETA_MASK 0xffff0000UL + +// VPMPC_MCM_SECOND_GAMUT_REMAP_C31_C32_SETA +#define VPMPC_MCM_SECOND_GAMUT_REMAP_C31_C32_SETA__VPMPCC_MCM_SECOND_GAMUT_REMAP_C31_SETA_MASK 0x0000ffffUL +#define VPMPC_MCM_SECOND_GAMUT_REMAP_C31_C32_SETA__VPMPCC_MCM_SECOND_GAMUT_REMAP_C32_SETA_MASK 0xffff0000UL + +// VPMPC_MCM_SECOND_GAMUT_REMAP_C33_C34_SETA +#define VPMPC_MCM_SECOND_GAMUT_REMAP_C33_C34_SETA__VPMPCC_MCM_SECOND_GAMUT_REMAP_C33_SETA_MASK 0x0000ffffUL +#define VPMPC_MCM_SECOND_GAMUT_REMAP_C33_C34_SETA__VPMPCC_MCM_SECOND_GAMUT_REMAP_C34_SETA_MASK 0xffff0000UL + +// VPMPCC_MCM_MEM_PWR_CTRL +#define VPMPCC_MCM_MEM_PWR_CTRL__VPMPCC_MCM_1DLUT_MEM_PWR_FORCE_MASK 0x00030000UL +#define VPMPCC_MCM_MEM_PWR_CTRL__VPMPCC_MCM_1DLUT_MEM_PWR_DIS_MASK 0x00040000UL +#define VPMPCC_MCM_MEM_PWR_CTRL__VPMPCC_MCM_1DLUT_MEM_LOW_PWR_MODE_MASK 0x00300000UL +#define VPMPCC_MCM_MEM_PWR_CTRL__VPMPCC_MCM_1DLUT_MEM_PWR_STATE_MASK 0x30000000UL + +// VPMPC_RMCM_SHAPER_CONTROL +#define VPMPC_RMCM_SHAPER_CONTROL__VPMPC_RMCM_SHAPER_LUT_MODE_MASK 0x00000003UL +#define VPMPC_RMCM_SHAPER_CONTROL__VPMPC_RMCM_SHAPER_MODE_CURRENT_MASK 0x0000000cUL +#define VPMPC_RMCM_SHAPER_CONTROL__VPMPC_RMCM_SHAPER_SELECT_CURRENT_MASK 0x00000010UL + +// VPMPC_RMCM_SHAPER_OFFSET_R +#define VPMPC_RMCM_SHAPER_OFFSET_R__VPMPC_RMCM_SHAPER_OFFSET_R_MASK 0x0007ffffUL + +// VPMPC_RMCM_SHAPER_OFFSET_G +#define VPMPC_RMCM_SHAPER_OFFSET_G__VPMPC_RMCM_SHAPER_OFFSET_G_MASK 0x0007ffffUL + +// VPMPC_RMCM_SHAPER_OFFSET_B +#define VPMPC_RMCM_SHAPER_OFFSET_B__VPMPC_RMCM_SHAPER_OFFSET_B_MASK 0x0007ffffUL + +// VPMPC_RMCM_SHAPER_SCALE_R +#define VPMPC_RMCM_SHAPER_SCALE_R__VPMPC_RMCM_SHAPER_SCALE_R_MASK 0x0000ffffUL + +// VPMPC_RMCM_SHAPER_SCALE_G_B +#define VPMPC_RMCM_SHAPER_SCALE_G_B__VPMPC_RMCM_SHAPER_SCALE_G_MASK 0x0000ffffUL +#define VPMPC_RMCM_SHAPER_SCALE_G_B__VPMPC_RMCM_SHAPER_SCALE_B_MASK 0xffff0000UL + +// VPMPC_RMCM_SHAPER_LUT_INDEX +#define VPMPC_RMCM_SHAPER_LUT_INDEX__VPMPC_RMCM_SHAPER_LUT_INDEX_MASK 0x000000ffUL + +// VPMPC_RMCM_SHAPER_LUT_DATA +#define VPMPC_RMCM_SHAPER_LUT_DATA__VPMPC_RMCM_SHAPER_LUT_DATA_MASK 0x00ffffffUL + +// VPMPC_RMCM_SHAPER_LUT_WRITE_EN_MASK +#define VPMPC_RMCM_SHAPER_LUT_WRITE_EN_MASK__VPMPC_RMCM_SHAPER_LUT_WRITE_EN_MASK_MASK 0x00000007UL +#define VPMPC_RMCM_SHAPER_LUT_WRITE_EN_MASK__VPMPC_RMCM_SHAPER_LUT_WRITE_SEL_MASK 0x00000010UL + +// VPMPC_RMCM_SHAPER_RAMA_START_CNTL_B +#define VPMPC_RMCM_SHAPER_RAMA_START_CNTL_B__VPMPC_RMCM_SHAPER_RAMA_EXP_REGION_START_B_MASK 0x0003ffffUL +#define VPMPC_RMCM_SHAPER_RAMA_START_CNTL_B__VPMPC_RMCM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_B_MASK 0x07f00000UL + +// VPMPC_RMCM_SHAPER_RAMA_START_CNTL_G +#define VPMPC_RMCM_SHAPER_RAMA_START_CNTL_G__VPMPC_RMCM_SHAPER_RAMA_EXP_REGION_START_G_MASK 0x0003ffffUL +#define VPMPC_RMCM_SHAPER_RAMA_START_CNTL_G__VPMPC_RMCM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_G_MASK 0x07f00000UL + +// VPMPC_RMCM_SHAPER_RAMA_START_CNTL_R +#define VPMPC_RMCM_SHAPER_RAMA_START_CNTL_R__VPMPC_RMCM_SHAPER_RAMA_EXP_REGION_START_R_MASK 0x0003ffffUL +#define VPMPC_RMCM_SHAPER_RAMA_START_CNTL_R__VPMPC_RMCM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_R_MASK 0x07f00000UL + +// VPMPC_RMCM_SHAPER_RAMA_END_CNTL_B +#define VPMPC_RMCM_SHAPER_RAMA_END_CNTL_B__VPMPC_RMCM_SHAPER_RAMA_EXP_REGION_END_B_MASK 0x0000ffffUL +#define VPMPC_RMCM_SHAPER_RAMA_END_CNTL_B__VPMPC_RMCM_SHAPER_RAMA_EXP_REGION_END_BASE_B_MASK 0x3fff0000UL + +// VPMPC_RMCM_SHAPER_RAMA_END_CNTL_G +#define VPMPC_RMCM_SHAPER_RAMA_END_CNTL_G__VPMPC_RMCM_SHAPER_RAMA_EXP_REGION_END_G_MASK 0x0000ffffUL +#define VPMPC_RMCM_SHAPER_RAMA_END_CNTL_G__VPMPC_RMCM_SHAPER_RAMA_EXP_REGION_END_BASE_G_MASK 0x3fff0000UL + +// VPMPC_RMCM_SHAPER_RAMA_END_CNTL_R +#define VPMPC_RMCM_SHAPER_RAMA_END_CNTL_R__VPMPC_RMCM_SHAPER_RAMA_EXP_REGION_END_R_MASK 0x0000ffffUL +#define VPMPC_RMCM_SHAPER_RAMA_END_CNTL_R__VPMPC_RMCM_SHAPER_RAMA_EXP_REGION_END_BASE_R_MASK 0x3fff0000UL + +// VPMPC_RMCM_SHAPER_RAMA_REGION_0_1 +#define VPMPC_RMCM_SHAPER_RAMA_REGION_0_1__VPMPC_RMCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET_MASK 0x000001ffUL +#define VPMPC_RMCM_SHAPER_RAMA_REGION_0_1__VPMPC_RMCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS_MASK 0x00007000UL +#define VPMPC_RMCM_SHAPER_RAMA_REGION_0_1__VPMPC_RMCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET_MASK 0x01ff0000UL +#define VPMPC_RMCM_SHAPER_RAMA_REGION_0_1__VPMPC_RMCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS_MASK 0x70000000UL + +// VPMPC_RMCM_SHAPER_RAMA_REGION_2_3 +#define VPMPC_RMCM_SHAPER_RAMA_REGION_2_3__VPMPC_RMCM_SHAPER_RAMA_EXP_REGION2_LUT_OFFSET_MASK 0x000001ffUL +#define VPMPC_RMCM_SHAPER_RAMA_REGION_2_3__VPMPC_RMCM_SHAPER_RAMA_EXP_REGION2_NUM_SEGMENTS_MASK 0x00007000UL +#define VPMPC_RMCM_SHAPER_RAMA_REGION_2_3__VPMPC_RMCM_SHAPER_RAMA_EXP_REGION3_LUT_OFFSET_MASK 0x01ff0000UL +#define VPMPC_RMCM_SHAPER_RAMA_REGION_2_3__VPMPC_RMCM_SHAPER_RAMA_EXP_REGION3_NUM_SEGMENTS_MASK 0x70000000UL + +// VPMPC_RMCM_SHAPER_RAMA_REGION_4_5 +#define VPMPC_RMCM_SHAPER_RAMA_REGION_4_5__VPMPC_RMCM_SHAPER_RAMA_EXP_REGION4_LUT_OFFSET_MASK 0x000001ffUL +#define VPMPC_RMCM_SHAPER_RAMA_REGION_4_5__VPMPC_RMCM_SHAPER_RAMA_EXP_REGION4_NUM_SEGMENTS_MASK 0x00007000UL +#define VPMPC_RMCM_SHAPER_RAMA_REGION_4_5__VPMPC_RMCM_SHAPER_RAMA_EXP_REGION5_LUT_OFFSET_MASK 0x01ff0000UL +#define VPMPC_RMCM_SHAPER_RAMA_REGION_4_5__VPMPC_RMCM_SHAPER_RAMA_EXP_REGION5_NUM_SEGMENTS_MASK 0x70000000UL + +// VPMPC_RMCM_SHAPER_RAMA_REGION_6_7 +#define VPMPC_RMCM_SHAPER_RAMA_REGION_6_7__VPMPC_RMCM_SHAPER_RAMA_EXP_REGION6_LUT_OFFSET_MASK 0x000001ffUL +#define VPMPC_RMCM_SHAPER_RAMA_REGION_6_7__VPMPC_RMCM_SHAPER_RAMA_EXP_REGION6_NUM_SEGMENTS_MASK 0x00007000UL +#define VPMPC_RMCM_SHAPER_RAMA_REGION_6_7__VPMPC_RMCM_SHAPER_RAMA_EXP_REGION7_LUT_OFFSET_MASK 0x01ff0000UL +#define VPMPC_RMCM_SHAPER_RAMA_REGION_6_7__VPMPC_RMCM_SHAPER_RAMA_EXP_REGION7_NUM_SEGMENTS_MASK 0x70000000UL + +// VPMPC_RMCM_SHAPER_RAMA_REGION_8_9 +#define VPMPC_RMCM_SHAPER_RAMA_REGION_8_9__VPMPC_RMCM_SHAPER_RAMA_EXP_REGION8_LUT_OFFSET_MASK 0x000001ffUL +#define VPMPC_RMCM_SHAPER_RAMA_REGION_8_9__VPMPC_RMCM_SHAPER_RAMA_EXP_REGION8_NUM_SEGMENTS_MASK 0x00007000UL +#define VPMPC_RMCM_SHAPER_RAMA_REGION_8_9__VPMPC_RMCM_SHAPER_RAMA_EXP_REGION9_LUT_OFFSET_MASK 0x01ff0000UL +#define VPMPC_RMCM_SHAPER_RAMA_REGION_8_9__VPMPC_RMCM_SHAPER_RAMA_EXP_REGION9_NUM_SEGMENTS_MASK 0x70000000UL + +// VPMPC_RMCM_SHAPER_RAMA_REGION_10_11 +#define VPMPC_RMCM_SHAPER_RAMA_REGION_10_11__VPMPC_RMCM_SHAPER_RAMA_EXP_REGION10_LUT_OFFSET_MASK 0x000001ffUL +#define VPMPC_RMCM_SHAPER_RAMA_REGION_10_11__VPMPC_RMCM_SHAPER_RAMA_EXP_REGION10_NUM_SEGMENTS_MASK 0x00007000UL +#define VPMPC_RMCM_SHAPER_RAMA_REGION_10_11__VPMPC_RMCM_SHAPER_RAMA_EXP_REGION11_LUT_OFFSET_MASK 0x01ff0000UL +#define VPMPC_RMCM_SHAPER_RAMA_REGION_10_11__VPMPC_RMCM_SHAPER_RAMA_EXP_REGION11_NUM_SEGMENTS_MASK 0x70000000UL + +// VPMPC_RMCM_SHAPER_RAMA_REGION_12_13 +#define VPMPC_RMCM_SHAPER_RAMA_REGION_12_13__VPMPC_RMCM_SHAPER_RAMA_EXP_REGION12_LUT_OFFSET_MASK 0x000001ffUL +#define VPMPC_RMCM_SHAPER_RAMA_REGION_12_13__VPMPC_RMCM_SHAPER_RAMA_EXP_REGION12_NUM_SEGMENTS_MASK 0x00007000UL +#define VPMPC_RMCM_SHAPER_RAMA_REGION_12_13__VPMPC_RMCM_SHAPER_RAMA_EXP_REGION13_LUT_OFFSET_MASK 0x01ff0000UL +#define VPMPC_RMCM_SHAPER_RAMA_REGION_12_13__VPMPC_RMCM_SHAPER_RAMA_EXP_REGION13_NUM_SEGMENTS_MASK 0x70000000UL + +// VPMPC_RMCM_SHAPER_RAMA_REGION_14_15 +#define VPMPC_RMCM_SHAPER_RAMA_REGION_14_15__VPMPC_RMCM_SHAPER_RAMA_EXP_REGION14_LUT_OFFSET_MASK 0x000001ffUL +#define VPMPC_RMCM_SHAPER_RAMA_REGION_14_15__VPMPC_RMCM_SHAPER_RAMA_EXP_REGION14_NUM_SEGMENTS_MASK 0x00007000UL +#define VPMPC_RMCM_SHAPER_RAMA_REGION_14_15__VPMPC_RMCM_SHAPER_RAMA_EXP_REGION15_LUT_OFFSET_MASK 0x01ff0000UL +#define VPMPC_RMCM_SHAPER_RAMA_REGION_14_15__VPMPC_RMCM_SHAPER_RAMA_EXP_REGION15_NUM_SEGMENTS_MASK 0x70000000UL + +// VPMPC_RMCM_SHAPER_RAMA_REGION_16_17 +#define VPMPC_RMCM_SHAPER_RAMA_REGION_16_17__VPMPC_RMCM_SHAPER_RAMA_EXP_REGION16_LUT_OFFSET_MASK 0x000001ffUL +#define VPMPC_RMCM_SHAPER_RAMA_REGION_16_17__VPMPC_RMCM_SHAPER_RAMA_EXP_REGION16_NUM_SEGMENTS_MASK 0x00007000UL +#define VPMPC_RMCM_SHAPER_RAMA_REGION_16_17__VPMPC_RMCM_SHAPER_RAMA_EXP_REGION17_LUT_OFFSET_MASK 0x01ff0000UL +#define VPMPC_RMCM_SHAPER_RAMA_REGION_16_17__VPMPC_RMCM_SHAPER_RAMA_EXP_REGION17_NUM_SEGMENTS_MASK 0x70000000UL + +// VPMPC_RMCM_SHAPER_RAMA_REGION_18_19 +#define VPMPC_RMCM_SHAPER_RAMA_REGION_18_19__VPMPC_RMCM_SHAPER_RAMA_EXP_REGION18_LUT_OFFSET_MASK 0x000001ffUL +#define VPMPC_RMCM_SHAPER_RAMA_REGION_18_19__VPMPC_RMCM_SHAPER_RAMA_EXP_REGION18_NUM_SEGMENTS_MASK 0x00007000UL +#define VPMPC_RMCM_SHAPER_RAMA_REGION_18_19__VPMPC_RMCM_SHAPER_RAMA_EXP_REGION19_LUT_OFFSET_MASK 0x01ff0000UL +#define VPMPC_RMCM_SHAPER_RAMA_REGION_18_19__VPMPC_RMCM_SHAPER_RAMA_EXP_REGION19_NUM_SEGMENTS_MASK 0x70000000UL + +// VPMPC_RMCM_SHAPER_RAMA_REGION_20_21 +#define VPMPC_RMCM_SHAPER_RAMA_REGION_20_21__VPMPC_RMCM_SHAPER_RAMA_EXP_REGION20_LUT_OFFSET_MASK 0x000001ffUL +#define VPMPC_RMCM_SHAPER_RAMA_REGION_20_21__VPMPC_RMCM_SHAPER_RAMA_EXP_REGION20_NUM_SEGMENTS_MASK 0x00007000UL +#define VPMPC_RMCM_SHAPER_RAMA_REGION_20_21__VPMPC_RMCM_SHAPER_RAMA_EXP_REGION21_LUT_OFFSET_MASK 0x01ff0000UL +#define VPMPC_RMCM_SHAPER_RAMA_REGION_20_21__VPMPC_RMCM_SHAPER_RAMA_EXP_REGION21_NUM_SEGMENTS_MASK 0x70000000UL + +// VPMPC_RMCM_SHAPER_RAMA_REGION_22_23 +#define VPMPC_RMCM_SHAPER_RAMA_REGION_22_23__VPMPC_RMCM_SHAPER_RAMA_EXP_REGION22_LUT_OFFSET_MASK 0x000001ffUL +#define VPMPC_RMCM_SHAPER_RAMA_REGION_22_23__VPMPC_RMCM_SHAPER_RAMA_EXP_REGION22_NUM_SEGMENTS_MASK 0x00007000UL +#define VPMPC_RMCM_SHAPER_RAMA_REGION_22_23__VPMPC_RMCM_SHAPER_RAMA_EXP_REGION23_LUT_OFFSET_MASK 0x01ff0000UL +#define VPMPC_RMCM_SHAPER_RAMA_REGION_22_23__VPMPC_RMCM_SHAPER_RAMA_EXP_REGION23_NUM_SEGMENTS_MASK 0x70000000UL + +// VPMPC_RMCM_SHAPER_RAMA_REGION_24_25 +#define VPMPC_RMCM_SHAPER_RAMA_REGION_24_25__VPMPC_RMCM_SHAPER_RAMA_EXP_REGION24_LUT_OFFSET_MASK 0x000001ffUL +#define VPMPC_RMCM_SHAPER_RAMA_REGION_24_25__VPMPC_RMCM_SHAPER_RAMA_EXP_REGION24_NUM_SEGMENTS_MASK 0x00007000UL +#define VPMPC_RMCM_SHAPER_RAMA_REGION_24_25__VPMPC_RMCM_SHAPER_RAMA_EXP_REGION25_LUT_OFFSET_MASK 0x01ff0000UL +#define VPMPC_RMCM_SHAPER_RAMA_REGION_24_25__VPMPC_RMCM_SHAPER_RAMA_EXP_REGION25_NUM_SEGMENTS_MASK 0x70000000UL + +// VPMPC_RMCM_SHAPER_RAMA_REGION_26_27 +#define VPMPC_RMCM_SHAPER_RAMA_REGION_26_27__VPMPC_RMCM_SHAPER_RAMA_EXP_REGION26_LUT_OFFSET_MASK 0x000001ffUL +#define VPMPC_RMCM_SHAPER_RAMA_REGION_26_27__VPMPC_RMCM_SHAPER_RAMA_EXP_REGION26_NUM_SEGMENTS_MASK 0x00007000UL +#define VPMPC_RMCM_SHAPER_RAMA_REGION_26_27__VPMPC_RMCM_SHAPER_RAMA_EXP_REGION27_LUT_OFFSET_MASK 0x01ff0000UL +#define VPMPC_RMCM_SHAPER_RAMA_REGION_26_27__VPMPC_RMCM_SHAPER_RAMA_EXP_REGION27_NUM_SEGMENTS_MASK 0x70000000UL + +// VPMPC_RMCM_SHAPER_RAMA_REGION_28_29 +#define VPMPC_RMCM_SHAPER_RAMA_REGION_28_29__VPMPC_RMCM_SHAPER_RAMA_EXP_REGION28_LUT_OFFSET_MASK 0x000001ffUL +#define VPMPC_RMCM_SHAPER_RAMA_REGION_28_29__VPMPC_RMCM_SHAPER_RAMA_EXP_REGION28_NUM_SEGMENTS_MASK 0x00007000UL +#define VPMPC_RMCM_SHAPER_RAMA_REGION_28_29__VPMPC_RMCM_SHAPER_RAMA_EXP_REGION29_LUT_OFFSET_MASK 0x01ff0000UL +#define VPMPC_RMCM_SHAPER_RAMA_REGION_28_29__VPMPC_RMCM_SHAPER_RAMA_EXP_REGION29_NUM_SEGMENTS_MASK 0x70000000UL + +// VPMPC_RMCM_SHAPER_RAMA_REGION_30_31 +#define VPMPC_RMCM_SHAPER_RAMA_REGION_30_31__VPMPC_RMCM_SHAPER_RAMA_EXP_REGION30_LUT_OFFSET_MASK 0x000001ffUL +#define VPMPC_RMCM_SHAPER_RAMA_REGION_30_31__VPMPC_RMCM_SHAPER_RAMA_EXP_REGION30_NUM_SEGMENTS_MASK 0x00007000UL +#define VPMPC_RMCM_SHAPER_RAMA_REGION_30_31__VPMPC_RMCM_SHAPER_RAMA_EXP_REGION31_LUT_OFFSET_MASK 0x01ff0000UL +#define VPMPC_RMCM_SHAPER_RAMA_REGION_30_31__VPMPC_RMCM_SHAPER_RAMA_EXP_REGION31_NUM_SEGMENTS_MASK 0x70000000UL + +// VPMPC_RMCM_SHAPER_RAMA_REGION_32_33 +#define VPMPC_RMCM_SHAPER_RAMA_REGION_32_33__VPMPC_RMCM_SHAPER_RAMA_EXP_REGION32_LUT_OFFSET_MASK 0x000001ffUL +#define VPMPC_RMCM_SHAPER_RAMA_REGION_32_33__VPMPC_RMCM_SHAPER_RAMA_EXP_REGION32_NUM_SEGMENTS_MASK 0x00007000UL +#define VPMPC_RMCM_SHAPER_RAMA_REGION_32_33__VPMPC_RMCM_SHAPER_RAMA_EXP_REGION33_LUT_OFFSET_MASK 0x01ff0000UL +#define VPMPC_RMCM_SHAPER_RAMA_REGION_32_33__VPMPC_RMCM_SHAPER_RAMA_EXP_REGION33_NUM_SEGMENTS_MASK 0x70000000UL + +// VPMPC_RMCM_3DLUT_MODE +#define VPMPC_RMCM_3DLUT_MODE__VPMPC_RMCM_3DLUT_MODE_MASK 0x00000003UL +#define VPMPC_RMCM_3DLUT_MODE__VPMPC_RMCM_3DLUT_SIZE_MASK 0x00000030UL +#define VPMPC_RMCM_3DLUT_MODE__VPMPC_RMCM_3DLUT_MODE_CURRENT_MASK 0x00000300UL +#define VPMPC_RMCM_3DLUT_MODE__VPMPC_RMCM_3DLUT_SELECT_CURRENT_MASK 0x00000400UL + +// VPMPC_RMCM_3DLUT_INDEX +#define VPMPC_RMCM_3DLUT_INDEX__VPMPC_RMCM_3DLUT_INDEX_MASK 0x00003fffUL + +// VPMPC_RMCM_3DLUT_DATA +#define VPMPC_RMCM_3DLUT_DATA__VPMPC_RMCM_3DLUT_DATA0_MASK 0x0000ffffUL +#define VPMPC_RMCM_3DLUT_DATA__VPMPC_RMCM_3DLUT_DATA1_MASK 0xffff0000UL + +// VPMPC_RMCM_3DLUT_DATA_30BIT +#define VPMPC_RMCM_3DLUT_DATA_30BIT__VPMPC_RMCM_3DLUT_DATA_30BIT_MASK 0xfffffffcUL + +// VPMPC_RMCM_3DLUT_READ_WRITE_CONTROL +#define VPMPC_RMCM_3DLUT_READ_WRITE_CONTROL__VPMPC_RMCM_3DLUT_WRITE_EN_MASK_MASK 0x0000000fUL +#define VPMPC_RMCM_3DLUT_READ_WRITE_CONTROL__VPMPC_RMCM_3DLUT_RAM_SEL_MASK 0x00000010UL +#define VPMPC_RMCM_3DLUT_READ_WRITE_CONTROL__VPMPC_RMCM_3DLUT_30BIT_EN_MASK 0x00000100UL +#define VPMPC_RMCM_3DLUT_READ_WRITE_CONTROL__VPMPC_RMCM_3DLUT_READ_SEL_MASK 0x00030000UL + +// VPMPC_RMCM_3DLUT_OUT_NORM_FACTOR +#define VPMPC_RMCM_3DLUT_OUT_NORM_FACTOR__VPMPC_RMCM_3DLUT_OUT_NORM_FACTOR_MASK 0x0000ffffUL + +// VPMPC_RMCM_3DLUT_OUT_OFFSET_R +#define VPMPC_RMCM_3DLUT_OUT_OFFSET_R__VPMPC_RMCM_3DLUT_OUT_OFFSET_R_MASK 0x0000ffffUL +#define VPMPC_RMCM_3DLUT_OUT_OFFSET_R__VPMPC_RMCM_3DLUT_OUT_SCALE_R_MASK 0xffff0000UL + +// VPMPC_RMCM_3DLUT_OUT_OFFSET_G +#define VPMPC_RMCM_3DLUT_OUT_OFFSET_G__VPMPC_RMCM_3DLUT_OUT_OFFSET_G_MASK 0x0000ffffUL +#define VPMPC_RMCM_3DLUT_OUT_OFFSET_G__VPMPC_RMCM_3DLUT_OUT_SCALE_G_MASK 0xffff0000UL + +// VPMPC_RMCM_3DLUT_OUT_OFFSET_B +#define VPMPC_RMCM_3DLUT_OUT_OFFSET_B__VPMPC_RMCM_3DLUT_OUT_OFFSET_B_MASK 0x0000ffffUL +#define VPMPC_RMCM_3DLUT_OUT_OFFSET_B__VPMPC_RMCM_3DLUT_OUT_SCALE_B_MASK 0xffff0000UL + +// VPMPC_RMCM_GAMUT_REMAP_COEF_FORMAT +#define VPMPC_RMCM_GAMUT_REMAP_COEF_FORMAT__VPMPC_RMCM_GAMUT_REMAP_COEF_FORMAT_MASK 0x00000001UL + +// VPMPC_RMCM_GAMUT_REMAP_MODE +#define VPMPC_RMCM_GAMUT_REMAP_MODE__VPMPC_RMCM_GAMUT_REMAP_MODE_MASK 0x00000003UL +#define VPMPC_RMCM_GAMUT_REMAP_MODE__VPMPC_RMCM_GAMUT_REMAP_MODE_CURRENT_MASK 0x00000180UL + +// VPMPC_RMCM_GAMUT_REMAP_C11_C12_SETA +#define VPMPC_RMCM_GAMUT_REMAP_C11_C12_SETA__VPMPC_RMCM_GAMUT_REMAP_C11_SETA_MASK 0x0000ffffUL +#define VPMPC_RMCM_GAMUT_REMAP_C11_C12_SETA__VPMPC_RMCM_GAMUT_REMAP_C12_SETA_MASK 0xffff0000UL + +// VPMPC_RMCM_GAMUT_REMAP_C13_C14_SETA +#define VPMPC_RMCM_GAMUT_REMAP_C13_C14_SETA__VPMPC_RMCM_GAMUT_REMAP_C13_SETA_MASK 0x0000ffffUL +#define VPMPC_RMCM_GAMUT_REMAP_C13_C14_SETA__VPMPC_RMCM_GAMUT_REMAP_C14_SETA_MASK 0xffff0000UL + +// VPMPC_RMCM_GAMUT_REMAP_C21_C22_SETA +#define VPMPC_RMCM_GAMUT_REMAP_C21_C22_SETA__VPMPC_RMCM_GAMUT_REMAP_C21_SETA_MASK 0x0000ffffUL +#define VPMPC_RMCM_GAMUT_REMAP_C21_C22_SETA__VPMPC_RMCM_GAMUT_REMAP_C22_SETA_MASK 0xffff0000UL + +// VPMPC_RMCM_GAMUT_REMAP_C23_C24_SETA +#define VPMPC_RMCM_GAMUT_REMAP_C23_C24_SETA__VPMPC_RMCM_GAMUT_REMAP_C23_SETA_MASK 0x0000ffffUL +#define VPMPC_RMCM_GAMUT_REMAP_C23_C24_SETA__VPMPC_RMCM_GAMUT_REMAP_C24_SETA_MASK 0xffff0000UL + +// VPMPC_RMCM_GAMUT_REMAP_C31_C32_SETA +#define VPMPC_RMCM_GAMUT_REMAP_C31_C32_SETA__VPMPC_RMCM_GAMUT_REMAP_C31_SETA_MASK 0x0000ffffUL +#define VPMPC_RMCM_GAMUT_REMAP_C31_C32_SETA__VPMPC_RMCM_GAMUT_REMAP_C32_SETA_MASK 0xffff0000UL + +// VPMPC_RMCM_GAMUT_REMAP_C33_C34_SETA +#define VPMPC_RMCM_GAMUT_REMAP_C33_C34_SETA__VPMPC_RMCM_GAMUT_REMAP_C33_SETA_MASK 0x0000ffffUL +#define VPMPC_RMCM_GAMUT_REMAP_C33_C34_SETA__VPMPC_RMCM_GAMUT_REMAP_C34_SETA_MASK 0xffff0000UL + +// VPMPC_RMCM_MEM_PWR_CTRL +#define VPMPC_RMCM_MEM_PWR_CTRL__VPMPC_RMCM_SHAPER_MEM_PWR_FORCE_MASK 0x00000003UL +#define VPMPC_RMCM_MEM_PWR_CTRL__VPMPC_RMCM_SHAPER_MEM_PWR_DIS_MASK 0x00000004UL +#define VPMPC_RMCM_MEM_PWR_CTRL__VPMPC_RMCM_SHAPER_MEM_LOW_PWR_MODE_MASK 0x00000030UL +#define VPMPC_RMCM_MEM_PWR_CTRL__VPMPC_RMCM_3DLUT_MEM_PWR_FORCE_MASK 0x00000300UL +#define VPMPC_RMCM_MEM_PWR_CTRL__VPMPC_RMCM_3DLUT_MEM_PWR_DIS_MASK 0x00000400UL +#define VPMPC_RMCM_MEM_PWR_CTRL__VPMPC_RMCM_3DLUT_MEM_LOW_PWR_MODE_MASK 0x00003000UL +#define VPMPC_RMCM_MEM_PWR_CTRL__VPMPC_RMCM_SHAPER_MEM_PWR_STATE_MASK 0x03000000UL +#define VPMPC_RMCM_MEM_PWR_CTRL__VPMPC_RMCM_3DLUT_MEM_PWR_STATE_MASK 0x0c000000UL + +// VPMPC_RMCM_3DLUT_FAST_LOAD_SELECT +#define VPMPC_RMCM_3DLUT_FAST_LOAD_SELECT__VPMPC_RMCM_3DLUT_FL_SEL_MASK 0x0000000fUL + +// VPMPC_RMCM_CNTL +#define VPMPC_RMCM_CNTL__VPMPC_RMCM_CNTL_MASK 0x0000000fUL + +// VPFMT_CLAMP_COMPONENT_R +#define VPFMT_CLAMP_COMPONENT_R__VPFMT_CLAMP_LOWER_R_MASK 0x0000ffffUL +#define VPFMT_CLAMP_COMPONENT_R__VPFMT_CLAMP_UPPER_R_MASK 0xffff0000UL + +// VPFMT_CLAMP_COMPONENT_G +#define VPFMT_CLAMP_COMPONENT_G__VPFMT_CLAMP_LOWER_G_MASK 0x0000ffffUL +#define VPFMT_CLAMP_COMPONENT_G__VPFMT_CLAMP_UPPER_G_MASK 0xffff0000UL + +// VPFMT_CLAMP_COMPONENT_B +#define VPFMT_CLAMP_COMPONENT_B__VPFMT_CLAMP_LOWER_B_MASK 0x0000ffffUL +#define VPFMT_CLAMP_COMPONENT_B__VPFMT_CLAMP_UPPER_B_MASK 0xffff0000UL + +// VPFMT_DYNAMIC_EXP_CNTL +#define VPFMT_DYNAMIC_EXP_CNTL__VPFMT_DYNAMIC_EXP_EN_MASK 0x00000001UL +#define VPFMT_DYNAMIC_EXP_CNTL__VPFMT_DYNAMIC_EXP_MODE_MASK 0x00000010UL + +// VPFMT_CONTROL +#define VPFMT_CONTROL__VPFMT_PIXEL_ENCODING_MASK 0x00000003UL +#define VPFMT_CONTROL__VPFMT_CBCR_BIT_REDUCTION_BYPASS_MASK 0x00000010UL +#define VPFMT_CONTROL__VPFMT_SPATIAL_DITHER_FRAME_COUNTER_MAX_MASK 0x00000f00UL +#define VPFMT_CONTROL__VPFMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP_MASK 0x00003000UL +#define VPFMT_CONTROL__VPFMT_SUBSAMPLE_HTAPS_MASK 0x00030000UL +#define VPFMT_CONTROL__VPFMT_SUBSAMPLE_LEFT_EDGE_MASK 0x00040000UL +#define VPFMT_CONTROL__VPFMT_SUBSAMPLE_RIGHT_EDGE_MASK 0x00080000UL +#define VPFMT_CONTROL__VPFMT_SUBSAMPLE_VTAPS_MASK 0x00300000UL +#define VPFMT_CONTROL__VPFMT_SUBSAMPLE_TOP_EDGE_MASK 0x00400000UL +#define VPFMT_CONTROL__VPFMT_SUBSAMPLE_BOTTOM_EDGE_MASK 0x00800000UL +#define VPFMT_CONTROL__VPFMT_DOUBLE_BUFFER_REG_UPDATE_PENDING_MASK 0x01000000UL + +// VPFMT_BIT_DEPTH_CONTROL +#define VPFMT_BIT_DEPTH_CONTROL__VPFMT_TRUNCATE_EN_MASK 0x00000001UL +#define VPFMT_BIT_DEPTH_CONTROL__VPFMT_TRUNCATE_MODE_MASK 0x00000002UL +#define VPFMT_BIT_DEPTH_CONTROL__VPFMT_TRUNCATE_DEPTH_MASK 0x00000030UL +#define VPFMT_BIT_DEPTH_CONTROL__VPFMT_SPATIAL_DITHER_EN_MASK 0x00000100UL +#define VPFMT_BIT_DEPTH_CONTROL__VPFMT_SPATIAL_DITHER_MODE_MASK 0x00000600UL +#define VPFMT_BIT_DEPTH_CONTROL__VPFMT_SPATIAL_DITHER_DEPTH_MASK 0x00001800UL +#define VPFMT_BIT_DEPTH_CONTROL__VPFMT_FRAME_RANDOM_ENABLE_MASK 0x00002000UL +#define VPFMT_BIT_DEPTH_CONTROL__VPFMT_RGB_RANDOM_ENABLE_MASK 0x00004000UL +#define VPFMT_BIT_DEPTH_CONTROL__VPFMT_HIGHPASS_RANDOM_ENABLE_MASK 0x00008000UL + +// VPFMT_DITHER_RAND_R_SEED +#define VPFMT_DITHER_RAND_R_SEED__VPFMT_RAND_R_SEED_MASK 0x000000ffUL +#define VPFMT_DITHER_RAND_R_SEED__VPFMT_OFFSET_R_CR_MASK 0xffff0000UL + +// VPFMT_DITHER_RAND_G_SEED +#define VPFMT_DITHER_RAND_G_SEED__VPFMT_RAND_G_SEED_MASK 0x000000ffUL +#define VPFMT_DITHER_RAND_G_SEED__VPFMT_OFFSET_G_Y_MASK 0xffff0000UL + +// VPFMT_DITHER_RAND_B_SEED +#define VPFMT_DITHER_RAND_B_SEED__VPFMT_RAND_B_SEED_MASK 0x000000ffUL +#define VPFMT_DITHER_RAND_B_SEED__VPFMT_OFFSET_B_CB_MASK 0xffff0000UL + +// VPFMT_CLAMP_CNTL +#define VPFMT_CLAMP_CNTL__VPFMT_CLAMP_DATA_EN_MASK 0x00000001UL +#define VPFMT_CLAMP_CNTL__VPFMT_CLAMP_COLOR_FORMAT_MASK 0x00070000UL + +// VPFMT_SUBSAMPLER_MEMORY_CONTROL +#define VPFMT_SUBSAMPLER_MEMORY_CONTROL__VPFMT_SUBSAMPLER_MEM_PWR_FORCE_MASK 0x00000003UL +#define VPFMT_SUBSAMPLER_MEMORY_CONTROL__VPFMT_SUBSAMPLER_MEM_PWR_DIS_MASK 0x00000010UL +#define VPFMT_SUBSAMPLER_MEMORY_CONTROL__VPFMT_SUBSAMPLER_MEM_PWR_STATE_MASK 0x00000300UL +#define VPFMT_SUBSAMPLER_MEMORY_CONTROL__VPFMT_DEFAULT_MEM_LOW_POWER_STATE_MASK 0x00003000UL + +// VPOPP_PIPE_CONTROL +#define VPOPP_PIPE_CONTROL__VPOPP_PIPE_CLOCK_ON_MASK 0x00000002UL +#define VPOPP_PIPE_CONTROL__VPOPP_PIPE_DIGITAL_BYPASS_EN_MASK 0x00000010UL +#define VPOPP_PIPE_CONTROL__VPOPP_PIPE_ALPHA_SEL_MASK 0x00000020UL +#define VPOPP_PIPE_CONTROL__VPOPP_PIPE_ALPHA_MASK 0xffff0000UL + +// VPOPP_PIPE_OUTBG_EXT1 +#define VPOPP_PIPE_OUTBG_EXT1__OUTBG_EXT_TOP_MASK 0x00003fffUL +#define VPOPP_PIPE_OUTBG_EXT1__OUTBG_EXT_BOT_MASK 0x0fffc000UL + +// VPOPP_PIPE_OUTBG_EXT2 +#define VPOPP_PIPE_OUTBG_EXT2__OUTBG_EXT_LEFT_MASK 0x000007ffUL +#define VPOPP_PIPE_OUTBG_EXT2__OUTBG_EXT_RIGHT_MASK 0x003ff800UL + +// VPOPP_PIPE_OUTBG_COL1 +#define VPOPP_PIPE_OUTBG_COL1__OUTBG_R_CR_MASK 0x0000ffffUL +#define VPOPP_PIPE_OUTBG_COL1__OUTBG_B_CB_MASK 0xffff0000UL + +// VPOPP_PIPE_OUTBG_COL2 +#define VPOPP_PIPE_OUTBG_COL2__OUTBG_Y_MASK 0x0000ffffUL + +// VPOPP_TOP_CLK_CONTROL +#define VPOPP_TOP_CLK_CONTROL__VPOPP_VPECLK_R_GATE_DIS_MASK 0x00000001UL +#define VPOPP_TOP_CLK_CONTROL__VPOPP_VPECLK_G_GATE_DIS_MASK 0x00000002UL + +// VPOPP_CRC_CONTROL +#define VPOPP_CRC_CONTROL__VPOPP_CRC_EN_MASK 0x00000001UL +#define VPOPP_CRC_CONTROL__VPOPP_CRC_CONT_EN_MASK 0x00000002UL +#define VPOPP_CRC_CONTROL__VPOPP_CRC_PIXEL_SELECT_MASK 0x0000000cUL +#define VPOPP_CRC_CONTROL__VPOPP_CRC_SOURCE_SELECT_MASK 0x00000030UL +#define VPOPP_CRC_CONTROL__VPOPP_CRC_PIPE_SELECT_MASK 0x00000040UL +#define VPOPP_CRC_CONTROL__VPOPP_CRC_MASK_MASK 0x00ffff00UL +#define VPOPP_CRC_CONTROL__VPOPP_CRC_ONE_SHOT_PENDING_MASK 0x80000000UL + +// VPOPP_CRC_RESULT_RG +#define VPOPP_CRC_RESULT_RG__VPOPP_CRC_RESULT_R_MASK 0x0000ffffUL +#define VPOPP_CRC_RESULT_RG__VPOPP_CRC_RESULT_G_MASK 0xffff0000UL + +// VPOPP_CRC_RESULT_BC +#define VPOPP_CRC_RESULT_BC__VPOPP_CRC_RESULT_B_MASK 0x0000ffffUL +#define VPOPP_CRC_RESULT_BC__VPOPP_CRC_RESULT_C_MASK 0xffff0000UL + +// VPOPP_FROD_CONTROL +#define VPOPP_FROD_CONTROL__FROD_EN_MASK 0x00000001UL + +// VPOPP_FROD_MEM_PWR_CONTROL +#define VPOPP_FROD_MEM_PWR_CONTROL__FROD_MEM_PWR_FORCE_MASK 0x00000003UL +#define VPOPP_FROD_MEM_PWR_CONTROL__FROD_MEM_PWR_DIS_MASK 0x00000010UL +#define VPOPP_FROD_MEM_PWR_CONTROL__FROD_MEM_PWR_STATE_MASK 0x00000300UL +#define VPOPP_FROD_MEM_PWR_CONTROL__FROD_MEM_DEFAULT_LOW_PWR_STATE_MASK 0x00003000UL + +#endif diff --git a/src/amd/vpelib/src/chip/vpe22/inc/asic/chip_offset.h b/src/amd/vpelib/src/chip/vpe22/inc/asic/chip_offset.h new file mode 100644 index 00000000000..38db0f9b001 --- /dev/null +++ b/src/amd/vpelib/src/chip/vpe22/inc/asic/chip_offset.h @@ -0,0 +1,835 @@ +// Copyright (c) 1994 - 2025 Advanced Micro Devices, Inc. All rights reserved. + +/* + * chip_offset.h + * + * Register Spec Release: + * + * + * (c) 2021 Advanced Micro Devices, Inc. (unpublished) + * + * All rights reserved. This notice is intended as a precaution against + * inadvertent publication and does not imply publication or any waiver + * of confidentiality. The year included in the foregoing notice is the + * year of creation of the work. + * + */ + +#ifndef _vpe22_chip_OFFSET_HEADER +#define _vpe22_chip_OFFSET_HEADER + + +// Registers from CDC block + +#define mmVPEP_MGCG_CNTL 0x11E00 +#define mmVPCDC_SOFT_RESET 0x11E01 +#define mmVPCDC_FE0_SURFACE_CONFIG 0x11E02 +#define mmVPCDC_FE0_CROSSBAR_CONFIG 0x11E03 +#define mmVPCDC_FE0_VIEWPORT_START_CONFIG 0x11E04 +#define mmVPCDC_FE0_VIEWPORT_DIMENSION_CONFIG 0x11E05 +#define mmVPCDC_FE0_VIEWPORT_START_C_CONFIG 0x11E06 +#define mmVPCDC_FE0_VIEWPORT_DIMENSION_C_CONFIG 0x11E07 +#define mmVPCDC_FE1_SURFACE_CONFIG 0x11E08 +#define mmVPCDC_FE1_CROSSBAR_CONFIG 0x11E09 +#define mmVPCDC_FE1_VIEWPORT_START_CONFIG 0x11E0A +#define mmVPCDC_FE1_VIEWPORT_DIMENSION_CONFIG 0x11E0B +#define mmVPCDC_FE1_VIEWPORT_START_C_CONFIG 0x11E0C +#define mmVPCDC_FE1_VIEWPORT_DIMENSION_C_CONFIG 0x11E0D +#define mmVPCDC_BE0_P2B_CONFIG 0x11E0E +#define mmVPCDC_BE0_GLOBAL_SYNC_CONFIG 0x11E0F +#define mmVPCDC_BE1_P2B_CONFIG 0x11E10 +#define mmVPCDC_BE1_GLOBAL_SYNC_CONFIG 0x11E11 +#define mmVPCDC_BE2_P2B_CONFIG 0x11E12 +#define mmVPCDC_BE2_GLOBAL_SYNC_CONFIG 0x11E13 +#define mmVPCDC_BE3_P2B_CONFIG 0x11E14 +#define mmVPCDC_BE3_GLOBAL_SYNC_CONFIG 0x11E15 +#define mmVPCDC_GLOBAL_SYNC_TRIGGER 0x11E16 +#define mmVPEP_MEM_GLOBAL_PWR_REQ_CNTL 0x11E18 +#define mmVPFE0_MEM_PWR_CNTL 0x11E19 +#define mmVPFE1_MEM_PWR_CNTL 0x11E1A +#define mmVPBE0_MEM_PWR_CNTL 0x11E1B +#define mmVPBE1_MEM_PWR_CNTL 0x11E1C +#define mmVPBE2_MEM_PWR_CNTL 0x11E1D +#define mmVPBE3_MEM_PWR_CNTL 0x11E1E +#define mmVPCDC_3DLUT_FL_CONFIG 0x11E26 +#define mmVPCDC_CONTROL 0x11E27 + + +// Registers from VPCNVC_CFG block + +#define mmVPCNVC_CFG0_VPCNVC_SURFACE_PIXEL_FORMAT 0x11F44 +#define mmVPCNVC_CFG1_VPCNVC_SURFACE_PIXEL_FORMAT 0x120E0 +#define mmVPCNVC_CFG0_VPCNVC_FORMAT_CONTROL 0x11F45 +#define mmVPCNVC_CFG1_VPCNVC_FORMAT_CONTROL 0x120E1 +#define mmVPCNVC_CFG0_VPCNVC_FCNV_FP_BIAS_R 0x11F46 +#define mmVPCNVC_CFG1_VPCNVC_FCNV_FP_BIAS_R 0x120E2 +#define mmVPCNVC_CFG0_VPCNVC_FCNV_FP_BIAS_G 0x11F47 +#define mmVPCNVC_CFG1_VPCNVC_FCNV_FP_BIAS_G 0x120E3 +#define mmVPCNVC_CFG0_VPCNVC_FCNV_FP_BIAS_B 0x11F48 +#define mmVPCNVC_CFG1_VPCNVC_FCNV_FP_BIAS_B 0x120E4 +#define mmVPCNVC_CFG0_VPCNVC_FCNV_FP_SCALE_R 0x11F49 +#define mmVPCNVC_CFG1_VPCNVC_FCNV_FP_SCALE_R 0x120E5 +#define mmVPCNVC_CFG0_VPCNVC_FCNV_FP_SCALE_G 0x11F4A +#define mmVPCNVC_CFG1_VPCNVC_FCNV_FP_SCALE_G 0x120E6 +#define mmVPCNVC_CFG0_VPCNVC_FCNV_FP_SCALE_B 0x11F4B +#define mmVPCNVC_CFG1_VPCNVC_FCNV_FP_SCALE_B 0x120E7 +#define mmVPCNVC_CFG0_VPCNVC_COLOR_KEYER_CONTROL 0x11F4C +#define mmVPCNVC_CFG1_VPCNVC_COLOR_KEYER_CONTROL 0x120E8 +#define mmVPCNVC_CFG0_VPCNVC_COLOR_KEYER_ALPHA 0x11F4D +#define mmVPCNVC_CFG1_VPCNVC_COLOR_KEYER_ALPHA 0x120E9 +#define mmVPCNVC_CFG0_VPCNVC_COLOR_KEYER_RED 0x11F4E +#define mmVPCNVC_CFG1_VPCNVC_COLOR_KEYER_RED 0x120EA +#define mmVPCNVC_CFG0_VPCNVC_COLOR_KEYER_GREEN 0x11F4F +#define mmVPCNVC_CFG1_VPCNVC_COLOR_KEYER_GREEN 0x120EB +#define mmVPCNVC_CFG0_VPCNVC_COLOR_KEYER_BLUE 0x11F50 +#define mmVPCNVC_CFG1_VPCNVC_COLOR_KEYER_BLUE 0x120EC +#define mmVPCNVC_CFG0_VPCNVC_ALPHA_2BIT_LUT01 0x11F52 +#define mmVPCNVC_CFG1_VPCNVC_ALPHA_2BIT_LUT01 0x120EE +#define mmVPCNVC_CFG0_VPCNVC_ALPHA_2BIT_LUT23 0x11F53 +#define mmVPCNVC_CFG1_VPCNVC_ALPHA_2BIT_LUT23 0x120EF +#define mmVPCNVC_CFG0_VPCNVC_PRE_DEALPHA 0x11F54 +#define mmVPCNVC_CFG1_VPCNVC_PRE_DEALPHA 0x120F0 +#define mmVPCNVC_CFG0_VPCNVC_PRE_CSC_MODE 0x11F55 +#define mmVPCNVC_CFG1_VPCNVC_PRE_CSC_MODE 0x120F1 +#define mmVPCNVC_CFG0_VPCNVC_PRE_CSC_C11_C12 0x11F56 +#define mmVPCNVC_CFG1_VPCNVC_PRE_CSC_C11_C12 0x120F2 +#define mmVPCNVC_CFG0_VPCNVC_PRE_CSC_C13_C14 0x11F57 +#define mmVPCNVC_CFG1_VPCNVC_PRE_CSC_C13_C14 0x120F3 +#define mmVPCNVC_CFG0_VPCNVC_PRE_CSC_C21_C22 0x11F58 +#define mmVPCNVC_CFG1_VPCNVC_PRE_CSC_C21_C22 0x120F4 +#define mmVPCNVC_CFG0_VPCNVC_PRE_CSC_C23_C24 0x11F59 +#define mmVPCNVC_CFG1_VPCNVC_PRE_CSC_C23_C24 0x120F5 +#define mmVPCNVC_CFG0_VPCNVC_PRE_CSC_C31_C32 0x11F5A +#define mmVPCNVC_CFG1_VPCNVC_PRE_CSC_C31_C32 0x120F6 +#define mmVPCNVC_CFG0_VPCNVC_PRE_CSC_C33_C34 0x11F5B +#define mmVPCNVC_CFG1_VPCNVC_PRE_CSC_C33_C34 0x120F7 +#define mmVPCNVC_CFG0_VPCNVC_COEF_FORMAT 0x11F5C +#define mmVPCNVC_CFG1_VPCNVC_COEF_FORMAT 0x120F8 +#define mmVPCNVC_CFG0_VPCNVC_PRE_DEGAM 0x11F5D +#define mmVPCNVC_CFG1_VPCNVC_PRE_DEGAM 0x120F9 +#define mmVPCNVC_CFG0_VPCNVC_PRE_REALPHA 0x11F5E +#define mmVPCNVC_CFG1_VPCNVC_PRE_REALPHA 0x120FA + + +// Registers from VPDSCL block + +#define mmVPDSCL0_VPDSCL_COEF_RAM_TAP_SELECT 0x11F68 +#define mmVPDSCL1_VPDSCL_COEF_RAM_TAP_SELECT 0x12104 +#define mmVPDSCL0_VPDSCL_COEF_RAM_TAP_DATA 0x11F69 +#define mmVPDSCL1_VPDSCL_COEF_RAM_TAP_DATA 0x12105 +#define mmVPDSCL0_VPDSCL_MODE 0x11F6A +#define mmVPDSCL1_VPDSCL_MODE 0x12106 +#define mmVPDSCL0_VPDSCL_TAP_CONTROL 0x11F6B +#define mmVPDSCL1_VPDSCL_TAP_CONTROL 0x12107 +#define mmVPDSCL0_VPDSCL_CONTROL 0x11F6C +#define mmVPDSCL1_VPDSCL_CONTROL 0x12108 +#define mmVPDSCL0_VPDSCL_2TAP_CONTROL 0x11F6D +#define mmVPDSCL1_VPDSCL_2TAP_CONTROL 0x12109 +#define mmVPDSCL0_VPDSCL_MANUAL_REPLICATE_CONTROL 0x11F6E +#define mmVPDSCL1_VPDSCL_MANUAL_REPLICATE_CONTROL 0x1210A +#define mmVPDSCL0_VPDSCL_HORZ_FILTER_SCALE_RATIO 0x11F6F +#define mmVPDSCL1_VPDSCL_HORZ_FILTER_SCALE_RATIO 0x1210B +#define mmVPDSCL0_VPDSCL_HORZ_FILTER_INIT 0x11F70 +#define mmVPDSCL1_VPDSCL_HORZ_FILTER_INIT 0x1210C +#define mmVPDSCL0_VPDSCL_HORZ_FILTER_SCALE_RATIO_C 0x11F71 +#define mmVPDSCL1_VPDSCL_HORZ_FILTER_SCALE_RATIO_C 0x1210D +#define mmVPDSCL0_VPDSCL_HORZ_FILTER_INIT_C 0x11F72 +#define mmVPDSCL1_VPDSCL_HORZ_FILTER_INIT_C 0x1210E +#define mmVPDSCL0_VPDSCL_VERT_FILTER_SCALE_RATIO 0x11F73 +#define mmVPDSCL1_VPDSCL_VERT_FILTER_SCALE_RATIO 0x1210F +#define mmVPDSCL0_VPDSCL_VERT_FILTER_INIT 0x11F74 +#define mmVPDSCL1_VPDSCL_VERT_FILTER_INIT 0x12110 +#define mmVPDSCL0_VPDSCL_VERT_FILTER_INIT_BOT 0x11F75 +#define mmVPDSCL1_VPDSCL_VERT_FILTER_INIT_BOT 0x12111 +#define mmVPDSCL0_VPDSCL_VERT_FILTER_SCALE_RATIO_C 0x11F76 +#define mmVPDSCL1_VPDSCL_VERT_FILTER_SCALE_RATIO_C 0x12112 +#define mmVPDSCL0_VPDSCL_VERT_FILTER_INIT_C 0x11F77 +#define mmVPDSCL1_VPDSCL_VERT_FILTER_INIT_C 0x12113 +#define mmVPDSCL0_VPDSCL_VERT_FILTER_INIT_BOT_C 0x11F78 +#define mmVPDSCL1_VPDSCL_VERT_FILTER_INIT_BOT_C 0x12114 +#define mmVPDSCL0_VPDSCL_BLACK_COLOR 0x11F79 +#define mmVPDSCL1_VPDSCL_BLACK_COLOR 0x12115 +#define mmVPDSCL0_VPDSCL_UPDATE 0x11F7A +#define mmVPDSCL1_VPDSCL_UPDATE 0x12116 +#define mmVPDSCL0_VPDSCL_AUTOCAL 0x11F7B +#define mmVPDSCL1_VPDSCL_AUTOCAL 0x12117 +#define mmVPDSCL0_VPDSCL_EXT_OVERSCAN_LEFT_RIGHT 0x11F7C +#define mmVPDSCL1_VPDSCL_EXT_OVERSCAN_LEFT_RIGHT 0x12118 +#define mmVPDSCL0_VPDSCL_EXT_OVERSCAN_TOP_BOTTOM 0x11F7D +#define mmVPDSCL1_VPDSCL_EXT_OVERSCAN_TOP_BOTTOM 0x12119 +#define mmVPDSCL0_VPOTG_H_BLANK 0x11F7E +#define mmVPDSCL1_VPOTG_H_BLANK 0x1211A +#define mmVPDSCL0_VPOTG_V_BLANK 0x11F7F +#define mmVPDSCL1_VPOTG_V_BLANK 0x1211B +#define mmVPDSCL0_VPDSCL_RECOUT_START 0x11F80 +#define mmVPDSCL1_VPDSCL_RECOUT_START 0x1211C +#define mmVPDSCL0_VPDSCL_RECOUT_SIZE 0x11F81 +#define mmVPDSCL1_VPDSCL_RECOUT_SIZE 0x1211D +#define mmVPDSCL0_VPMPC_SIZE 0x11F82 +#define mmVPDSCL1_VPMPC_SIZE 0x1211E +#define mmVPDSCL0_VPLB_DATA_FORMAT 0x11F83 +#define mmVPDSCL1_VPLB_DATA_FORMAT 0x1211F +#define mmVPDSCL0_VPLB_MEMORY_CTRL 0x11F84 +#define mmVPDSCL1_VPLB_MEMORY_CTRL 0x12120 +#define mmVPDSCL0_VPLB_V_COUNTER 0x11F85 +#define mmVPDSCL1_VPLB_V_COUNTER 0x12121 +#define mmVPDSCL0_VPDSCL_MEM_PWR_CTRL 0x11F86 +#define mmVPDSCL1_VPDSCL_MEM_PWR_CTRL 0x12122 +#define mmVPDSCL0_VPDSCL_MEM_PWR_STATUS 0x11F87 +#define mmVPDSCL1_VPDSCL_MEM_PWR_STATUS 0x12123 +#define mmVPDSCL0_VPDSCL_EASF_H_MODE 0x11F88 +#define mmVPDSCL1_VPDSCL_EASF_H_MODE 0x12124 +#define mmVPDSCL0_VPDSCL_EASF_V_MODE 0x11F89 +#define mmVPDSCL1_VPDSCL_EASF_V_MODE 0x12125 +#define mmVPDSCL0_VPDSCL_SC_MODE 0x11F8A +#define mmVPDSCL1_VPDSCL_SC_MODE 0x12126 +#define mmVPDSCL0_VPDSCL_SC_MATRIX_C0C1 0x11F8B +#define mmVPDSCL1_VPDSCL_SC_MATRIX_C0C1 0x12127 +#define mmVPDSCL0_VPDSCL_SC_MATRIX_C2C3 0x11F8C +#define mmVPDSCL1_VPDSCL_SC_MATRIX_C2C3 0x12128 +#define mmVPDSCL0_VPDSCL_EASF_H_RINGEST_EVENTAP_GAIN 0x11F8D +#define mmVPDSCL1_VPDSCL_EASF_H_RINGEST_EVENTAP_GAIN 0x12129 +#define mmVPDSCL0_VPDSCL_EASF_H_RINGEST_EVENTAP_REDUCE 0x11F8E +#define mmVPDSCL1_VPDSCL_EASF_H_RINGEST_EVENTAP_REDUCE 0x1212A +#define mmVPDSCL0_VPDSCL_EASF_V_RINGEST_EVENTAP_GAIN 0x11F8F +#define mmVPDSCL1_VPDSCL_EASF_V_RINGEST_EVENTAP_GAIN 0x1212B +#define mmVPDSCL0_VPDSCL_EASF_V_RINGEST_EVENTAP_REDUCE 0x11F90 +#define mmVPDSCL1_VPDSCL_EASF_V_RINGEST_EVENTAP_REDUCE 0x1212C +#define mmVPDSCL0_VPDSCL_EASF_V_RINGEST_3TAP_CNTL1 0x11F91 +#define mmVPDSCL1_VPDSCL_EASF_V_RINGEST_3TAP_CNTL1 0x1212D +#define mmVPDSCL0_VPDSCL_EASF_V_RINGEST_3TAP_CNTL2 0x11F92 +#define mmVPDSCL1_VPDSCL_EASF_V_RINGEST_3TAP_CNTL2 0x1212E +#define mmVPDSCL0_VPDSCL_EASF_V_RINGEST_3TAP_CNTL3 0x11F93 +#define mmVPDSCL1_VPDSCL_EASF_V_RINGEST_3TAP_CNTL3 0x1212F +#define mmVPDSCL0_VPDSCL_EASF_RINGEST_FORCE 0x11F94 +#define mmVPDSCL1_VPDSCL_EASF_RINGEST_FORCE 0x12130 +#define mmVPDSCL0_VPDSCL_EASF_H_BF_CNTL 0x11F95 +#define mmVPDSCL1_VPDSCL_EASF_H_BF_CNTL 0x12131 +#define mmVPDSCL0_VPDSCL_EASF_H_BF_FINAL_MAX_MIN 0x11F96 +#define mmVPDSCL1_VPDSCL_EASF_H_BF_FINAL_MAX_MIN 0x12132 +#define mmVPDSCL0_VPDSCL_EASF_V_BF_CNTL 0x11F97 +#define mmVPDSCL1_VPDSCL_EASF_V_BF_CNTL 0x12133 +#define mmVPDSCL0_VPDSCL_EASF_V_BF_FINAL_MAX_MIN 0x11F98 +#define mmVPDSCL1_VPDSCL_EASF_V_BF_FINAL_MAX_MIN 0x12134 +#define mmVPDSCL0_VPDSCL_EASF_H_BF1_PWL_SEG0 0x11F99 +#define mmVPDSCL1_VPDSCL_EASF_H_BF1_PWL_SEG0 0x12135 +#define mmVPDSCL0_VPDSCL_EASF_H_BF1_PWL_SEG1 0x11F9A +#define mmVPDSCL1_VPDSCL_EASF_H_BF1_PWL_SEG1 0x12136 +#define mmVPDSCL0_VPDSCL_EASF_H_BF1_PWL_SEG2 0x11F9B +#define mmVPDSCL1_VPDSCL_EASF_H_BF1_PWL_SEG2 0x12137 +#define mmVPDSCL0_VPDSCL_EASF_H_BF1_PWL_SEG3 0x11F9C +#define mmVPDSCL1_VPDSCL_EASF_H_BF1_PWL_SEG3 0x12138 +#define mmVPDSCL0_VPDSCL_EASF_H_BF1_PWL_SEG4 0x11F9D +#define mmVPDSCL1_VPDSCL_EASF_H_BF1_PWL_SEG4 0x12139 +#define mmVPDSCL0_VPDSCL_EASF_H_BF1_PWL_SEG5 0x11F9E +#define mmVPDSCL1_VPDSCL_EASF_H_BF1_PWL_SEG5 0x1213A +#define mmVPDSCL0_VPDSCL_EASF_H_BF1_PWL_SEG6 0x11F9F +#define mmVPDSCL1_VPDSCL_EASF_H_BF1_PWL_SEG6 0x1213B +#define mmVPDSCL0_VPDSCL_EASF_H_BF1_PWL_SEG7 0x11FA0 +#define mmVPDSCL1_VPDSCL_EASF_H_BF1_PWL_SEG7 0x1213C +#define mmVPDSCL0_VPDSCL_EASF_V_BF1_PWL_SEG0 0x11FA1 +#define mmVPDSCL1_VPDSCL_EASF_V_BF1_PWL_SEG0 0x1213D +#define mmVPDSCL0_VPDSCL_EASF_V_BF1_PWL_SEG1 0x11FA2 +#define mmVPDSCL1_VPDSCL_EASF_V_BF1_PWL_SEG1 0x1213E +#define mmVPDSCL0_VPDSCL_EASF_V_BF1_PWL_SEG2 0x11FA3 +#define mmVPDSCL1_VPDSCL_EASF_V_BF1_PWL_SEG2 0x1213F +#define mmVPDSCL0_VPDSCL_EASF_V_BF1_PWL_SEG3 0x11FA4 +#define mmVPDSCL1_VPDSCL_EASF_V_BF1_PWL_SEG3 0x12140 +#define mmVPDSCL0_VPDSCL_EASF_V_BF1_PWL_SEG4 0x11FA5 +#define mmVPDSCL1_VPDSCL_EASF_V_BF1_PWL_SEG4 0x12141 +#define mmVPDSCL0_VPDSCL_EASF_V_BF1_PWL_SEG5 0x11FA6 +#define mmVPDSCL1_VPDSCL_EASF_V_BF1_PWL_SEG5 0x12142 +#define mmVPDSCL0_VPDSCL_EASF_V_BF1_PWL_SEG6 0x11FA7 +#define mmVPDSCL1_VPDSCL_EASF_V_BF1_PWL_SEG6 0x12143 +#define mmVPDSCL0_VPDSCL_EASF_V_BF1_PWL_SEG7 0x11FA8 +#define mmVPDSCL1_VPDSCL_EASF_V_BF1_PWL_SEG7 0x12144 +#define mmVPDSCL0_VPDSCL_EASF_H_BF3_PWL_SEG0 0x11FA9 +#define mmVPDSCL1_VPDSCL_EASF_H_BF3_PWL_SEG0 0x12145 +#define mmVPDSCL0_VPDSCL_EASF_H_BF3_PWL_SEG1 0x11FAA +#define mmVPDSCL1_VPDSCL_EASF_H_BF3_PWL_SEG1 0x12146 +#define mmVPDSCL0_VPDSCL_EASF_H_BF3_PWL_SEG2 0x11FAB +#define mmVPDSCL1_VPDSCL_EASF_H_BF3_PWL_SEG2 0x12147 +#define mmVPDSCL0_VPDSCL_EASF_H_BF3_PWL_SEG3 0x11FAC +#define mmVPDSCL1_VPDSCL_EASF_H_BF3_PWL_SEG3 0x12148 +#define mmVPDSCL0_VPDSCL_EASF_H_BF3_PWL_SEG4 0x11FAD +#define mmVPDSCL1_VPDSCL_EASF_H_BF3_PWL_SEG4 0x12149 +#define mmVPDSCL0_VPDSCL_EASF_H_BF3_PWL_SEG5 0x11FAE +#define mmVPDSCL1_VPDSCL_EASF_H_BF3_PWL_SEG5 0x1214A +#define mmVPDSCL0_VPDSCL_EASF_V_BF3_PWL_SEG0 0x11FAF +#define mmVPDSCL1_VPDSCL_EASF_V_BF3_PWL_SEG0 0x1214B +#define mmVPDSCL0_VPDSCL_EASF_V_BF3_PWL_SEG1 0x11FB0 +#define mmVPDSCL1_VPDSCL_EASF_V_BF3_PWL_SEG1 0x1214C +#define mmVPDSCL0_VPDSCL_EASF_V_BF3_PWL_SEG2 0x11FB1 +#define mmVPDSCL1_VPDSCL_EASF_V_BF3_PWL_SEG2 0x1214D +#define mmVPDSCL0_VPDSCL_EASF_V_BF3_PWL_SEG3 0x11FB2 +#define mmVPDSCL1_VPDSCL_EASF_V_BF3_PWL_SEG3 0x1214E +#define mmVPDSCL0_VPDSCL_EASF_V_BF3_PWL_SEG4 0x11FB3 +#define mmVPDSCL1_VPDSCL_EASF_V_BF3_PWL_SEG4 0x1214F +#define mmVPDSCL0_VPDSCL_EASF_V_BF3_PWL_SEG5 0x11FB4 +#define mmVPDSCL1_VPDSCL_EASF_V_BF3_PWL_SEG5 0x12150 +#define mmVPDSCL0_VPISHARP_MODE 0x11FB5 +#define mmVPDSCL1_VPISHARP_MODE 0x12151 +#define mmVPDSCL0_VPISHARP_DELTA_CTRL 0x11FB6 +#define mmVPDSCL1_VPISHARP_DELTA_CTRL 0x12152 +#define mmVPDSCL0_VPISHARP_DELTA_INDEX 0x11FB7 +#define mmVPDSCL1_VPISHARP_DELTA_INDEX 0x12153 +#define mmVPDSCL0_VPISHARP_DELTA_DATA 0x11FB8 +#define mmVPDSCL1_VPISHARP_DELTA_DATA 0x12154 +#define mmVPDSCL0_VPISHARP_NLDELTA_SOFT_CLIP 0x11FB9 +#define mmVPDSCL1_VPISHARP_NLDELTA_SOFT_CLIP 0x12155 +#define mmVPDSCL0_VPISHARP_NOISEDET_THRESHOLD 0x11FBA +#define mmVPDSCL1_VPISHARP_NOISEDET_THRESHOLD 0x12156 +#define mmVPDSCL0_VPISHARP_NOISE_GAIN_PWL 0x11FBB +#define mmVPDSCL1_VPISHARP_NOISE_GAIN_PWL 0x12157 +#define mmVPDSCL0_VPISHARP_LBA_PWL_SEG0 0x11FBC +#define mmVPDSCL1_VPISHARP_LBA_PWL_SEG0 0x12158 +#define mmVPDSCL0_VPISHARP_LBA_PWL_SEG1 0x11FBD +#define mmVPDSCL1_VPISHARP_LBA_PWL_SEG1 0x12159 +#define mmVPDSCL0_VPISHARP_LBA_PWL_SEG2 0x11FBE +#define mmVPDSCL1_VPISHARP_LBA_PWL_SEG2 0x1215A +#define mmVPDSCL0_VPISHARP_LBA_PWL_SEG3 0x11FBF +#define mmVPDSCL1_VPISHARP_LBA_PWL_SEG3 0x1215B +#define mmVPDSCL0_VPISHARP_LBA_PWL_SEG4 0x11FC0 +#define mmVPDSCL1_VPISHARP_LBA_PWL_SEG4 0x1215C +#define mmVPDSCL0_VPISHARP_LBA_PWL_SEG5 0x11FC1 +#define mmVPDSCL1_VPISHARP_LBA_PWL_SEG5 0x1215D +#define mmVPDSCL0_VPISHARP_DELTA_LUT_MEM_PWR_CTRL 0x11FC2 +#define mmVPDSCL1_VPISHARP_DELTA_LUT_MEM_PWR_CTRL 0x1215E + + +// Registers from VPCM block + +#define mmVPCM0_VPCM_CONTROL 0x1201C +#define mmVPCM1_VPCM_CONTROL 0x121B8 +#define mmVPCM0_VPCM_POST_CSC_CONTROL 0x1201D +#define mmVPCM1_VPCM_POST_CSC_CONTROL 0x121B9 +#define mmVPCM0_VPCM_POST_CSC_C11_C12 0x1201E +#define mmVPCM1_VPCM_POST_CSC_C11_C12 0x121BA +#define mmVPCM0_VPCM_POST_CSC_C13_C14 0x1201F +#define mmVPCM1_VPCM_POST_CSC_C13_C14 0x121BB +#define mmVPCM0_VPCM_POST_CSC_C21_C22 0x12020 +#define mmVPCM1_VPCM_POST_CSC_C21_C22 0x121BC +#define mmVPCM0_VPCM_POST_CSC_C23_C24 0x12021 +#define mmVPCM1_VPCM_POST_CSC_C23_C24 0x121BD +#define mmVPCM0_VPCM_POST_CSC_C31_C32 0x12022 +#define mmVPCM1_VPCM_POST_CSC_C31_C32 0x121BE +#define mmVPCM0_VPCM_POST_CSC_C33_C34 0x12023 +#define mmVPCM1_VPCM_POST_CSC_C33_C34 0x121BF +#define mmVPCM0_VPCM_BIAS_CR_R 0x12024 +#define mmVPCM1_VPCM_BIAS_CR_R 0x121C0 +#define mmVPCM0_VPCM_BIAS_Y_G_CB_B 0x12025 +#define mmVPCM1_VPCM_BIAS_Y_G_CB_B 0x121C1 +#define mmVPCM0_VPCM_GAMCOR_CONTROL 0x12026 +#define mmVPCM1_VPCM_GAMCOR_CONTROL 0x121C2 +#define mmVPCM0_VPCM_GAMCOR_LUT_INDEX 0x12027 +#define mmVPCM1_VPCM_GAMCOR_LUT_INDEX 0x121C3 +#define mmVPCM0_VPCM_GAMCOR_LUT_DATA 0x12028 +#define mmVPCM1_VPCM_GAMCOR_LUT_DATA 0x121C4 +#define mmVPCM0_VPCM_GAMCOR_LUT_CONTROL 0x12029 +#define mmVPCM1_VPCM_GAMCOR_LUT_CONTROL 0x121C5 +#define mmVPCM0_VPCM_GAMCOR_RAMA_START_CNTL_B 0x1202A +#define mmVPCM1_VPCM_GAMCOR_RAMA_START_CNTL_B 0x121C6 +#define mmVPCM0_VPCM_GAMCOR_RAMA_START_CNTL_G 0x1202B +#define mmVPCM1_VPCM_GAMCOR_RAMA_START_CNTL_G 0x121C7 +#define mmVPCM0_VPCM_GAMCOR_RAMA_START_CNTL_R 0x1202C +#define mmVPCM1_VPCM_GAMCOR_RAMA_START_CNTL_R 0x121C8 +#define mmVPCM0_VPCM_GAMCOR_RAMA_START_SLOPE_CNTL_B 0x1202D +#define mmVPCM1_VPCM_GAMCOR_RAMA_START_SLOPE_CNTL_B 0x121C9 +#define mmVPCM0_VPCM_GAMCOR_RAMA_START_SLOPE_CNTL_G 0x1202E +#define mmVPCM1_VPCM_GAMCOR_RAMA_START_SLOPE_CNTL_G 0x121CA +#define mmVPCM0_VPCM_GAMCOR_RAMA_START_SLOPE_CNTL_R 0x1202F +#define mmVPCM1_VPCM_GAMCOR_RAMA_START_SLOPE_CNTL_R 0x121CB +#define mmVPCM0_VPCM_GAMCOR_RAMA_START_BASE_CNTL_B 0x12030 +#define mmVPCM1_VPCM_GAMCOR_RAMA_START_BASE_CNTL_B 0x121CC +#define mmVPCM0_VPCM_GAMCOR_RAMA_START_BASE_CNTL_G 0x12031 +#define mmVPCM1_VPCM_GAMCOR_RAMA_START_BASE_CNTL_G 0x121CD +#define mmVPCM0_VPCM_GAMCOR_RAMA_START_BASE_CNTL_R 0x12032 +#define mmVPCM1_VPCM_GAMCOR_RAMA_START_BASE_CNTL_R 0x121CE +#define mmVPCM0_VPCM_GAMCOR_RAMA_END_CNTL1_B 0x12033 +#define mmVPCM1_VPCM_GAMCOR_RAMA_END_CNTL1_B 0x121CF +#define mmVPCM0_VPCM_GAMCOR_RAMA_END_CNTL2_B 0x12034 +#define mmVPCM1_VPCM_GAMCOR_RAMA_END_CNTL2_B 0x121D0 +#define mmVPCM0_VPCM_GAMCOR_RAMA_END_CNTL1_G 0x12035 +#define mmVPCM1_VPCM_GAMCOR_RAMA_END_CNTL1_G 0x121D1 +#define mmVPCM0_VPCM_GAMCOR_RAMA_END_CNTL2_G 0x12036 +#define mmVPCM1_VPCM_GAMCOR_RAMA_END_CNTL2_G 0x121D2 +#define mmVPCM0_VPCM_GAMCOR_RAMA_END_CNTL1_R 0x12037 +#define mmVPCM1_VPCM_GAMCOR_RAMA_END_CNTL1_R 0x121D3 +#define mmVPCM0_VPCM_GAMCOR_RAMA_END_CNTL2_R 0x12038 +#define mmVPCM1_VPCM_GAMCOR_RAMA_END_CNTL2_R 0x121D4 +#define mmVPCM0_VPCM_GAMCOR_RAMA_OFFSET_B 0x12039 +#define mmVPCM1_VPCM_GAMCOR_RAMA_OFFSET_B 0x121D5 +#define mmVPCM0_VPCM_GAMCOR_RAMA_OFFSET_G 0x1203A +#define mmVPCM1_VPCM_GAMCOR_RAMA_OFFSET_G 0x121D6 +#define mmVPCM0_VPCM_GAMCOR_RAMA_OFFSET_R 0x1203B +#define mmVPCM1_VPCM_GAMCOR_RAMA_OFFSET_R 0x121D7 +#define mmVPCM0_VPCM_GAMCOR_RAMA_REGION_0_1 0x1203C +#define mmVPCM1_VPCM_GAMCOR_RAMA_REGION_0_1 0x121D8 +#define mmVPCM0_VPCM_GAMCOR_RAMA_REGION_2_3 0x1203D +#define mmVPCM1_VPCM_GAMCOR_RAMA_REGION_2_3 0x121D9 +#define mmVPCM0_VPCM_GAMCOR_RAMA_REGION_4_5 0x1203E +#define mmVPCM1_VPCM_GAMCOR_RAMA_REGION_4_5 0x121DA +#define mmVPCM0_VPCM_GAMCOR_RAMA_REGION_6_7 0x1203F +#define mmVPCM1_VPCM_GAMCOR_RAMA_REGION_6_7 0x121DB +#define mmVPCM0_VPCM_GAMCOR_RAMA_REGION_8_9 0x12040 +#define mmVPCM1_VPCM_GAMCOR_RAMA_REGION_8_9 0x121DC +#define mmVPCM0_VPCM_GAMCOR_RAMA_REGION_10_11 0x12041 +#define mmVPCM1_VPCM_GAMCOR_RAMA_REGION_10_11 0x121DD +#define mmVPCM0_VPCM_GAMCOR_RAMA_REGION_12_13 0x12042 +#define mmVPCM1_VPCM_GAMCOR_RAMA_REGION_12_13 0x121DE +#define mmVPCM0_VPCM_GAMCOR_RAMA_REGION_14_15 0x12043 +#define mmVPCM1_VPCM_GAMCOR_RAMA_REGION_14_15 0x121DF +#define mmVPCM0_VPCM_GAMCOR_RAMA_REGION_16_17 0x12044 +#define mmVPCM1_VPCM_GAMCOR_RAMA_REGION_16_17 0x121E0 +#define mmVPCM0_VPCM_GAMCOR_RAMA_REGION_18_19 0x12045 +#define mmVPCM1_VPCM_GAMCOR_RAMA_REGION_18_19 0x121E1 +#define mmVPCM0_VPCM_GAMCOR_RAMA_REGION_20_21 0x12046 +#define mmVPCM1_VPCM_GAMCOR_RAMA_REGION_20_21 0x121E2 +#define mmVPCM0_VPCM_GAMCOR_RAMA_REGION_22_23 0x12047 +#define mmVPCM1_VPCM_GAMCOR_RAMA_REGION_22_23 0x121E3 +#define mmVPCM0_VPCM_GAMCOR_RAMA_REGION_24_25 0x12048 +#define mmVPCM1_VPCM_GAMCOR_RAMA_REGION_24_25 0x121E4 +#define mmVPCM0_VPCM_GAMCOR_RAMA_REGION_26_27 0x12049 +#define mmVPCM1_VPCM_GAMCOR_RAMA_REGION_26_27 0x121E5 +#define mmVPCM0_VPCM_GAMCOR_RAMA_REGION_28_29 0x1204A +#define mmVPCM1_VPCM_GAMCOR_RAMA_REGION_28_29 0x121E6 +#define mmVPCM0_VPCM_GAMCOR_RAMA_REGION_30_31 0x1204B +#define mmVPCM1_VPCM_GAMCOR_RAMA_REGION_30_31 0x121E7 +#define mmVPCM0_VPCM_GAMCOR_RAMA_REGION_32_33 0x1204C +#define mmVPCM1_VPCM_GAMCOR_RAMA_REGION_32_33 0x121E8 +#define mmVPCM0_VPCM_HDR_MULT_COEF 0x1204D +#define mmVPCM1_VPCM_HDR_MULT_COEF 0x121E9 +#define mmVPCM0_VPCM_MEM_PWR_CTRL 0x1204E +#define mmVPCM1_VPCM_MEM_PWR_CTRL 0x121EA +#define mmVPCM0_VPCM_MEM_PWR_STATUS 0x1204F +#define mmVPCM1_VPCM_MEM_PWR_STATUS 0x121EB +#define mmVPCM0_VPCM_DEALPHA 0x12051 +#define mmVPCM1_VPCM_DEALPHA 0x121ED +#define mmVPCM0_VPCM_COEF_FORMAT 0x12052 +#define mmVPCM1_VPCM_COEF_FORMAT 0x121EE +#define mmVPCM0_VPCM_HIST_CNTL 0x12055 +#define mmVPCM1_VPCM_HIST_CNTL 0x121F1 +#define mmVPCM0_VPCM_HIST_SCALE_SRC1 0x12056 +#define mmVPCM1_VPCM_HIST_SCALE_SRC1 0x121F2 +#define mmVPCM0_VPCM_HIST_COEFA_SRC2 0x12057 +#define mmVPCM1_VPCM_HIST_COEFA_SRC2 0x121F3 +#define mmVPCM0_VPCM_HIST_COEFB_SRC2 0x12058 +#define mmVPCM1_VPCM_HIST_COEFB_SRC2 0x121F4 +#define mmVPCM0_VPCM_HIST_COEFC_SRC2 0x12059 +#define mmVPCM1_VPCM_HIST_COEFC_SRC2 0x121F5 +#define mmVPCM0_VPCM_HIST_SCALE_SRC3 0x1205A +#define mmVPCM1_VPCM_HIST_SCALE_SRC3 0x121F6 +#define mmVPCM0_VPCM_HIST_BIAS_SRC1 0x1205B +#define mmVPCM1_VPCM_HIST_BIAS_SRC1 0x121F7 +#define mmVPCM0_VPCM_HIST_BIAS_SRC2 0x1205C +#define mmVPCM1_VPCM_HIST_BIAS_SRC2 0x121F8 +#define mmVPCM0_VPCM_HIST_BIAS_SRC3 0x1205D +#define mmVPCM1_VPCM_HIST_BIAS_SRC3 0x121F9 + + +// Registers from VPDPP_TOP block + +#define mmVPDPP_TOP0_VPDPP_CONTROL 0x11F38 +#define mmVPDPP_TOP1_VPDPP_CONTROL 0x120D4 +#define mmVPDPP_TOP0_VPDPP_CRC_CTRL 0x11F3C +#define mmVPDPP_TOP1_VPDPP_CRC_CTRL 0x120D8 + + +// Registers from VPMPC_CFG block + +#define mmVPMPC_CLOCK_CONTROL 0x12768 +#define mmVPMPC_SOFT_RESET 0x12769 +#define mmVPMPC_CRC_CTRL 0x1276A +#define mmVPMPC_CRC_SEL_CONTROL 0x1276B +#define mmVPMPC_CRC_RESULT_AR 0x1276C +#define mmVPMPC_CRC_RESULT_GB 0x1276D +#define mmVPMPC_CRC_RESULT_C 0x1276E +#define mmVPMPC_BYPASS_BG_AR 0x12771 +#define mmVPMPC_BYPASS_BG_GB 0x12772 +#define mmVPMPC_HOST_READ_CONTROL 0x12773 +#define mmVPMPC_PENDING_STATUS_MISC 0x12774 +#define mmVPMPC_VPCDC0_3DLUT_FL_CONFIG 0x12775 +#define mmVPMPC_VPCDC0_3DLUT_FL_BIAS_SCALE 0x12776 + + +// Registers from VPMPC_OCSC block + +#define mmVPMPC_OUT0_MUX 0x12789 +#define mmVPMPC_OUT0_FLOAT_CONTROL 0x1278A +#define mmVPMPC_OUT0_DENORM_CONTROL 0x1278B +#define mmVPMPC_OUT0_DENORM_CLAMP_G_Y 0x1278C +#define mmVPMPC_OUT0_DENORM_CLAMP_B_CB 0x1278D +#define mmVPMPC_OUT1_MUX 0x1278E +#define mmVPMPC_OUT1_FLOAT_CONTROL 0x1278F +#define mmVPMPC_OUT1_DENORM_CONTROL 0x12790 +#define mmVPMPC_OUT1_DENORM_CLAMP_G_Y 0x12791 +#define mmVPMPC_OUT1_DENORM_CLAMP_B_CB 0x12792 +#define mmVPMPC_OUT_CSC_COEF_FORMAT 0x1279D +#define mmVPMPC_OUT0_CSC_MODE 0x1279E +#define mmVPMPC_OUT0_CSC_C11_C12_A 0x1279F +#define mmVPMPC_OUT0_CSC_C13_C14_A 0x127A0 +#define mmVPMPC_OUT0_CSC_C21_C22_A 0x127A1 +#define mmVPMPC_OUT0_CSC_C23_C24_A 0x127A2 +#define mmVPMPC_OUT0_CSC_C31_C32_A 0x127A3 +#define mmVPMPC_OUT0_CSC_C33_C34_A 0x127A4 +#define mmVPMPC_OUT1_CSC_MODE 0x127A5 +#define mmVPMPC_OUT1_CSC_C11_C12_A 0x127A6 +#define mmVPMPC_OUT1_CSC_C13_C14_A 0x127A7 +#define mmVPMPC_OUT1_CSC_C21_C22_A 0x127A8 +#define mmVPMPC_OUT1_CSC_C23_C24_A 0x127A9 +#define mmVPMPC_OUT1_CSC_C31_C32_A 0x127AA +#define mmVPMPC_OUT1_CSC_C33_C34_A 0x127AB + + +// Registers from VPMPCC block + +#define mmVPMPCC0_VPMPCC_TOP_SEL 0x125C0 +#define mmVPMPCC1_VPMPCC_TOP_SEL 0x125D5 +#define mmVPMPCC0_VPMPCC_BOT_SEL 0x125C1 +#define mmVPMPCC1_VPMPCC_BOT_SEL 0x125D6 +#define mmVPMPCC0_VPMPCC_VPOPP_ID 0x125C2 +#define mmVPMPCC1_VPMPCC_VPOPP_ID 0x125D7 +#define mmVPMPCC0_VPMPCC_CONTROL 0x125C3 +#define mmVPMPCC1_VPMPCC_CONTROL 0x125D8 +#define mmVPMPCC0_VPMPCC_CONTROL2 0x125C4 +#define mmVPMPCC1_VPMPCC_CONTROL2 0x125D9 +#define mmVPMPCC0_VPMPCC_TOP_GAIN 0x125C5 +#define mmVPMPCC1_VPMPCC_TOP_GAIN 0x125DA +#define mmVPMPCC0_VPMPCC_BOT_GAIN_INSIDE 0x125C6 +#define mmVPMPCC1_VPMPCC_BOT_GAIN_INSIDE 0x125DB +#define mmVPMPCC0_VPMPCC_BOT_GAIN_OUTSIDE 0x125C7 +#define mmVPMPCC1_VPMPCC_BOT_GAIN_OUTSIDE 0x125DC +#define mmVPMPCC0_VPMPCC_MOVABLE_CM_LOCATION_CONTROL 0x125C8 +#define mmVPMPCC1_VPMPCC_MOVABLE_CM_LOCATION_CONTROL 0x125DD +#define mmVPMPCC0_VPMPCC_BG_R_CR 0x125C9 +#define mmVPMPCC1_VPMPCC_BG_R_CR 0x125DE +#define mmVPMPCC0_VPMPCC_BG_G_Y 0x125CA +#define mmVPMPCC1_VPMPCC_BG_G_Y 0x125DF +#define mmVPMPCC0_VPMPCC_BG_B_CB 0x125CB +#define mmVPMPCC1_VPMPCC_BG_B_CB 0x125E0 +#define mmVPMPCC0_VPMPCC_MEM_PWR_CTRL 0x125CC +#define mmVPMPCC1_VPMPCC_MEM_PWR_CTRL 0x125E1 +#define mmVPMPCC0_VPMPCC_STATUS 0x125CD +#define mmVPMPCC1_VPMPCC_STATUS 0x125E2 + + +// Registers from VPMPCC_OGAM block + +#define mmVPMPCC_OGAM0_VPMPCC_OGAM_CONTROL 0x12614 +#define mmVPMPCC_OGAM1_VPMPCC_OGAM_CONTROL 0x1264B +#define mmVPMPCC_OGAM0_VPMPCC_OGAM_LUT_INDEX 0x12615 +#define mmVPMPCC_OGAM1_VPMPCC_OGAM_LUT_INDEX 0x1264C +#define mmVPMPCC_OGAM0_VPMPCC_OGAM_LUT_DATA 0x12616 +#define mmVPMPCC_OGAM1_VPMPCC_OGAM_LUT_DATA 0x1264D +#define mmVPMPCC_OGAM0_VPMPCC_OGAM_LUT_CONTROL 0x12617 +#define mmVPMPCC_OGAM1_VPMPCC_OGAM_LUT_CONTROL 0x1264E +#define mmVPMPCC_OGAM0_VPMPCC_OGAM_RAMA_START_CNTL_B 0x12618 +#define mmVPMPCC_OGAM1_VPMPCC_OGAM_RAMA_START_CNTL_B 0x1264F +#define mmVPMPCC_OGAM0_VPMPCC_OGAM_RAMA_START_CNTL_G 0x12619 +#define mmVPMPCC_OGAM1_VPMPCC_OGAM_RAMA_START_CNTL_G 0x12650 +#define mmVPMPCC_OGAM0_VPMPCC_OGAM_RAMA_START_CNTL_R 0x1261A +#define mmVPMPCC_OGAM1_VPMPCC_OGAM_RAMA_START_CNTL_R 0x12651 +#define mmVPMPCC_OGAM0_VPMPCC_OGAM_RAMA_START_SLOPE_CNTL_B 0x1261B +#define mmVPMPCC_OGAM1_VPMPCC_OGAM_RAMA_START_SLOPE_CNTL_B 0x12652 +#define mmVPMPCC_OGAM0_VPMPCC_OGAM_RAMA_START_SLOPE_CNTL_G 0x1261C +#define mmVPMPCC_OGAM1_VPMPCC_OGAM_RAMA_START_SLOPE_CNTL_G 0x12653 +#define mmVPMPCC_OGAM0_VPMPCC_OGAM_RAMA_START_SLOPE_CNTL_R 0x1261D +#define mmVPMPCC_OGAM1_VPMPCC_OGAM_RAMA_START_SLOPE_CNTL_R 0x12654 +#define mmVPMPCC_OGAM0_VPMPCC_OGAM_RAMA_START_BASE_CNTL_B 0x1261E +#define mmVPMPCC_OGAM1_VPMPCC_OGAM_RAMA_START_BASE_CNTL_B 0x12655 +#define mmVPMPCC_OGAM0_VPMPCC_OGAM_RAMA_START_BASE_CNTL_G 0x1261F +#define mmVPMPCC_OGAM1_VPMPCC_OGAM_RAMA_START_BASE_CNTL_G 0x12656 +#define mmVPMPCC_OGAM0_VPMPCC_OGAM_RAMA_START_BASE_CNTL_R 0x12620 +#define mmVPMPCC_OGAM1_VPMPCC_OGAM_RAMA_START_BASE_CNTL_R 0x12657 +#define mmVPMPCC_OGAM0_VPMPCC_OGAM_RAMA_END_CNTL1_B 0x12621 +#define mmVPMPCC_OGAM1_VPMPCC_OGAM_RAMA_END_CNTL1_B 0x12658 +#define mmVPMPCC_OGAM0_VPMPCC_OGAM_RAMA_END_CNTL2_B 0x12622 +#define mmVPMPCC_OGAM1_VPMPCC_OGAM_RAMA_END_CNTL2_B 0x12659 +#define mmVPMPCC_OGAM0_VPMPCC_OGAM_RAMA_END_CNTL1_G 0x12623 +#define mmVPMPCC_OGAM1_VPMPCC_OGAM_RAMA_END_CNTL1_G 0x1265A +#define mmVPMPCC_OGAM0_VPMPCC_OGAM_RAMA_END_CNTL2_G 0x12624 +#define mmVPMPCC_OGAM1_VPMPCC_OGAM_RAMA_END_CNTL2_G 0x1265B +#define mmVPMPCC_OGAM0_VPMPCC_OGAM_RAMA_END_CNTL1_R 0x12625 +#define mmVPMPCC_OGAM1_VPMPCC_OGAM_RAMA_END_CNTL1_R 0x1265C +#define mmVPMPCC_OGAM0_VPMPCC_OGAM_RAMA_END_CNTL2_R 0x12626 +#define mmVPMPCC_OGAM1_VPMPCC_OGAM_RAMA_END_CNTL2_R 0x1265D +#define mmVPMPCC_OGAM0_VPMPCC_OGAM_RAMA_OFFSET_B 0x12627 +#define mmVPMPCC_OGAM1_VPMPCC_OGAM_RAMA_OFFSET_B 0x1265E +#define mmVPMPCC_OGAM0_VPMPCC_OGAM_RAMA_OFFSET_G 0x12628 +#define mmVPMPCC_OGAM1_VPMPCC_OGAM_RAMA_OFFSET_G 0x1265F +#define mmVPMPCC_OGAM0_VPMPCC_OGAM_RAMA_OFFSET_R 0x12629 +#define mmVPMPCC_OGAM1_VPMPCC_OGAM_RAMA_OFFSET_R 0x12660 +#define mmVPMPCC_OGAM0_VPMPCC_OGAM_RAMA_REGION_0_1 0x1262A +#define mmVPMPCC_OGAM1_VPMPCC_OGAM_RAMA_REGION_0_1 0x12661 +#define mmVPMPCC_OGAM0_VPMPCC_OGAM_RAMA_REGION_2_3 0x1262B +#define mmVPMPCC_OGAM1_VPMPCC_OGAM_RAMA_REGION_2_3 0x12662 +#define mmVPMPCC_OGAM0_VPMPCC_OGAM_RAMA_REGION_4_5 0x1262C +#define mmVPMPCC_OGAM1_VPMPCC_OGAM_RAMA_REGION_4_5 0x12663 +#define mmVPMPCC_OGAM0_VPMPCC_OGAM_RAMA_REGION_6_7 0x1262D +#define mmVPMPCC_OGAM1_VPMPCC_OGAM_RAMA_REGION_6_7 0x12664 +#define mmVPMPCC_OGAM0_VPMPCC_OGAM_RAMA_REGION_8_9 0x1262E +#define mmVPMPCC_OGAM1_VPMPCC_OGAM_RAMA_REGION_8_9 0x12665 +#define mmVPMPCC_OGAM0_VPMPCC_OGAM_RAMA_REGION_10_11 0x1262F +#define mmVPMPCC_OGAM1_VPMPCC_OGAM_RAMA_REGION_10_11 0x12666 +#define mmVPMPCC_OGAM0_VPMPCC_OGAM_RAMA_REGION_12_13 0x12630 +#define mmVPMPCC_OGAM1_VPMPCC_OGAM_RAMA_REGION_12_13 0x12667 +#define mmVPMPCC_OGAM0_VPMPCC_OGAM_RAMA_REGION_14_15 0x12631 +#define mmVPMPCC_OGAM1_VPMPCC_OGAM_RAMA_REGION_14_15 0x12668 +#define mmVPMPCC_OGAM0_VPMPCC_OGAM_RAMA_REGION_16_17 0x12632 +#define mmVPMPCC_OGAM1_VPMPCC_OGAM_RAMA_REGION_16_17 0x12669 +#define mmVPMPCC_OGAM0_VPMPCC_OGAM_RAMA_REGION_18_19 0x12633 +#define mmVPMPCC_OGAM1_VPMPCC_OGAM_RAMA_REGION_18_19 0x1266A +#define mmVPMPCC_OGAM0_VPMPCC_OGAM_RAMA_REGION_20_21 0x12634 +#define mmVPMPCC_OGAM1_VPMPCC_OGAM_RAMA_REGION_20_21 0x1266B +#define mmVPMPCC_OGAM0_VPMPCC_OGAM_RAMA_REGION_22_23 0x12635 +#define mmVPMPCC_OGAM1_VPMPCC_OGAM_RAMA_REGION_22_23 0x1266C +#define mmVPMPCC_OGAM0_VPMPCC_OGAM_RAMA_REGION_24_25 0x12636 +#define mmVPMPCC_OGAM1_VPMPCC_OGAM_RAMA_REGION_24_25 0x1266D +#define mmVPMPCC_OGAM0_VPMPCC_OGAM_RAMA_REGION_26_27 0x12637 +#define mmVPMPCC_OGAM1_VPMPCC_OGAM_RAMA_REGION_26_27 0x1266E +#define mmVPMPCC_OGAM0_VPMPCC_OGAM_RAMA_REGION_28_29 0x12638 +#define mmVPMPCC_OGAM1_VPMPCC_OGAM_RAMA_REGION_28_29 0x1266F +#define mmVPMPCC_OGAM0_VPMPCC_OGAM_RAMA_REGION_30_31 0x12639 +#define mmVPMPCC_OGAM1_VPMPCC_OGAM_RAMA_REGION_30_31 0x12670 +#define mmVPMPCC_OGAM0_VPMPCC_OGAM_RAMA_REGION_32_33 0x1263A +#define mmVPMPCC_OGAM1_VPMPCC_OGAM_RAMA_REGION_32_33 0x12671 +#define mmVPMPCC_OGAM0_VPMPCC_GAMUT_REMAP_COEF_FORMAT 0x1263B +#define mmVPMPCC_OGAM1_VPMPCC_GAMUT_REMAP_COEF_FORMAT 0x12672 +#define mmVPMPCC_OGAM0_VPMPCC_GAMUT_REMAP_MODE 0x1263C +#define mmVPMPCC_OGAM1_VPMPCC_GAMUT_REMAP_MODE 0x12673 +#define mmVPMPCC_OGAM0_VPMPC_GAMUT_REMAP_C11_C12_A 0x1263D +#define mmVPMPCC_OGAM1_VPMPC_GAMUT_REMAP_C11_C12_A 0x12674 +#define mmVPMPCC_OGAM0_VPMPC_GAMUT_REMAP_C13_C14_A 0x1263E +#define mmVPMPCC_OGAM1_VPMPC_GAMUT_REMAP_C13_C14_A 0x12675 +#define mmVPMPCC_OGAM0_VPMPC_GAMUT_REMAP_C21_C22_A 0x1263F +#define mmVPMPCC_OGAM1_VPMPC_GAMUT_REMAP_C21_C22_A 0x12676 +#define mmVPMPCC_OGAM0_VPMPC_GAMUT_REMAP_C23_C24_A 0x12640 +#define mmVPMPCC_OGAM1_VPMPC_GAMUT_REMAP_C23_C24_A 0x12677 +#define mmVPMPCC_OGAM0_VPMPC_GAMUT_REMAP_C31_C32_A 0x12641 +#define mmVPMPCC_OGAM1_VPMPC_GAMUT_REMAP_C31_C32_A 0x12678 +#define mmVPMPCC_OGAM0_VPMPC_GAMUT_REMAP_C33_C34_A 0x12642 +#define mmVPMPCC_OGAM1_VPMPC_GAMUT_REMAP_C33_C34_A 0x12679 + + +// Registers from VPMPCC_MCM block + +#define mmVPMPCC_MCM0_VPMPCC_MCM_1DLUT_CONTROL 0x12882 +#define mmVPMPCC_MCM1_VPMPCC_MCM_1DLUT_CONTROL 0x12912 +#define mmVPMPCC_MCM0_VPMPCC_MCM_1DLUT_LUT_INDEX 0x12883 +#define mmVPMPCC_MCM1_VPMPCC_MCM_1DLUT_LUT_INDEX 0x12913 +#define mmVPMPCC_MCM0_VPMPCC_MCM_1DLUT_LUT_DATA 0x12884 +#define mmVPMPCC_MCM1_VPMPCC_MCM_1DLUT_LUT_DATA 0x12914 +#define mmVPMPCC_MCM0_VPMPCC_MCM_1DLUT_LUT_CONTROL 0x12885 +#define mmVPMPCC_MCM1_VPMPCC_MCM_1DLUT_LUT_CONTROL 0x12915 +#define mmVPMPCC_MCM0_VPMPCC_MCM_1DLUT_RAMA_START_CNTL_B 0x12886 +#define mmVPMPCC_MCM1_VPMPCC_MCM_1DLUT_RAMA_START_CNTL_B 0x12916 +#define mmVPMPCC_MCM0_VPMPCC_MCM_1DLUT_RAMA_START_CNTL_G 0x12887 +#define mmVPMPCC_MCM1_VPMPCC_MCM_1DLUT_RAMA_START_CNTL_G 0x12917 +#define mmVPMPCC_MCM0_VPMPCC_MCM_1DLUT_RAMA_START_CNTL_R 0x12888 +#define mmVPMPCC_MCM1_VPMPCC_MCM_1DLUT_RAMA_START_CNTL_R 0x12918 +#define mmVPMPCC_MCM0_VPMPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_B 0x12889 +#define mmVPMPCC_MCM1_VPMPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_B 0x12919 +#define mmVPMPCC_MCM0_VPMPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_G 0x1288A +#define mmVPMPCC_MCM1_VPMPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_G 0x1291A +#define mmVPMPCC_MCM0_VPMPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_R 0x1288B +#define mmVPMPCC_MCM1_VPMPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_R 0x1291B +#define mmVPMPCC_MCM0_VPMPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_B 0x1288C +#define mmVPMPCC_MCM1_VPMPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_B 0x1291C +#define mmVPMPCC_MCM0_VPMPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_G 0x1288D +#define mmVPMPCC_MCM1_VPMPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_G 0x1291D +#define mmVPMPCC_MCM0_VPMPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_R 0x1288E +#define mmVPMPCC_MCM1_VPMPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_R 0x1291E +#define mmVPMPCC_MCM0_VPMPCC_MCM_1DLUT_RAMA_END_CNTL1_B 0x1288F +#define mmVPMPCC_MCM1_VPMPCC_MCM_1DLUT_RAMA_END_CNTL1_B 0x1291F +#define mmVPMPCC_MCM0_VPMPCC_MCM_1DLUT_RAMA_END_CNTL2_B 0x12890 +#define mmVPMPCC_MCM1_VPMPCC_MCM_1DLUT_RAMA_END_CNTL2_B 0x12920 +#define mmVPMPCC_MCM0_VPMPCC_MCM_1DLUT_RAMA_END_CNTL1_G 0x12891 +#define mmVPMPCC_MCM1_VPMPCC_MCM_1DLUT_RAMA_END_CNTL1_G 0x12921 +#define mmVPMPCC_MCM0_VPMPCC_MCM_1DLUT_RAMA_END_CNTL2_G 0x12892 +#define mmVPMPCC_MCM1_VPMPCC_MCM_1DLUT_RAMA_END_CNTL2_G 0x12922 +#define mmVPMPCC_MCM0_VPMPCC_MCM_1DLUT_RAMA_END_CNTL1_R 0x12893 +#define mmVPMPCC_MCM1_VPMPCC_MCM_1DLUT_RAMA_END_CNTL1_R 0x12923 +#define mmVPMPCC_MCM0_VPMPCC_MCM_1DLUT_RAMA_END_CNTL2_R 0x12894 +#define mmVPMPCC_MCM1_VPMPCC_MCM_1DLUT_RAMA_END_CNTL2_R 0x12924 +#define mmVPMPCC_MCM0_VPMPCC_MCM_1DLUT_RAMA_OFFSET_B 0x12895 +#define mmVPMPCC_MCM1_VPMPCC_MCM_1DLUT_RAMA_OFFSET_B 0x12925 +#define mmVPMPCC_MCM0_VPMPCC_MCM_1DLUT_RAMA_OFFSET_G 0x12896 +#define mmVPMPCC_MCM1_VPMPCC_MCM_1DLUT_RAMA_OFFSET_G 0x12926 +#define mmVPMPCC_MCM0_VPMPCC_MCM_1DLUT_RAMA_OFFSET_R 0x12897 +#define mmVPMPCC_MCM1_VPMPCC_MCM_1DLUT_RAMA_OFFSET_R 0x12927 +#define mmVPMPCC_MCM0_VPMPCC_MCM_1DLUT_RAMA_REGION_0_1 0x12898 +#define mmVPMPCC_MCM1_VPMPCC_MCM_1DLUT_RAMA_REGION_0_1 0x12928 +#define mmVPMPCC_MCM0_VPMPCC_MCM_1DLUT_RAMA_REGION_2_3 0x12899 +#define mmVPMPCC_MCM1_VPMPCC_MCM_1DLUT_RAMA_REGION_2_3 0x12929 +#define mmVPMPCC_MCM0_VPMPCC_MCM_1DLUT_RAMA_REGION_4_5 0x1289A +#define mmVPMPCC_MCM1_VPMPCC_MCM_1DLUT_RAMA_REGION_4_5 0x1292A +#define mmVPMPCC_MCM0_VPMPCC_MCM_1DLUT_RAMA_REGION_6_7 0x1289B +#define mmVPMPCC_MCM1_VPMPCC_MCM_1DLUT_RAMA_REGION_6_7 0x1292B +#define mmVPMPCC_MCM0_VPMPCC_MCM_1DLUT_RAMA_REGION_8_9 0x1289C +#define mmVPMPCC_MCM1_VPMPCC_MCM_1DLUT_RAMA_REGION_8_9 0x1292C +#define mmVPMPCC_MCM0_VPMPCC_MCM_1DLUT_RAMA_REGION_10_11 0x1289D +#define mmVPMPCC_MCM1_VPMPCC_MCM_1DLUT_RAMA_REGION_10_11 0x1292D +#define mmVPMPCC_MCM0_VPMPCC_MCM_1DLUT_RAMA_REGION_12_13 0x1289E +#define mmVPMPCC_MCM1_VPMPCC_MCM_1DLUT_RAMA_REGION_12_13 0x1292E +#define mmVPMPCC_MCM0_VPMPCC_MCM_1DLUT_RAMA_REGION_14_15 0x1289F +#define mmVPMPCC_MCM1_VPMPCC_MCM_1DLUT_RAMA_REGION_14_15 0x1292F +#define mmVPMPCC_MCM0_VPMPCC_MCM_1DLUT_RAMA_REGION_16_17 0x128A0 +#define mmVPMPCC_MCM1_VPMPCC_MCM_1DLUT_RAMA_REGION_16_17 0x12930 +#define mmVPMPCC_MCM0_VPMPCC_MCM_1DLUT_RAMA_REGION_18_19 0x128A1 +#define mmVPMPCC_MCM1_VPMPCC_MCM_1DLUT_RAMA_REGION_18_19 0x12931 +#define mmVPMPCC_MCM0_VPMPCC_MCM_1DLUT_RAMA_REGION_20_21 0x128A2 +#define mmVPMPCC_MCM1_VPMPCC_MCM_1DLUT_RAMA_REGION_20_21 0x12932 +#define mmVPMPCC_MCM0_VPMPCC_MCM_1DLUT_RAMA_REGION_22_23 0x128A3 +#define mmVPMPCC_MCM1_VPMPCC_MCM_1DLUT_RAMA_REGION_22_23 0x12933 +#define mmVPMPCC_MCM0_VPMPCC_MCM_1DLUT_RAMA_REGION_24_25 0x128A4 +#define mmVPMPCC_MCM1_VPMPCC_MCM_1DLUT_RAMA_REGION_24_25 0x12934 +#define mmVPMPCC_MCM0_VPMPCC_MCM_1DLUT_RAMA_REGION_26_27 0x128A5 +#define mmVPMPCC_MCM1_VPMPCC_MCM_1DLUT_RAMA_REGION_26_27 0x12935 +#define mmVPMPCC_MCM0_VPMPCC_MCM_1DLUT_RAMA_REGION_28_29 0x128A6 +#define mmVPMPCC_MCM1_VPMPCC_MCM_1DLUT_RAMA_REGION_28_29 0x12936 +#define mmVPMPCC_MCM0_VPMPCC_MCM_1DLUT_RAMA_REGION_30_31 0x128A7 +#define mmVPMPCC_MCM1_VPMPCC_MCM_1DLUT_RAMA_REGION_30_31 0x12937 +#define mmVPMPCC_MCM0_VPMPCC_MCM_1DLUT_RAMA_REGION_32_33 0x128A8 +#define mmVPMPCC_MCM1_VPMPCC_MCM_1DLUT_RAMA_REGION_32_33 0x12938 +#define mmVPMPCC_MCM0_VPMPCC_MCM_FIRST_GAMUT_REMAP_COEF_FORMAT 0x128A9 +#define mmVPMPCC_MCM1_VPMPCC_MCM_FIRST_GAMUT_REMAP_COEF_FORMAT 0x12939 +#define mmVPMPCC_MCM0_VPMPCC_MCM_FIRST_GAMUT_REMAP_MODE 0x128AA +#define mmVPMPCC_MCM1_VPMPCC_MCM_FIRST_GAMUT_REMAP_MODE 0x1293A +#define mmVPMPCC_MCM0_VPMPC_MCM_FIRST_GAMUT_REMAP_C11_C12_SETA 0x128AB +#define mmVPMPCC_MCM1_VPMPC_MCM_FIRST_GAMUT_REMAP_C11_C12_SETA 0x1293B +#define mmVPMPCC_MCM0_VPMPC_MCM_FIRST_GAMUT_REMAP_C13_C14_SETA 0x128AC +#define mmVPMPCC_MCM1_VPMPC_MCM_FIRST_GAMUT_REMAP_C13_C14_SETA 0x1293C +#define mmVPMPCC_MCM0_VPMPC_MCM_FIRST_GAMUT_REMAP_C21_C22_SETA 0x128AD +#define mmVPMPCC_MCM1_VPMPC_MCM_FIRST_GAMUT_REMAP_C21_C22_SETA 0x1293D +#define mmVPMPCC_MCM0_VPMPC_MCM_FIRST_GAMUT_REMAP_C23_C24_SETA 0x128AE +#define mmVPMPCC_MCM1_VPMPC_MCM_FIRST_GAMUT_REMAP_C23_C24_SETA 0x1293E +#define mmVPMPCC_MCM0_VPMPC_MCM_FIRST_GAMUT_REMAP_C31_C32_SETA 0x128AF +#define mmVPMPCC_MCM1_VPMPC_MCM_FIRST_GAMUT_REMAP_C31_C32_SETA 0x1293F +#define mmVPMPCC_MCM0_VPMPC_MCM_FIRST_GAMUT_REMAP_C33_C34_SETA 0x128B0 +#define mmVPMPCC_MCM1_VPMPC_MCM_FIRST_GAMUT_REMAP_C33_C34_SETA 0x12940 +#define mmVPMPCC_MCM0_VPMPCC_MCM_SECOND_GAMUT_REMAP_COEF_FORMAT 0x128B1 +#define mmVPMPCC_MCM1_VPMPCC_MCM_SECOND_GAMUT_REMAP_COEF_FORMAT 0x12941 +#define mmVPMPCC_MCM0_VPMPCC_MCM_SECOND_GAMUT_REMAP_MODE 0x128B2 +#define mmVPMPCC_MCM1_VPMPCC_MCM_SECOND_GAMUT_REMAP_MODE 0x12942 +#define mmVPMPCC_MCM0_VPMPC_MCM_SECOND_GAMUT_REMAP_C11_C12_SETA 0x128B3 +#define mmVPMPCC_MCM1_VPMPC_MCM_SECOND_GAMUT_REMAP_C11_C12_SETA 0x12943 +#define mmVPMPCC_MCM0_VPMPC_MCM_SECOND_GAMUT_REMAP_C13_C14_SETA 0x128B4 +#define mmVPMPCC_MCM1_VPMPC_MCM_SECOND_GAMUT_REMAP_C13_C14_SETA 0x12944 +#define mmVPMPCC_MCM0_VPMPC_MCM_SECOND_GAMUT_REMAP_C21_C22_SETA 0x128B5 +#define mmVPMPCC_MCM1_VPMPC_MCM_SECOND_GAMUT_REMAP_C21_C22_SETA 0x12945 +#define mmVPMPCC_MCM0_VPMPC_MCM_SECOND_GAMUT_REMAP_C23_C24_SETA 0x128B6 +#define mmVPMPCC_MCM1_VPMPC_MCM_SECOND_GAMUT_REMAP_C23_C24_SETA 0x12946 +#define mmVPMPCC_MCM0_VPMPC_MCM_SECOND_GAMUT_REMAP_C31_C32_SETA 0x128B7 +#define mmVPMPCC_MCM1_VPMPC_MCM_SECOND_GAMUT_REMAP_C31_C32_SETA 0x12947 +#define mmVPMPCC_MCM0_VPMPC_MCM_SECOND_GAMUT_REMAP_C33_C34_SETA 0x128B8 +#define mmVPMPCC_MCM1_VPMPC_MCM_SECOND_GAMUT_REMAP_C33_C34_SETA 0x12948 +#define mmVPMPCC_MCM0_VPMPCC_MCM_MEM_PWR_CTRL 0x128B9 +#define mmVPMPCC_MCM1_VPMPCC_MCM_MEM_PWR_CTRL 0x12949 + + +// Registers from VPMPC_RMCM block + +#define mmVPMPC_RMCM_SHAPER_CONTROL 0x126F0 +#define mmVPMPC_RMCM_SHAPER_OFFSET_R 0x126F1 +#define mmVPMPC_RMCM_SHAPER_OFFSET_G 0x126F2 +#define mmVPMPC_RMCM_SHAPER_OFFSET_B 0x126F3 +#define mmVPMPC_RMCM_SHAPER_SCALE_R 0x126F4 +#define mmVPMPC_RMCM_SHAPER_SCALE_G_B 0x126F5 +#define mmVPMPC_RMCM_SHAPER_LUT_INDEX 0x126F6 +#define mmVPMPC_RMCM_SHAPER_LUT_DATA 0x126F7 +#define mmVPMPC_RMCM_SHAPER_LUT_WRITE_EN_MASK 0x126F8 +#define mmVPMPC_RMCM_SHAPER_RAMA_START_CNTL_B 0x126F9 +#define mmVPMPC_RMCM_SHAPER_RAMA_START_CNTL_G 0x126FA +#define mmVPMPC_RMCM_SHAPER_RAMA_START_CNTL_R 0x126FB +#define mmVPMPC_RMCM_SHAPER_RAMA_END_CNTL_B 0x126FC +#define mmVPMPC_RMCM_SHAPER_RAMA_END_CNTL_G 0x126FD +#define mmVPMPC_RMCM_SHAPER_RAMA_END_CNTL_R 0x126FE +#define mmVPMPC_RMCM_SHAPER_RAMA_REGION_0_1 0x126FF +#define mmVPMPC_RMCM_SHAPER_RAMA_REGION_2_3 0x12700 +#define mmVPMPC_RMCM_SHAPER_RAMA_REGION_4_5 0x12701 +#define mmVPMPC_RMCM_SHAPER_RAMA_REGION_6_7 0x12702 +#define mmVPMPC_RMCM_SHAPER_RAMA_REGION_8_9 0x12703 +#define mmVPMPC_RMCM_SHAPER_RAMA_REGION_10_11 0x12704 +#define mmVPMPC_RMCM_SHAPER_RAMA_REGION_12_13 0x12705 +#define mmVPMPC_RMCM_SHAPER_RAMA_REGION_14_15 0x12706 +#define mmVPMPC_RMCM_SHAPER_RAMA_REGION_16_17 0x12707 +#define mmVPMPC_RMCM_SHAPER_RAMA_REGION_18_19 0x12708 +#define mmVPMPC_RMCM_SHAPER_RAMA_REGION_20_21 0x12709 +#define mmVPMPC_RMCM_SHAPER_RAMA_REGION_22_23 0x1270A +#define mmVPMPC_RMCM_SHAPER_RAMA_REGION_24_25 0x1270B +#define mmVPMPC_RMCM_SHAPER_RAMA_REGION_26_27 0x1270C +#define mmVPMPC_RMCM_SHAPER_RAMA_REGION_28_29 0x1270D +#define mmVPMPC_RMCM_SHAPER_RAMA_REGION_30_31 0x1270E +#define mmVPMPC_RMCM_SHAPER_RAMA_REGION_32_33 0x1270F +#define mmVPMPC_RMCM_3DLUT_MODE 0x12710 +#define mmVPMPC_RMCM_3DLUT_INDEX 0x12711 +#define mmVPMPC_RMCM_3DLUT_DATA 0x12712 +#define mmVPMPC_RMCM_3DLUT_DATA_30BIT 0x12713 +#define mmVPMPC_RMCM_3DLUT_READ_WRITE_CONTROL 0x12714 +#define mmVPMPC_RMCM_3DLUT_OUT_NORM_FACTOR 0x12715 +#define mmVPMPC_RMCM_3DLUT_OUT_OFFSET_R 0x12716 +#define mmVPMPC_RMCM_3DLUT_OUT_OFFSET_G 0x12717 +#define mmVPMPC_RMCM_3DLUT_OUT_OFFSET_B 0x12718 +#define mmVPMPC_RMCM_GAMUT_REMAP_COEF_FORMAT 0x12719 +#define mmVPMPC_RMCM_GAMUT_REMAP_MODE 0x1271A +#define mmVPMPC_RMCM_GAMUT_REMAP_C11_C12_SETA 0x1271B +#define mmVPMPC_RMCM_GAMUT_REMAP_C13_C14_SETA 0x1271C +#define mmVPMPC_RMCM_GAMUT_REMAP_C21_C22_SETA 0x1271D +#define mmVPMPC_RMCM_GAMUT_REMAP_C23_C24_SETA 0x1271E +#define mmVPMPC_RMCM_GAMUT_REMAP_C31_C32_SETA 0x1271F +#define mmVPMPC_RMCM_GAMUT_REMAP_C33_C34_SETA 0x12720 +#define mmVPMPC_RMCM_MEM_PWR_CTRL 0x12721 +#define mmVPMPC_RMCM_3DLUT_FAST_LOAD_SELECT 0x12722 +#define mmVPMPC_RMCM_CNTL 0x12724 + + +// Registers from VPFMT block + +#define mmVPFMT0_VPFMT_CLAMP_COMPONENT_R 0x12AB0 +#define mmVPFMT1_VPFMT_CLAMP_COMPONENT_R 0x12AF3 +#define mmVPFMT0_VPFMT_CLAMP_COMPONENT_G 0x12AB1 +#define mmVPFMT1_VPFMT_CLAMP_COMPONENT_G 0x12AF4 +#define mmVPFMT0_VPFMT_CLAMP_COMPONENT_B 0x12AB2 +#define mmVPFMT1_VPFMT_CLAMP_COMPONENT_B 0x12AF5 +#define mmVPFMT0_VPFMT_DYNAMIC_EXP_CNTL 0x12AB3 +#define mmVPFMT1_VPFMT_DYNAMIC_EXP_CNTL 0x12AF6 +#define mmVPFMT0_VPFMT_CONTROL 0x12AB4 +#define mmVPFMT1_VPFMT_CONTROL 0x12AF7 +#define mmVPFMT0_VPFMT_BIT_DEPTH_CONTROL 0x12AB5 +#define mmVPFMT1_VPFMT_BIT_DEPTH_CONTROL 0x12AF8 +#define mmVPFMT0_VPFMT_DITHER_RAND_R_SEED 0x12AB6 +#define mmVPFMT1_VPFMT_DITHER_RAND_R_SEED 0x12AF9 +#define mmVPFMT0_VPFMT_DITHER_RAND_G_SEED 0x12AB7 +#define mmVPFMT1_VPFMT_DITHER_RAND_G_SEED 0x12AFA +#define mmVPFMT0_VPFMT_DITHER_RAND_B_SEED 0x12AB8 +#define mmVPFMT1_VPFMT_DITHER_RAND_B_SEED 0x12AFB +#define mmVPFMT0_VPFMT_CLAMP_CNTL 0x12AB9 +#define mmVPFMT1_VPFMT_CLAMP_CNTL 0x12AFC +#define mmVPFMT0_VPFMT_SUBSAMPLER_MEMORY_CONTROL 0x12ABA +#define mmVPFMT1_VPFMT_SUBSAMPLER_MEMORY_CONTROL 0x12AFD + + +// Registers from VPOPP_PIPE block + +#define mmVPOPP_PIPE0_VPOPP_PIPE_CONTROL 0x12AD8 +#define mmVPOPP_PIPE1_VPOPP_PIPE_CONTROL 0x12B1B +#define mmVPOPP_PIPE0_VPOPP_PIPE_OUTBG_EXT1 0x12AD9 +#define mmVPOPP_PIPE1_VPOPP_PIPE_OUTBG_EXT1 0x12B1C +#define mmVPOPP_PIPE0_VPOPP_PIPE_OUTBG_EXT2 0x12ADA +#define mmVPOPP_PIPE1_VPOPP_PIPE_OUTBG_EXT2 0x12B1D +#define mmVPOPP_PIPE0_VPOPP_PIPE_OUTBG_COL1 0x12ADB +#define mmVPOPP_PIPE1_VPOPP_PIPE_OUTBG_COL1 0x12B1E +#define mmVPOPP_PIPE0_VPOPP_PIPE_OUTBG_COL2 0x12ADC +#define mmVPOPP_PIPE1_VPOPP_PIPE_OUTBG_COL2 0x12B1F + + +// Registers from VPOPP_TOP block + +#define mmVPOPP_TOP_CLK_CONTROL 0x12BC2 +#define mmVPOPP_CRC_CONTROL 0x12BC4 +#define mmVPOPP_CRC_RESULT_RG 0x12BC5 +#define mmVPOPP_CRC_RESULT_BC 0x12BC6 +#define mmVPOPP_FROD_CONTROL 0x12BC7 +#define mmVPOPP_FROD_MEM_PWR_CONTROL 0x12BC8 + +#endif diff --git a/src/amd/vpelib/src/chip/vpe22/inc/asic/chip_shift.h b/src/amd/vpelib/src/chip/vpe22/inc/asic/chip_shift.h new file mode 100644 index 00000000000..49c530fecb0 --- /dev/null +++ b/src/amd/vpelib/src/chip/vpe22/inc/asic/chip_shift.h @@ -0,0 +1,1893 @@ +// Copyright (c) 1994 - 2025 Advanced Micro Devices, Inc. All rights reserved. + +#if !defined (_vpe22_SHIFT_HEADER) +#define _vpe22_SHIFT_HEADER +/* + * vpe22_shift.h + * + * Register Spec Release: + * + * + * (c) 2021 Advanced Micro Devices, Inc. (unpublished) + * + * All rights reserved. This notice is intended as a precaution against + * inadvertent publication and does not imply publication or any waiver + * of confidentiality. The year included in the foregoing notice is the + * year of creation of the work. + * + */ + +// reg: VPEP_MGCG_CNTL block: CDC comp: amd.com/lib/vpcdc-vpep2gn/1.0 +#define VPEP_MGCG_CNTL__VPDPP0_CLK_GATE_DIS__SHIFT 0x00000000 +#define VPEP_MGCG_CNTL__VPMPC_CLK_GATE_DIS__SHIFT 0x0000000c +#define VPEP_MGCG_CNTL__VPOPP_CLK_GATE_DIS__SHIFT 0x00000012 +#define VPEP_MGCG_CNTL__VPCDC_SOCCLK_G_GATE_DIS__SHIFT 0x00000014 +#define VPEP_MGCG_CNTL__VPCDC_SOCCLK_R_GATE_DIS__SHIFT 0x00000015 +#define VPEP_MGCG_CNTL__VPCDC_VPECLK_G_GATE_DIS__SHIFT 0x00000016 +#define VPEP_MGCG_CNTL__VPCDC_VPECLK_R_GATE_DIS__SHIFT 0x00000017 + +// reg: VPCDC_SOFT_RESET block: CDC comp: amd.com/lib/vpcdc-vpep2gn/1.0 +#define VPCDC_SOFT_RESET__VPCDC_SOCCLK_SOFT_RESET__SHIFT 0x00000000 +#define VPCDC_SOFT_RESET__VPCDC_VPECLK_SOFT_RESET__SHIFT 0x00000001 + +// reg: VPCDC_FE0_SURFACE_CONFIG block: CDC comp: amd.com/lib/vpcdc-vpep2gn/1.0 +#define VPCDC_FE0_SURFACE_CONFIG__SURFACE_PIXEL_FORMAT_FE0__SHIFT 0x00000000 +#define VPCDC_FE0_SURFACE_CONFIG__ROTATION_ANGLE_FE0__SHIFT 0x00000009 +#define VPCDC_FE0_SURFACE_CONFIG__H_MIRROR_EN_FE0__SHIFT 0x0000000c +#define VPCDC_FE0_SURFACE_CONFIG__PIX_SURFACE_LINEAR_FE0__SHIFT 0x0000000d + +// reg: VPCDC_FE0_CROSSBAR_CONFIG block: CDC comp: amd.com/lib/vpcdc-vpep2gn/1.0 +#define VPCDC_FE0_CROSSBAR_CONFIG__CROSSBAR_SRC_ALPHA_FE0__SHIFT 0x00000000 +#define VPCDC_FE0_CROSSBAR_CONFIG__CROSSBAR_SRC_Y_G_FE0__SHIFT 0x00000002 +#define VPCDC_FE0_CROSSBAR_CONFIG__CROSSBAR_SRC_CB_B_FE0__SHIFT 0x00000004 +#define VPCDC_FE0_CROSSBAR_CONFIG__CROSSBAR_SRC_CR_R_FE0__SHIFT 0x00000006 + +// reg: VPCDC_FE0_VIEWPORT_START_CONFIG block: CDC comp: amd.com/lib/vpcdc-vpep2gn/1.0 +#define VPCDC_FE0_VIEWPORT_START_CONFIG__VIEWPORT_X_START_FE0__SHIFT 0x00000000 +#define VPCDC_FE0_VIEWPORT_START_CONFIG__VIEWPORT_Y_START_FE0__SHIFT 0x00000010 + +// reg: VPCDC_FE0_VIEWPORT_DIMENSION_CONFIG block: CDC comp: amd.com/lib/vpcdc-vpep2gn/1.0 +#define VPCDC_FE0_VIEWPORT_DIMENSION_CONFIG__VIEWPORT_WIDTH_FE0__SHIFT 0x00000000 +#define VPCDC_FE0_VIEWPORT_DIMENSION_CONFIG__VIEWPORT_HEIGHT_FE0__SHIFT 0x00000010 + +// reg: VPCDC_FE0_VIEWPORT_START_C_CONFIG block: CDC comp: amd.com/lib/vpcdc-vpep2gn/1.0 +#define VPCDC_FE0_VIEWPORT_START_C_CONFIG__VIEWPORT_X_START_C_FE0__SHIFT 0x00000000 +#define VPCDC_FE0_VIEWPORT_START_C_CONFIG__VIEWPORT_Y_START_C_FE0__SHIFT 0x00000010 + +// reg: VPCDC_FE0_VIEWPORT_DIMENSION_C_CONFIG block: CDC comp: amd.com/lib/vpcdc-vpep2gn/1.0 +#define VPCDC_FE0_VIEWPORT_DIMENSION_C_CONFIG__VIEWPORT_WIDTH_C_FE0__SHIFT 0x00000000 +#define VPCDC_FE0_VIEWPORT_DIMENSION_C_CONFIG__VIEWPORT_HEIGHT_C_FE0__SHIFT 0x00000010 + +// reg: VPCDC_BE0_P2B_CONFIG block: CDC comp: amd.com/lib/vpcdc-vpep2gn/1.0 +#define VPCDC_BE0_P2B_CONFIG__VPCDC_BE0_P2B_XBAR_SEL0__SHIFT 0x00000000 +#define VPCDC_BE0_P2B_CONFIG__VPCDC_BE0_P2B_XBAR_SEL1__SHIFT 0x00000002 +#define VPCDC_BE0_P2B_CONFIG__VPCDC_BE0_P2B_XBAR_SEL2__SHIFT 0x00000004 +#define VPCDC_BE0_P2B_CONFIG__VPCDC_BE0_P2B_XBAR_SEL3__SHIFT 0x00000006 +#define VPCDC_BE0_P2B_CONFIG__VPCDC_BE0_P2B_FORMAT_SEL__SHIFT 0x00000008 +#define VPCDC_BE0_P2B_CONFIG__VPCDC_BE0_P2B_TILED__SHIFT 0x00000011 +#define VPCDC_BE0_P2B_CONFIG__VPCDC_BE0_P2B_X_START_PLANE0__SHIFT 0x00000012 +#define VPCDC_BE0_P2B_CONFIG__VPCDC_BE0_P2B_X_START_PLANE1__SHIFT 0x00000017 + +// reg: VPCDC_BE0_GLOBAL_SYNC_CONFIG block: CDC comp: amd.com/lib/vpcdc-vpep2gn/1.0 +#define VPCDC_BE0_GLOBAL_SYNC_CONFIG__BE0_VUPDATE_OFFSET__SHIFT 0x00000000 +#define VPCDC_BE0_GLOBAL_SYNC_CONFIG__BE0_VUPDATE_WIDTH__SHIFT 0x0000000a +#define VPCDC_BE0_GLOBAL_SYNC_CONFIG__BE0_VREADY_OFFSET__SHIFT 0x00000014 + +// reg: VPCDC_GLOBAL_SYNC_TRIGGER block: CDC comp: amd.com/lib/vpcdc-vpep2gn/1.0 +#define VPCDC_GLOBAL_SYNC_TRIGGER__VPBE_GS_TRIG__SHIFT 0x00000000 + +// reg: VPCDC_VREADY_STATUS block: CDC comp: amd.com/lib/vpcdc-vpep2gn/1.0 +#define VPCDC_VREADY_STATUS__VPFE_VR_STATUS__SHIFT 0x00000000 + +// reg: VPEP_MEM_GLOBAL_PWR_REQ_CNTL block: CDC comp: amd.com/lib/vpcdc-vpep2gn/1.0 +#define VPEP_MEM_GLOBAL_PWR_REQ_CNTL__MEM_GLOBAL_PWR_REQ_DIS__SHIFT 0x00000000 + +// reg: VPFE0_MEM_PWR_CNTL block: CDC comp: amd.com/lib/vpcdc-vpep2gn/1.0 +#define VPFE0_MEM_PWR_CNTL__VPFE0_MEM_PWR_FORCE__SHIFT 0x00000000 +#define VPFE0_MEM_PWR_CNTL__VPFE0_MEM_PWR_MODE__SHIFT 0x00000002 +#define VPFE0_MEM_PWR_CNTL__VPFE0_MEM_PWR_STATE__SHIFT 0x00000004 +#define VPFE0_MEM_PWR_CNTL__VPFE0_MEM_PWR_DIS__SHIFT 0x00000006 + +// reg: VPBE0_MEM_PWR_CNTL block: CDC comp: amd.com/lib/vpcdc-vpep2gn/1.0 +#define VPBE0_MEM_PWR_CNTL__VPBE0_MEM_PWR_FORCE__SHIFT 0x00000000 +#define VPBE0_MEM_PWR_CNTL__VPBE0_MEM_PWR_MODE__SHIFT 0x00000002 +#define VPBE0_MEM_PWR_CNTL__VPBE0_MEM_PWR_STATE__SHIFT 0x00000004 +#define VPBE0_MEM_PWR_CNTL__VPBE0_MEM_PWR_DIS__SHIFT 0x00000006 + +// reg: VPCDC_3DLUT_FL_CONFIG block: CDC comp: amd.com/lib/vpcdc-vpep2gn/1.0 +#define VPCDC_3DLUT_FL_CONFIG__VPCDC_3DLUT_FL_MODE__SHIFT 0x00000000 +#define VPCDC_3DLUT_FL_CONFIG__VPCDC_3DLUT_FL_CROSSBAR_SRC_G__SHIFT 0x00000002 +#define VPCDC_3DLUT_FL_CONFIG__VPCDC_3DLUT_FL_CROSSBAR_SRC_B__SHIFT 0x00000004 +#define VPCDC_3DLUT_FL_CONFIG__VPCDC_3DLUT_FL_CROSSBAR_SRC_R__SHIFT 0x00000006 +#define VPCDC_3DLUT_FL_CONFIG__VPCDC_3DLUT_FL_SIZE__SHIFT 0x00000008 + +// reg: VPCDC_CONTROL block: CDC comp: amd.com/lib/vpcdc-vpep2gn/1.0 +#define VPCDC_CONTROL__VPCDC_HISTOGRAM0_EN__SHIFT 0x00000000 +#define VPCDC_CONTROL__VPCDC_HISTOGRAM1_EN__SHIFT 0x00000002 +#define VPCDC_CONTROL__VPCDC_FROD_EN__SHIFT 0x00000008 + + +// reg: VPCNVC_SURFACE_PIXEL_FORMAT block: VPCNVC_CFG comp: amd.com/lib/vpdpp-vpep2gn/1.0 +#define VPCNVC_SURFACE_PIXEL_FORMAT__VPCNVC_SURFACE_PIXEL_FORMAT__SHIFT 0x00000000 + +// reg: VPCNVC_FORMAT_CONTROL block: VPCNVC_CFG comp: amd.com/lib/vpdpp-vpep2gn/1.0 +#define VPCNVC_FORMAT_CONTROL__FORMAT_EXPANSION_MODE__SHIFT 0x00000000 +#define VPCNVC_FORMAT_CONTROL__FORMAT_CNV16__SHIFT 0x00000004 +#define VPCNVC_FORMAT_CONTROL__ALPHA_EN__SHIFT 0x00000008 +#define VPCNVC_FORMAT_CONTROL__VPCNVC_BYPASS__SHIFT 0x0000000c +#define VPCNVC_FORMAT_CONTROL__VPCNVC_BYPASS_MSB_ALIGN__SHIFT 0x0000000d +#define VPCNVC_FORMAT_CONTROL__CLAMP_POSITIVE__SHIFT 0x00000010 +#define VPCNVC_FORMAT_CONTROL__CLAMP_POSITIVE_C__SHIFT 0x00000011 +#define VPCNVC_FORMAT_CONTROL__VPCNVC_UPDATE_PENDING__SHIFT 0x00000014 + +// reg: VPCNVC_FCNV_FP_BIAS_R block: VPCNVC_CFG comp: amd.com/lib/vpdpp-vpep2gn/1.0 +#define VPCNVC_FCNV_FP_BIAS_R__FCNV_FP_BIAS_R__SHIFT 0x00000000 + +// reg: VPCNVC_FCNV_FP_BIAS_G block: VPCNVC_CFG comp: amd.com/lib/vpdpp-vpep2gn/1.0 +#define VPCNVC_FCNV_FP_BIAS_G__FCNV_FP_BIAS_G__SHIFT 0x00000000 + +// reg: VPCNVC_FCNV_FP_BIAS_B block: VPCNVC_CFG comp: amd.com/lib/vpdpp-vpep2gn/1.0 +#define VPCNVC_FCNV_FP_BIAS_B__FCNV_FP_BIAS_B__SHIFT 0x00000000 + +// reg: VPCNVC_FCNV_FP_SCALE_R block: VPCNVC_CFG comp: amd.com/lib/vpdpp-vpep2gn/1.0 +#define VPCNVC_FCNV_FP_SCALE_R__FCNV_FP_SCALE_R__SHIFT 0x00000000 + +// reg: VPCNVC_FCNV_FP_SCALE_G block: VPCNVC_CFG comp: amd.com/lib/vpdpp-vpep2gn/1.0 +#define VPCNVC_FCNV_FP_SCALE_G__FCNV_FP_SCALE_G__SHIFT 0x00000000 + +// reg: VPCNVC_FCNV_FP_SCALE_B block: VPCNVC_CFG comp: amd.com/lib/vpdpp-vpep2gn/1.0 +#define VPCNVC_FCNV_FP_SCALE_B__FCNV_FP_SCALE_B__SHIFT 0x00000000 + +// reg: VPCNVC_COLOR_KEYER_CONTROL block: VPCNVC_CFG comp: amd.com/lib/vpdpp-vpep2gn/1.0 +#define VPCNVC_COLOR_KEYER_CONTROL__COLOR_KEYER_EN__SHIFT 0x00000000 +#define VPCNVC_COLOR_KEYER_CONTROL__LUMA_KEYER_EN__SHIFT 0x00000001 +#define VPCNVC_COLOR_KEYER_CONTROL__COLOR_KEYER_MODE__SHIFT 0x00000004 + +// reg: VPCNVC_COLOR_KEYER_ALPHA block: VPCNVC_CFG comp: amd.com/lib/vpdpp-vpep2gn/1.0 +#define VPCNVC_COLOR_KEYER_ALPHA__COLOR_KEYER_ALPHA_LOW__SHIFT 0x00000000 +#define VPCNVC_COLOR_KEYER_ALPHA__COLOR_KEYER_ALPHA_HIGH__SHIFT 0x00000010 + +// reg: VPCNVC_COLOR_KEYER_RED block: VPCNVC_CFG comp: amd.com/lib/vpdpp-vpep2gn/1.0 +#define VPCNVC_COLOR_KEYER_RED__COLOR_KEYER_RED_LOW__SHIFT 0x00000000 +#define VPCNVC_COLOR_KEYER_RED__COLOR_KEYER_RED_HIGH__SHIFT 0x00000010 + +// reg: VPCNVC_COLOR_KEYER_GREEN block: VPCNVC_CFG comp: amd.com/lib/vpdpp-vpep2gn/1.0 +#define VPCNVC_COLOR_KEYER_GREEN__COLOR_KEYER_GREEN_LOW__SHIFT 0x00000000 +#define VPCNVC_COLOR_KEYER_GREEN__COLOR_KEYER_GREEN_HIGH__SHIFT 0x00000010 + +// reg: VPCNVC_COLOR_KEYER_BLUE block: VPCNVC_CFG comp: amd.com/lib/vpdpp-vpep2gn/1.0 +#define VPCNVC_COLOR_KEYER_BLUE__COLOR_KEYER_BLUE_LOW__SHIFT 0x00000000 +#define VPCNVC_COLOR_KEYER_BLUE__COLOR_KEYER_BLUE_HIGH__SHIFT 0x00000010 + +// reg: VPCNVC_ALPHA_2BIT_LUT01 block: VPCNVC_CFG comp: amd.com/lib/vpdpp-vpep2gn/1.0 +#define VPCNVC_ALPHA_2BIT_LUT01__ALPHA_2BIT_LUT0__SHIFT 0x00000000 +#define VPCNVC_ALPHA_2BIT_LUT01__ALPHA_2BIT_LUT1__SHIFT 0x00000010 + +// reg: VPCNVC_ALPHA_2BIT_LUT23 block: VPCNVC_CFG comp: amd.com/lib/vpdpp-vpep2gn/1.0 +#define VPCNVC_ALPHA_2BIT_LUT23__ALPHA_2BIT_LUT2__SHIFT 0x00000000 +#define VPCNVC_ALPHA_2BIT_LUT23__ALPHA_2BIT_LUT3__SHIFT 0x00000010 + +// reg: VPCNVC_PRE_DEALPHA block: VPCNVC_CFG comp: amd.com/lib/vpdpp-vpep2gn/1.0 +#define VPCNVC_PRE_DEALPHA__PRE_DEALPHA_EN__SHIFT 0x00000000 +#define VPCNVC_PRE_DEALPHA__PRE_DEALPHA_ABLND_EN__SHIFT 0x00000004 + +// reg: VPCNVC_PRE_CSC_MODE block: VPCNVC_CFG comp: amd.com/lib/vpdpp-vpep2gn/1.0 +#define VPCNVC_PRE_CSC_MODE__PRE_CSC_MODE__SHIFT 0x00000000 +#define VPCNVC_PRE_CSC_MODE__PRE_CSC_MODE_CURRENT__SHIFT 0x00000002 + +// reg: VPCNVC_PRE_CSC_C11_C12 block: VPCNVC_CFG comp: amd.com/lib/vpdpp-vpep2gn/1.0 +#define VPCNVC_PRE_CSC_C11_C12__PRE_CSC_C11__SHIFT 0x00000000 +#define VPCNVC_PRE_CSC_C11_C12__PRE_CSC_C12__SHIFT 0x00000010 + +// reg: VPCNVC_PRE_CSC_C13_C14 block: VPCNVC_CFG comp: amd.com/lib/vpdpp-vpep2gn/1.0 +#define VPCNVC_PRE_CSC_C13_C14__PRE_CSC_C13__SHIFT 0x00000000 +#define VPCNVC_PRE_CSC_C13_C14__PRE_CSC_C14__SHIFT 0x00000010 + +// reg: VPCNVC_PRE_CSC_C21_C22 block: VPCNVC_CFG comp: amd.com/lib/vpdpp-vpep2gn/1.0 +#define VPCNVC_PRE_CSC_C21_C22__PRE_CSC_C21__SHIFT 0x00000000 +#define VPCNVC_PRE_CSC_C21_C22__PRE_CSC_C22__SHIFT 0x00000010 + +// reg: VPCNVC_PRE_CSC_C23_C24 block: VPCNVC_CFG comp: amd.com/lib/vpdpp-vpep2gn/1.0 +#define VPCNVC_PRE_CSC_C23_C24__PRE_CSC_C23__SHIFT 0x00000000 +#define VPCNVC_PRE_CSC_C23_C24__PRE_CSC_C24__SHIFT 0x00000010 + +// reg: VPCNVC_PRE_CSC_C31_C32 block: VPCNVC_CFG comp: amd.com/lib/vpdpp-vpep2gn/1.0 +#define VPCNVC_PRE_CSC_C31_C32__PRE_CSC_C31__SHIFT 0x00000000 +#define VPCNVC_PRE_CSC_C31_C32__PRE_CSC_C32__SHIFT 0x00000010 + +// reg: VPCNVC_PRE_CSC_C33_C34 block: VPCNVC_CFG comp: amd.com/lib/vpdpp-vpep2gn/1.0 +#define VPCNVC_PRE_CSC_C33_C34__PRE_CSC_C33__SHIFT 0x00000000 +#define VPCNVC_PRE_CSC_C33_C34__PRE_CSC_C34__SHIFT 0x00000010 + +// reg: VPCNVC_COEF_FORMAT block: VPCNVC_CFG comp: amd.com/lib/vpdpp-vpep2gn/1.0 +#define VPCNVC_COEF_FORMAT__PRE_CSC_COEF_FORMAT__SHIFT 0x00000000 + +// reg: VPCNVC_PRE_DEGAM block: VPCNVC_CFG comp: amd.com/lib/vpdpp-vpep2gn/1.0 +#define VPCNVC_PRE_DEGAM__PRE_DEGAM_MODE__SHIFT 0x00000000 +#define VPCNVC_PRE_DEGAM__PRE_DEGAM_SELECT__SHIFT 0x00000004 + +// reg: VPCNVC_PRE_REALPHA block: VPCNVC_CFG comp: amd.com/lib/vpdpp-vpep2gn/1.0 +#define VPCNVC_PRE_REALPHA__PRE_REALPHA_EN__SHIFT 0x00000000 +#define VPCNVC_PRE_REALPHA__PRE_REALPHA_ABLND_EN__SHIFT 0x00000004 + +// reg: VPDSCL_COEF_RAM_TAP_SELECT block: VPDSCL comp: amd.com/lib/vpdpp-vpep2gn/1.0 +#define VPDSCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_TAP_PAIR_IDX__SHIFT 0x00000000 +#define VPDSCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_PHASE__SHIFT 0x00000008 +#define VPDSCL_COEF_RAM_TAP_SELECT__SCL_COEF_RAM_FILTER_TYPE__SHIFT 0x00000010 + +// reg: VPDSCL_COEF_RAM_TAP_DATA block: VPDSCL comp: amd.com/lib/vpdpp-vpep2gn/1.0 +#define VPDSCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_EVEN_TAP_COEF__SHIFT 0x00000000 +#define VPDSCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_EVEN_TAP_COEF_EN__SHIFT 0x0000000f +#define VPDSCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_ODD_TAP_COEF__SHIFT 0x00000010 +#define VPDSCL_COEF_RAM_TAP_DATA__SCL_COEF_RAM_ODD_TAP_COEF_EN__SHIFT 0x0000001f + +// reg: VPDSCL_MODE block: VPDSCL comp: amd.com/lib/vpdpp-vpep2gn/1.0 +#define VPDSCL_MODE__VPDSCL_MODE__SHIFT 0x00000000 +#define VPDSCL_MODE__SCL_COEF_RAM_SELECT_CURRENT__SHIFT 0x0000000c +#define VPDSCL_MODE__SCL_CHROMA_COEF_MODE__SHIFT 0x00000010 +#define VPDSCL_MODE__SCL_ALPHA_COEF_MODE__SHIFT 0x00000014 +#define VPDSCL_MODE__SCL_COEF_RAM_SELECT_RD__SHIFT 0x00000018 + +// reg: VPDSCL_TAP_CONTROL block: VPDSCL comp: amd.com/lib/vpdpp-vpep2gn/1.0 +#define VPDSCL_TAP_CONTROL__SCL_V_NUM_TAPS__SHIFT 0x00000000 +#define VPDSCL_TAP_CONTROL__SCL_H_NUM_TAPS__SHIFT 0x00000004 +#define VPDSCL_TAP_CONTROL__SCL_V_NUM_TAPS_C__SHIFT 0x00000008 +#define VPDSCL_TAP_CONTROL__SCL_H_NUM_TAPS_C__SHIFT 0x0000000c + +// reg: VPDSCL_CONTROL block: VPDSCL comp: amd.com/lib/vpdpp-vpep2gn/1.0 +#define VPDSCL_CONTROL__SCL_BOUNDARY_MODE__SHIFT 0x00000000 + +// reg: VPDSCL_2TAP_CONTROL block: VPDSCL comp: amd.com/lib/vpdpp-vpep2gn/1.0 +#define VPDSCL_2TAP_CONTROL__SCL_H_2TAP_HARDCODE_COEF_EN__SHIFT 0x00000000 +#define VPDSCL_2TAP_CONTROL__SCL_H_2TAP_SHARP_EN__SHIFT 0x00000004 +#define VPDSCL_2TAP_CONTROL__SCL_H_2TAP_SHARP_FACTOR__SHIFT 0x00000008 +#define VPDSCL_2TAP_CONTROL__SCL_V_2TAP_HARDCODE_COEF_EN__SHIFT 0x00000010 +#define VPDSCL_2TAP_CONTROL__SCL_V_2TAP_SHARP_EN__SHIFT 0x00000014 +#define VPDSCL_2TAP_CONTROL__SCL_V_2TAP_SHARP_FACTOR__SHIFT 0x00000018 + +// reg: VPDSCL_MANUAL_REPLICATE_CONTROL block: VPDSCL comp: amd.com/lib/vpdpp-vpep2gn/1.0 +#define VPDSCL_MANUAL_REPLICATE_CONTROL__SCL_V_MANUAL_REPLICATE_FACTOR__SHIFT 0x00000000 +#define VPDSCL_MANUAL_REPLICATE_CONTROL__SCL_H_MANUAL_REPLICATE_FACTOR__SHIFT 0x00000008 + +// reg: VPDSCL_HORZ_FILTER_SCALE_RATIO block: VPDSCL comp: amd.com/lib/vpdpp-vpep2gn/1.0 +#define VPDSCL_HORZ_FILTER_SCALE_RATIO__SCL_H_SCALE_RATIO__SHIFT 0x00000000 + +// reg: VPDSCL_HORZ_FILTER_INIT block: VPDSCL comp: amd.com/lib/vpdpp-vpep2gn/1.0 +#define VPDSCL_HORZ_FILTER_INIT__SCL_H_INIT_FRAC__SHIFT 0x00000000 +#define VPDSCL_HORZ_FILTER_INIT__SCL_H_INIT_INT__SHIFT 0x00000018 + +// reg: VPDSCL_HORZ_FILTER_SCALE_RATIO_C block: VPDSCL comp: amd.com/lib/vpdpp-vpep2gn/1.0 +#define VPDSCL_HORZ_FILTER_SCALE_RATIO_C__SCL_H_SCALE_RATIO_C__SHIFT 0x00000000 + +// reg: VPDSCL_HORZ_FILTER_INIT_C block: VPDSCL comp: amd.com/lib/vpdpp-vpep2gn/1.0 +#define VPDSCL_HORZ_FILTER_INIT_C__SCL_H_INIT_FRAC_C__SHIFT 0x00000000 +#define VPDSCL_HORZ_FILTER_INIT_C__SCL_H_INIT_INT_C__SHIFT 0x00000018 + +// reg: VPDSCL_VERT_FILTER_SCALE_RATIO block: VPDSCL comp: amd.com/lib/vpdpp-vpep2gn/1.0 +#define VPDSCL_VERT_FILTER_SCALE_RATIO__SCL_V_SCALE_RATIO__SHIFT 0x00000000 + +// reg: VPDSCL_VERT_FILTER_INIT block: VPDSCL comp: amd.com/lib/vpdpp-vpep2gn/1.0 +#define VPDSCL_VERT_FILTER_INIT__SCL_V_INIT_FRAC__SHIFT 0x00000000 +#define VPDSCL_VERT_FILTER_INIT__SCL_V_INIT_INT__SHIFT 0x00000018 + +// reg: VPDSCL_VERT_FILTER_INIT_BOT block: VPDSCL comp: amd.com/lib/vpdpp-vpep2gn/1.0 +#define VPDSCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_FRAC_BOT__SHIFT 0x00000000 +#define VPDSCL_VERT_FILTER_INIT_BOT__SCL_V_INIT_INT_BOT__SHIFT 0x00000018 + +// reg: VPDSCL_VERT_FILTER_SCALE_RATIO_C block: VPDSCL comp: amd.com/lib/vpdpp-vpep2gn/1.0 +#define VPDSCL_VERT_FILTER_SCALE_RATIO_C__SCL_V_SCALE_RATIO_C__SHIFT 0x00000000 + +// reg: VPDSCL_VERT_FILTER_INIT_C block: VPDSCL comp: amd.com/lib/vpdpp-vpep2gn/1.0 +#define VPDSCL_VERT_FILTER_INIT_C__SCL_V_INIT_FRAC_C__SHIFT 0x00000000 +#define VPDSCL_VERT_FILTER_INIT_C__SCL_V_INIT_INT_C__SHIFT 0x00000018 + +// reg: VPDSCL_VERT_FILTER_INIT_BOT_C block: VPDSCL comp: amd.com/lib/vpdpp-vpep2gn/1.0 +#define VPDSCL_VERT_FILTER_INIT_BOT_C__SCL_V_INIT_FRAC_BOT_C__SHIFT 0x00000000 +#define VPDSCL_VERT_FILTER_INIT_BOT_C__SCL_V_INIT_INT_BOT_C__SHIFT 0x00000018 + +// reg: VPDSCL_BLACK_COLOR block: VPDSCL comp: amd.com/lib/vpdpp-vpep2gn/1.0 +#define VPDSCL_BLACK_COLOR__SCL_BLACK_COLOR_RGB_Y__SHIFT 0x00000000 +#define VPDSCL_BLACK_COLOR__SCL_BLACK_COLOR_CBCR__SHIFT 0x00000010 + +// reg: VPDSCL_UPDATE block: VPDSCL comp: amd.com/lib/vpdpp-vpep2gn/1.0 +#define VPDSCL_UPDATE__SCL_UPDATE_PENDING__SHIFT 0x00000000 + +// reg: VPDSCL_AUTOCAL block: VPDSCL comp: amd.com/lib/vpdpp-vpep2gn/1.0 +#define VPDSCL_AUTOCAL__AUTOCAL_MODE__SHIFT 0x00000000 + +// reg: VPDSCL_EXT_OVERSCAN_LEFT_RIGHT block: VPDSCL comp: amd.com/lib/vpdpp-vpep2gn/1.0 +#define VPDSCL_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_RIGHT__SHIFT 0x00000000 +#define VPDSCL_EXT_OVERSCAN_LEFT_RIGHT__EXT_OVERSCAN_LEFT__SHIFT 0x00000010 + +// reg: VPDSCL_EXT_OVERSCAN_TOP_BOTTOM block: VPDSCL comp: amd.com/lib/vpdpp-vpep2gn/1.0 +#define VPDSCL_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_BOTTOM__SHIFT 0x00000000 +#define VPDSCL_EXT_OVERSCAN_TOP_BOTTOM__EXT_OVERSCAN_TOP__SHIFT 0x00000010 + +// reg: VPOTG_H_BLANK block: VPDSCL comp: amd.com/lib/vpdpp-vpep2gn/1.0 +#define VPOTG_H_BLANK__OTG_H_BLANK_START__SHIFT 0x00000000 +#define VPOTG_H_BLANK__OTG_H_BLANK_END__SHIFT 0x00000010 + +// reg: VPOTG_V_BLANK block: VPDSCL comp: amd.com/lib/vpdpp-vpep2gn/1.0 +#define VPOTG_V_BLANK__OTG_V_BLANK_START__SHIFT 0x00000000 +#define VPOTG_V_BLANK__OTG_V_BLANK_END__SHIFT 0x00000010 + +// reg: VPDSCL_RECOUT_START block: VPDSCL comp: amd.com/lib/vpdpp-vpep2gn/1.0 +#define VPDSCL_RECOUT_START__RECOUT_START_X__SHIFT 0x00000000 +#define VPDSCL_RECOUT_START__RECOUT_START_Y__SHIFT 0x00000010 + +// reg: VPDSCL_RECOUT_SIZE block: VPDSCL comp: amd.com/lib/vpdpp-vpep2gn/1.0 +#define VPDSCL_RECOUT_SIZE__RECOUT_WIDTH__SHIFT 0x00000000 +#define VPDSCL_RECOUT_SIZE__RECOUT_HEIGHT__SHIFT 0x00000010 + +// reg: VPMPC_SIZE block: VPDSCL comp: amd.com/lib/vpdpp-vpep2gn/1.0 +#define VPMPC_SIZE__VPMPC_WIDTH__SHIFT 0x00000000 +#define VPMPC_SIZE__VPMPC_HEIGHT__SHIFT 0x00000010 + +// reg: VPLB_DATA_FORMAT block: VPDSCL comp: amd.com/lib/vpdpp-vpep2gn/1.0 +#define VPLB_DATA_FORMAT__ALPHA_EN__SHIFT 0x00000004 + +// reg: VPLB_MEMORY_CTRL block: VPDSCL comp: amd.com/lib/vpdpp-vpep2gn/1.0 +#define VPLB_MEMORY_CTRL__LB_MAX_PARTITIONS__SHIFT 0x00000008 +#define VPLB_MEMORY_CTRL__LB_NUM_PARTITIONS__SHIFT 0x00000010 +#define VPLB_MEMORY_CTRL__LB_NUM_PARTITIONS_C__SHIFT 0x00000018 + +// reg: VPLB_V_COUNTER block: VPDSCL comp: amd.com/lib/vpdpp-vpep2gn/1.0 +#define VPLB_V_COUNTER__V_COUNTER__SHIFT 0x00000000 +#define VPLB_V_COUNTER__V_COUNTER_C__SHIFT 0x00000010 + +// reg: VPDSCL_MEM_PWR_CTRL block: VPDSCL comp: amd.com/lib/vpdpp-vpep2gn/1.0 +#define VPDSCL_MEM_PWR_CTRL__LUT_MEM_PWR_FORCE__SHIFT 0x00000000 +#define VPDSCL_MEM_PWR_CTRL__LUT_MEM_PWR_DIS__SHIFT 0x00000002 +#define VPDSCL_MEM_PWR_CTRL__LB_G1_MEM_PWR_FORCE__SHIFT 0x00000004 +#define VPDSCL_MEM_PWR_CTRL__LB_G1_MEM_PWR_DIS__SHIFT 0x00000006 +#define VPDSCL_MEM_PWR_CTRL__LB_G2_MEM_PWR_FORCE__SHIFT 0x00000008 +#define VPDSCL_MEM_PWR_CTRL__LB_G2_MEM_PWR_DIS__SHIFT 0x0000000a +#define VPDSCL_MEM_PWR_CTRL__LB_MEM_PWR_MODE__SHIFT 0x0000001c + +// reg: VPDSCL_MEM_PWR_STATUS block: VPDSCL comp: amd.com/lib/vpdpp-vpep2gn/1.0 +#define VPDSCL_MEM_PWR_STATUS__LUT_MEM_PWR_STATE__SHIFT 0x00000000 +#define VPDSCL_MEM_PWR_STATUS__LB_G1_MEM_PWR_STATE__SHIFT 0x00000002 +#define VPDSCL_MEM_PWR_STATUS__LB_G2_MEM_PWR_STATE__SHIFT 0x00000004 + +// reg: VPDSCL_EASF_H_MODE block: VPDSCL comp: amd.com/lib/vpdpp-vpep2gn/1.0 +#define VPDSCL_EASF_H_MODE__SCL_EASF_H_EN__SHIFT 0x00000000 +#define VPDSCL_EASF_H_MODE__SCL_EASF_H_RINGEST_FORCE_EN__SHIFT 0x00000004 +#define VPDSCL_EASF_H_MODE__SCL_EASF_H_2TAP_SHARP_FACTOR__SHIFT 0x00000008 + +// reg: VPDSCL_EASF_V_MODE block: VPDSCL comp: amd.com/lib/vpdpp-vpep2gn/1.0 +#define VPDSCL_EASF_V_MODE__SCL_EASF_V_EN__SHIFT 0x00000000 +#define VPDSCL_EASF_V_MODE__SCL_EASF_V_RINGEST_FORCE_EN__SHIFT 0x00000004 +#define VPDSCL_EASF_V_MODE__SCL_EASF_V_2TAP_SHARP_FACTOR__SHIFT 0x00000008 + +// reg: VPDSCL_SC_MODE block: VPDSCL comp: amd.com/lib/vpdpp-vpep2gn/1.0 +#define VPDSCL_SC_MODE__SCL_SC_MATRIX_MODE__SHIFT 0x00000000 +#define VPDSCL_SC_MODE__SCL_SC_LTONL_EN__SHIFT 0x00000008 + +// reg: VPDSCL_SC_MATRIX_C0C1 block: VPDSCL comp: amd.com/lib/vpdpp-vpep2gn/1.0 +#define VPDSCL_SC_MATRIX_C0C1__SCL_SC_MATRIX_C0__SHIFT 0x00000000 +#define VPDSCL_SC_MATRIX_C0C1__SCL_SC_MATRIX_C1__SHIFT 0x00000010 + +// reg: VPDSCL_SC_MATRIX_C2C3 block: VPDSCL comp: amd.com/lib/vpdpp-vpep2gn/1.0 +#define VPDSCL_SC_MATRIX_C2C3__SCL_SC_MATRIX_C2__SHIFT 0x00000000 +#define VPDSCL_SC_MATRIX_C2C3__SCL_SC_MATRIX_C3__SHIFT 0x00000010 + +// reg: VPDSCL_EASF_H_RINGEST_EVENTAP_GAIN block: VPDSCL comp: amd.com/lib/vpdpp-vpep2gn/1.0 +#define VPDSCL_EASF_H_RINGEST_EVENTAP_GAIN__SCL_EASF_H_RINGEST_EVENTAP_GAIN1__SHIFT 0x00000000 +#define VPDSCL_EASF_H_RINGEST_EVENTAP_GAIN__SCL_EASF_H_RINGEST_EVENTAP_GAIN2__SHIFT 0x00000010 + +// reg: VPDSCL_EASF_H_RINGEST_EVENTAP_REDUCE block: VPDSCL comp: amd.com/lib/vpdpp-vpep2gn/1.0 +#define VPDSCL_EASF_H_RINGEST_EVENTAP_REDUCE__SCL_EASF_H_RINGEST_EVENTAP_REDUCEG1__SHIFT 0x00000000 +#define VPDSCL_EASF_H_RINGEST_EVENTAP_REDUCE__SCL_EASF_H_RINGEST_EVENTAP_REDUCEG2__SHIFT 0x00000010 + +// reg: VPDSCL_EASF_V_RINGEST_EVENTAP_GAIN block: VPDSCL comp: amd.com/lib/vpdpp-vpep2gn/1.0 +#define VPDSCL_EASF_V_RINGEST_EVENTAP_GAIN__SCL_EASF_V_RINGEST_EVENTAP_GAIN1__SHIFT 0x00000000 +#define VPDSCL_EASF_V_RINGEST_EVENTAP_GAIN__SCL_EASF_V_RINGEST_EVENTAP_GAIN2__SHIFT 0x00000010 + +// reg: VPDSCL_EASF_V_RINGEST_EVENTAP_REDUCE block: VPDSCL comp: amd.com/lib/vpdpp-vpep2gn/1.0 +#define VPDSCL_EASF_V_RINGEST_EVENTAP_REDUCE__SCL_EASF_V_RINGEST_EVENTAP_REDUCEG1__SHIFT 0x00000000 +#define VPDSCL_EASF_V_RINGEST_EVENTAP_REDUCE__SCL_EASF_V_RINGEST_EVENTAP_REDUCEG2__SHIFT 0x00000010 + +// reg: VPDSCL_EASF_V_RINGEST_3TAP_CNTL1 block: VPDSCL comp: amd.com/lib/vpdpp-vpep2gn/1.0 +#define VPDSCL_EASF_V_RINGEST_3TAP_CNTL1__SCL_EASF_V_RINGEST_3TAP_DNTILT_UPTILT__SHIFT 0x00000000 +#define VPDSCL_EASF_V_RINGEST_3TAP_CNTL1__SCL_EASF_V_RINGEST_3TAP_UPTILT_MAXVAL__SHIFT 0x00000010 + +// reg: VPDSCL_EASF_V_RINGEST_3TAP_CNTL2 block: VPDSCL comp: amd.com/lib/vpdpp-vpep2gn/1.0 +#define VPDSCL_EASF_V_RINGEST_3TAP_CNTL2__SCL_EASF_V_RINGEST_3TAP_DNTILT_SLOPE__SHIFT 0x00000000 +#define VPDSCL_EASF_V_RINGEST_3TAP_CNTL2__SCL_EASF_V_RINGEST_3TAP_UPTILT1_SLOPE__SHIFT 0x00000010 + +// reg: VPDSCL_EASF_V_RINGEST_3TAP_CNTL3 block: VPDSCL comp: amd.com/lib/vpdpp-vpep2gn/1.0 +#define VPDSCL_EASF_V_RINGEST_3TAP_CNTL3__SCL_EASF_V_RINGEST_3TAP_UPTILT2_SLOPE__SHIFT 0x00000000 +#define VPDSCL_EASF_V_RINGEST_3TAP_CNTL3__SCL_EASF_V_RINGEST_3TAP_UPTILT2_OFFSET__SHIFT 0x00000010 + +// reg: VPDSCL_EASF_RINGEST_FORCE block: VPDSCL comp: amd.com/lib/vpdpp-vpep2gn/1.0 +#define VPDSCL_EASF_RINGEST_FORCE__SCL_EASF_H_RINGEST_FORCE__SHIFT 0x00000000 +#define VPDSCL_EASF_RINGEST_FORCE__SCL_EASF_V_RINGEST_FORCE__SHIFT 0x00000010 + +// reg: VPDSCL_EASF_H_BF_CNTL block: VPDSCL comp: amd.com/lib/vpdpp-vpep2gn/1.0 +#define VPDSCL_EASF_H_BF_CNTL__SCL_EASF_H_BF1_EN__SHIFT 0x00000000 +#define VPDSCL_EASF_H_BF_CNTL__SCL_EASF_H_BF2_MODE__SHIFT 0x00000008 +#define VPDSCL_EASF_H_BF_CNTL__SCL_EASF_H_BF3_MODE__SHIFT 0x00000010 +#define VPDSCL_EASF_H_BF_CNTL__SCL_EASF_H_BF2_FLAT1_GAIN__SHIFT 0x00000014 +#define VPDSCL_EASF_H_BF_CNTL__SCL_EASF_H_BF2_FLAT2_GAIN__SHIFT 0x00000018 +#define VPDSCL_EASF_H_BF_CNTL__SCL_EASF_H_BF2_ROC_GAIN__SHIFT 0x0000001c + +// reg: VPDSCL_EASF_H_BF_FINAL_MAX_MIN block: VPDSCL comp: amd.com/lib/vpdpp-vpep2gn/1.0 +#define VPDSCL_EASF_H_BF_FINAL_MAX_MIN__SCL_EASF_H_BF_MAXA__SHIFT 0x00000000 +#define VPDSCL_EASF_H_BF_FINAL_MAX_MIN__SCL_EASF_H_BF_MAXB__SHIFT 0x00000008 +#define VPDSCL_EASF_H_BF_FINAL_MAX_MIN__SCL_EASF_H_BF_MINA__SHIFT 0x00000010 +#define VPDSCL_EASF_H_BF_FINAL_MAX_MIN__SCL_EASF_H_BF_MINB__SHIFT 0x00000018 + +// reg: VPDSCL_EASF_V_BF_CNTL block: VPDSCL comp: amd.com/lib/vpdpp-vpep2gn/1.0 +#define VPDSCL_EASF_V_BF_CNTL__SCL_EASF_V_BF1_EN__SHIFT 0x00000000 +#define VPDSCL_EASF_V_BF_CNTL__SCL_EASF_V_BF2_MODE__SHIFT 0x00000008 +#define VPDSCL_EASF_V_BF_CNTL__SCL_EASF_V_BF3_MODE__SHIFT 0x00000010 +#define VPDSCL_EASF_V_BF_CNTL__SCL_EASF_V_BF2_FLAT1_GAIN__SHIFT 0x00000014 +#define VPDSCL_EASF_V_BF_CNTL__SCL_EASF_V_BF2_FLAT2_GAIN__SHIFT 0x00000018 +#define VPDSCL_EASF_V_BF_CNTL__SCL_EASF_V_BF2_ROC_GAIN__SHIFT 0x0000001c + +// reg: VPDSCL_EASF_H_BF1_PWL_SEG0 block: VPDSCL comp: amd.com/lib/vpdpp-vpep2gn/1.0 +#define VPDSCL_EASF_H_BF1_PWL_SEG0__SCL_EASF_H_BF1_PWL_IN_SEG0__SHIFT 0x00000000 +#define VPDSCL_EASF_H_BF1_PWL_SEG0__SCL_EASF_H_BF1_PWL_BASE_SEG0__SHIFT 0x0000000c +#define VPDSCL_EASF_H_BF1_PWL_SEG0__SCL_EASF_H_BF1_PWL_SLOPE_SEG0__SHIFT 0x00000014 + +// reg: VPDSCL_EASF_H_BF1_PWL_SEG1 block: VPDSCL comp: amd.com/lib/vpdpp-vpep2gn/1.0 +#define VPDSCL_EASF_H_BF1_PWL_SEG1__SCL_EASF_H_BF1_PWL_IN_SEG1__SHIFT 0x00000000 +#define VPDSCL_EASF_H_BF1_PWL_SEG1__SCL_EASF_H_BF1_PWL_BASE_SEG1__SHIFT 0x0000000c +#define VPDSCL_EASF_H_BF1_PWL_SEG1__SCL_EASF_H_BF1_PWL_SLOPE_SEG1__SHIFT 0x00000014 + +// reg: VPDSCL_EASF_H_BF1_PWL_SEG2 block: VPDSCL comp: amd.com/lib/vpdpp-vpep2gn/1.0 +#define VPDSCL_EASF_H_BF1_PWL_SEG2__SCL_EASF_H_BF1_PWL_IN_SEG2__SHIFT 0x00000000 +#define VPDSCL_EASF_H_BF1_PWL_SEG2__SCL_EASF_H_BF1_PWL_BASE_SEG2__SHIFT 0x0000000c +#define VPDSCL_EASF_H_BF1_PWL_SEG2__SCL_EASF_H_BF1_PWL_SLOPE_SEG2__SHIFT 0x00000014 + +// reg: VPDSCL_EASF_H_BF1_PWL_SEG3 block: VPDSCL comp: amd.com/lib/vpdpp-vpep2gn/1.0 +#define VPDSCL_EASF_H_BF1_PWL_SEG3__SCL_EASF_H_BF1_PWL_IN_SEG3__SHIFT 0x00000000 +#define VPDSCL_EASF_H_BF1_PWL_SEG3__SCL_EASF_H_BF1_PWL_BASE_SEG3__SHIFT 0x0000000c +#define VPDSCL_EASF_H_BF1_PWL_SEG3__SCL_EASF_H_BF1_PWL_SLOPE_SEG3__SHIFT 0x00000014 + +// reg: VPDSCL_EASF_H_BF1_PWL_SEG4 block: VPDSCL comp: amd.com/lib/vpdpp-vpep2gn/1.0 +#define VPDSCL_EASF_H_BF1_PWL_SEG4__SCL_EASF_H_BF1_PWL_IN_SEG4__SHIFT 0x00000000 +#define VPDSCL_EASF_H_BF1_PWL_SEG4__SCL_EASF_H_BF1_PWL_BASE_SEG4__SHIFT 0x0000000c +#define VPDSCL_EASF_H_BF1_PWL_SEG4__SCL_EASF_H_BF1_PWL_SLOPE_SEG4__SHIFT 0x00000014 + +// reg: VPDSCL_EASF_H_BF1_PWL_SEG5 block: VPDSCL comp: amd.com/lib/vpdpp-vpep2gn/1.0 +#define VPDSCL_EASF_H_BF1_PWL_SEG5__SCL_EASF_H_BF1_PWL_IN_SEG5__SHIFT 0x00000000 +#define VPDSCL_EASF_H_BF1_PWL_SEG5__SCL_EASF_H_BF1_PWL_BASE_SEG5__SHIFT 0x0000000c +#define VPDSCL_EASF_H_BF1_PWL_SEG5__SCL_EASF_H_BF1_PWL_SLOPE_SEG5__SHIFT 0x00000014 + +// reg: VPDSCL_EASF_H_BF1_PWL_SEG6 block: VPDSCL comp: amd.com/lib/vpdpp-vpep2gn/1.0 +#define VPDSCL_EASF_H_BF1_PWL_SEG6__SCL_EASF_H_BF1_PWL_IN_SEG6__SHIFT 0x00000000 +#define VPDSCL_EASF_H_BF1_PWL_SEG6__SCL_EASF_H_BF1_PWL_BASE_SEG6__SHIFT 0x0000000c +#define VPDSCL_EASF_H_BF1_PWL_SEG6__SCL_EASF_H_BF1_PWL_SLOPE_SEG6__SHIFT 0x00000014 + +// reg: VPDSCL_EASF_H_BF1_PWL_SEG7 block: VPDSCL comp: amd.com/lib/vpdpp-vpep2gn/1.0 +#define VPDSCL_EASF_H_BF1_PWL_SEG7__SCL_EASF_H_BF1_PWL_IN_SEG7__SHIFT 0x00000000 +#define VPDSCL_EASF_H_BF1_PWL_SEG7__SCL_EASF_H_BF1_PWL_BASE_SEG7__SHIFT 0x0000000c + +// reg: VPDSCL_EASF_V_BF1_PWL_SEG0 block: VPDSCL comp: amd.com/lib/vpdpp-vpep2gn/1.0 +#define VPDSCL_EASF_V_BF1_PWL_SEG0__SCL_EASF_V_BF1_PWL_IN_SEG0__SHIFT 0x00000000 +#define VPDSCL_EASF_V_BF1_PWL_SEG0__SCL_EASF_V_BF1_PWL_BASE_SEG0__SHIFT 0x0000000c +#define VPDSCL_EASF_V_BF1_PWL_SEG0__SCL_EASF_V_BF1_PWL_SLOPE_SEG0__SHIFT 0x00000014 + +// reg: VPDSCL_EASF_V_BF1_PWL_SEG1 block: VPDSCL comp: amd.com/lib/vpdpp-vpep2gn/1.0 +#define VPDSCL_EASF_V_BF1_PWL_SEG1__SCL_EASF_V_BF1_PWL_IN_SEG1__SHIFT 0x00000000 +#define VPDSCL_EASF_V_BF1_PWL_SEG1__SCL_EASF_V_BF1_PWL_BASE_SEG1__SHIFT 0x0000000c +#define VPDSCL_EASF_V_BF1_PWL_SEG1__SCL_EASF_V_BF1_PWL_SLOPE_SEG1__SHIFT 0x00000014 + +// reg: VPDSCL_EASF_V_BF1_PWL_SEG2 block: VPDSCL comp: amd.com/lib/vpdpp-vpep2gn/1.0 +#define VPDSCL_EASF_V_BF1_PWL_SEG2__SCL_EASF_V_BF1_PWL_IN_SEG2__SHIFT 0x00000000 +#define VPDSCL_EASF_V_BF1_PWL_SEG2__SCL_EASF_V_BF1_PWL_BASE_SEG2__SHIFT 0x0000000c +#define VPDSCL_EASF_V_BF1_PWL_SEG2__SCL_EASF_V_BF1_PWL_SLOPE_SEG2__SHIFT 0x00000014 + +// reg: VPDSCL_EASF_V_BF1_PWL_SEG3 block: VPDSCL comp: amd.com/lib/vpdpp-vpep2gn/1.0 +#define VPDSCL_EASF_V_BF1_PWL_SEG3__SCL_EASF_V_BF1_PWL_IN_SEG3__SHIFT 0x00000000 +#define VPDSCL_EASF_V_BF1_PWL_SEG3__SCL_EASF_V_BF1_PWL_BASE_SEG3__SHIFT 0x0000000c +#define VPDSCL_EASF_V_BF1_PWL_SEG3__SCL_EASF_V_BF1_PWL_SLOPE_SEG3__SHIFT 0x00000014 + +// reg: VPDSCL_EASF_V_BF1_PWL_SEG4 block: VPDSCL comp: amd.com/lib/vpdpp-vpep2gn/1.0 +#define VPDSCL_EASF_V_BF1_PWL_SEG4__SCL_EASF_V_BF1_PWL_IN_SEG4__SHIFT 0x00000000 +#define VPDSCL_EASF_V_BF1_PWL_SEG4__SCL_EASF_V_BF1_PWL_BASE_SEG4__SHIFT 0x0000000c +#define VPDSCL_EASF_V_BF1_PWL_SEG4__SCL_EASF_V_BF1_PWL_SLOPE_SEG4__SHIFT 0x00000014 + +// reg: VPDSCL_EASF_V_BF1_PWL_SEG5 block: VPDSCL comp: amd.com/lib/vpdpp-vpep2gn/1.0 +#define VPDSCL_EASF_V_BF1_PWL_SEG5__SCL_EASF_V_BF1_PWL_IN_SEG5__SHIFT 0x00000000 +#define VPDSCL_EASF_V_BF1_PWL_SEG5__SCL_EASF_V_BF1_PWL_BASE_SEG5__SHIFT 0x0000000c +#define VPDSCL_EASF_V_BF1_PWL_SEG5__SCL_EASF_V_BF1_PWL_SLOPE_SEG5__SHIFT 0x00000014 + +// reg: VPDSCL_EASF_V_BF1_PWL_SEG6 block: VPDSCL comp: amd.com/lib/vpdpp-vpep2gn/1.0 +#define VPDSCL_EASF_V_BF1_PWL_SEG6__SCL_EASF_V_BF1_PWL_IN_SEG6__SHIFT 0x00000000 +#define VPDSCL_EASF_V_BF1_PWL_SEG6__SCL_EASF_V_BF1_PWL_BASE_SEG6__SHIFT 0x0000000c +#define VPDSCL_EASF_V_BF1_PWL_SEG6__SCL_EASF_V_BF1_PWL_SLOPE_SEG6__SHIFT 0x00000014 + +// reg: VPDSCL_EASF_V_BF1_PWL_SEG7 block: VPDSCL comp: amd.com/lib/vpdpp-vpep2gn/1.0 +#define VPDSCL_EASF_V_BF1_PWL_SEG7__SCL_EASF_V_BF1_PWL_IN_SEG7__SHIFT 0x00000000 +#define VPDSCL_EASF_V_BF1_PWL_SEG7__SCL_EASF_V_BF1_PWL_BASE_SEG7__SHIFT 0x0000000c + +// reg: VPDSCL_EASF_H_BF3_PWL_SEG0 block: VPDSCL comp: amd.com/lib/vpdpp-vpep2gn/1.0 +#define VPDSCL_EASF_H_BF3_PWL_SEG0__SCL_EASF_H_BF3_PWL_IN_SEG0__SHIFT 0x00000000 +#define VPDSCL_EASF_H_BF3_PWL_SEG0__SCL_EASF_H_BF3_PWL_BASE_SEG0__SHIFT 0x0000000c +#define VPDSCL_EASF_H_BF3_PWL_SEG0__SCL_EASF_H_BF3_PWL_SLOPE_SEG0__SHIFT 0x00000013 + +// reg: VPDSCL_EASF_H_BF3_PWL_SEG1 block: VPDSCL comp: amd.com/lib/vpdpp-vpep2gn/1.0 +#define VPDSCL_EASF_H_BF3_PWL_SEG1__SCL_EASF_H_BF3_PWL_IN_SEG1__SHIFT 0x00000000 +#define VPDSCL_EASF_H_BF3_PWL_SEG1__SCL_EASF_H_BF3_PWL_BASE_SEG1__SHIFT 0x0000000c +#define VPDSCL_EASF_H_BF3_PWL_SEG1__SCL_EASF_H_BF3_PWL_SLOPE_SEG1__SHIFT 0x00000013 + +// reg: VPDSCL_EASF_H_BF3_PWL_SEG2 block: VPDSCL comp: amd.com/lib/vpdpp-vpep2gn/1.0 +#define VPDSCL_EASF_H_BF3_PWL_SEG2__SCL_EASF_H_BF3_PWL_IN_SEG2__SHIFT 0x00000000 +#define VPDSCL_EASF_H_BF3_PWL_SEG2__SCL_EASF_H_BF3_PWL_BASE_SEG2__SHIFT 0x0000000c +#define VPDSCL_EASF_H_BF3_PWL_SEG2__SCL_EASF_H_BF3_PWL_SLOPE_SEG2__SHIFT 0x00000013 + +// reg: VPDSCL_EASF_H_BF3_PWL_SEG3 block: VPDSCL comp: amd.com/lib/vpdpp-vpep2gn/1.0 +#define VPDSCL_EASF_H_BF3_PWL_SEG3__SCL_EASF_H_BF3_PWL_IN_SEG3__SHIFT 0x00000000 +#define VPDSCL_EASF_H_BF3_PWL_SEG3__SCL_EASF_H_BF3_PWL_BASE_SEG3__SHIFT 0x0000000c +#define VPDSCL_EASF_H_BF3_PWL_SEG3__SCL_EASF_H_BF3_PWL_SLOPE_SEG3__SHIFT 0x00000013 + +// reg: VPDSCL_EASF_H_BF3_PWL_SEG4 block: VPDSCL comp: amd.com/lib/vpdpp-vpep2gn/1.0 +#define VPDSCL_EASF_H_BF3_PWL_SEG4__SCL_EASF_H_BF3_PWL_IN_SEG4__SHIFT 0x00000000 +#define VPDSCL_EASF_H_BF3_PWL_SEG4__SCL_EASF_H_BF3_PWL_BASE_SEG4__SHIFT 0x0000000c +#define VPDSCL_EASF_H_BF3_PWL_SEG4__SCL_EASF_H_BF3_PWL_SLOPE_SEG4__SHIFT 0x00000013 + +// reg: VPDSCL_EASF_H_BF3_PWL_SEG5 block: VPDSCL comp: amd.com/lib/vpdpp-vpep2gn/1.0 +#define VPDSCL_EASF_H_BF3_PWL_SEG5__SCL_EASF_H_BF3_PWL_IN_SEG5__SHIFT 0x00000000 +#define VPDSCL_EASF_H_BF3_PWL_SEG5__SCL_EASF_H_BF3_PWL_BASE_SEG5__SHIFT 0x0000000c + +// reg: VPDSCL_EASF_V_BF3_PWL_SEG0 block: VPDSCL comp: amd.com/lib/vpdpp-vpep2gn/1.0 +#define VPDSCL_EASF_V_BF3_PWL_SEG0__SCL_EASF_V_BF3_PWL_IN_SEG0__SHIFT 0x00000000 +#define VPDSCL_EASF_V_BF3_PWL_SEG0__SCL_EASF_V_BF3_PWL_BASE_SEG0__SHIFT 0x0000000c +#define VPDSCL_EASF_V_BF3_PWL_SEG0__SCL_EASF_V_BF3_PWL_SLOPE_SEG0__SHIFT 0x00000013 + +// reg: VPDSCL_EASF_V_BF3_PWL_SEG1 block: VPDSCL comp: amd.com/lib/vpdpp-vpep2gn/1.0 +#define VPDSCL_EASF_V_BF3_PWL_SEG1__SCL_EASF_V_BF3_PWL_IN_SEG1__SHIFT 0x00000000 +#define VPDSCL_EASF_V_BF3_PWL_SEG1__SCL_EASF_V_BF3_PWL_BASE_SEG1__SHIFT 0x0000000c +#define VPDSCL_EASF_V_BF3_PWL_SEG1__SCL_EASF_V_BF3_PWL_SLOPE_SEG1__SHIFT 0x00000013 + +// reg: VPDSCL_EASF_V_BF3_PWL_SEG2 block: VPDSCL comp: amd.com/lib/vpdpp-vpep2gn/1.0 +#define VPDSCL_EASF_V_BF3_PWL_SEG2__SCL_EASF_V_BF3_PWL_IN_SEG2__SHIFT 0x00000000 +#define VPDSCL_EASF_V_BF3_PWL_SEG2__SCL_EASF_V_BF3_PWL_BASE_SEG2__SHIFT 0x0000000c +#define VPDSCL_EASF_V_BF3_PWL_SEG2__SCL_EASF_V_BF3_PWL_SLOPE_SEG2__SHIFT 0x00000013 + +// reg: VPDSCL_EASF_V_BF3_PWL_SEG3 block: VPDSCL comp: amd.com/lib/vpdpp-vpep2gn/1.0 +#define VPDSCL_EASF_V_BF3_PWL_SEG3__SCL_EASF_V_BF3_PWL_IN_SEG3__SHIFT 0x00000000 +#define VPDSCL_EASF_V_BF3_PWL_SEG3__SCL_EASF_V_BF3_PWL_BASE_SEG3__SHIFT 0x0000000c +#define VPDSCL_EASF_V_BF3_PWL_SEG3__SCL_EASF_V_BF3_PWL_SLOPE_SEG3__SHIFT 0x00000013 + +// reg: VPDSCL_EASF_V_BF3_PWL_SEG4 block: VPDSCL comp: amd.com/lib/vpdpp-vpep2gn/1.0 +#define VPDSCL_EASF_V_BF3_PWL_SEG4__SCL_EASF_V_BF3_PWL_IN_SEG4__SHIFT 0x00000000 +#define VPDSCL_EASF_V_BF3_PWL_SEG4__SCL_EASF_V_BF3_PWL_BASE_SEG4__SHIFT 0x0000000c +#define VPDSCL_EASF_V_BF3_PWL_SEG4__SCL_EASF_V_BF3_PWL_SLOPE_SEG4__SHIFT 0x00000013 + +// reg: VPDSCL_EASF_V_BF3_PWL_SEG5 block: VPDSCL comp: amd.com/lib/vpdpp-vpep2gn/1.0 +#define VPDSCL_EASF_V_BF3_PWL_SEG5__SCL_EASF_V_BF3_PWL_IN_SEG5__SHIFT 0x00000000 +#define VPDSCL_EASF_V_BF3_PWL_SEG5__SCL_EASF_V_BF3_PWL_BASE_SEG5__SHIFT 0x0000000c + +// reg: VPISHARP_MODE block: VPDSCL comp: amd.com/lib/vpdpp-vpep2gn/1.0 +#define VPISHARP_MODE__ISHARP_EN__SHIFT 0x00000000 +#define VPISHARP_MODE__ISHARP_NOISEDET_EN__SHIFT 0x00000004 +#define VPISHARP_MODE__ISHARP_NOISEDET_MODE__SHIFT 0x00000005 +#define VPISHARP_MODE__ISHARP_LBA_MODE__SHIFT 0x00000009 +#define VPISHARP_MODE__ISHARP_FMT_MODE__SHIFT 0x0000000b +#define VPISHARP_MODE__ISHARP_FMT_NORM__SHIFT 0x0000000c +#define VPISHARP_MODE__ISHARP_DELTA_LUT_SELECT_CURRENT__SHIFT 0x0000001c + +// reg: VPISHARP_DELTA_CTRL block: VPDSCL comp: amd.com/lib/vpdpp-vpep2gn/1.0 +#define VPISHARP_DELTA_CTRL__ISHARP_DELTA_LUT_HOST_SELECT__SHIFT 0x00000000 + +// reg: VPISHARP_DELTA_INDEX block: VPDSCL comp: amd.com/lib/vpdpp-vpep2gn/1.0 +#define VPISHARP_DELTA_INDEX__ISHARP_DELTA_INDEX__SHIFT 0x00000000 + +// reg: VPISHARP_DELTA_DATA block: VPDSCL comp: amd.com/lib/vpdpp-vpep2gn/1.0 +#define VPISHARP_DELTA_DATA__ISHARP_DELTA_DATA__SHIFT 0x00000000 + +// reg: VPISHARP_NLDELTA_SOFT_CLIP block: VPDSCL comp: amd.com/lib/vpdpp-vpep2gn/1.0 +#define VPISHARP_NLDELTA_SOFT_CLIP__ISHARP_NLDELTA_SCLIP_EN_P__SHIFT 0x00000000 +#define VPISHARP_NLDELTA_SOFT_CLIP__ISHARP_NLDELTA_SCLIP_PIVOT_P__SHIFT 0x00000001 +#define VPISHARP_NLDELTA_SOFT_CLIP__ISHARP_NLDELTA_SCLIP_SLOPE_P__SHIFT 0x00000008 +#define VPISHARP_NLDELTA_SOFT_CLIP__ISHARP_NLDELTA_SCLIP_EN_N__SHIFT 0x00000010 +#define VPISHARP_NLDELTA_SOFT_CLIP__ISHARP_NLDELTA_SCLIP_PIVOT_N__SHIFT 0x00000011 +#define VPISHARP_NLDELTA_SOFT_CLIP__ISHARP_NLDELTA_SCLIP_SLOPE_N__SHIFT 0x00000018 + +// reg: VPISHARP_NOISEDET_THRESHOLD block: VPDSCL comp: amd.com/lib/vpdpp-vpep2gn/1.0 +#define VPISHARP_NOISEDET_THRESHOLD__ISHARP_NOISEDET_UTHRE__SHIFT 0x00000000 +#define VPISHARP_NOISEDET_THRESHOLD__ISHARP_NOISEDET_DTHRE__SHIFT 0x00000010 + +// reg: VPISHARP_NOISE_GAIN_PWL block: VPDSCL comp: amd.com/lib/vpdpp-vpep2gn/1.0 +#define VPISHARP_NOISE_GAIN_PWL__ISHARP_NOISEDET_PWL_START_IN__SHIFT 0x00000000 +#define VPISHARP_NOISE_GAIN_PWL__ISHARP_NOISEDET_PWL_END_IN__SHIFT 0x00000008 +#define VPISHARP_NOISE_GAIN_PWL__ISHARP_NOISEDET_PWL_SLOPE__SHIFT 0x00000010 + +// reg: VPISHARP_LBA_PWL_SEG0 block: VPDSCL comp: amd.com/lib/vpdpp-vpep2gn/1.0 +#define VPISHARP_LBA_PWL_SEG0__ISHARP_LBA_PWL_IN_SEG0__SHIFT 0x00000000 +#define VPISHARP_LBA_PWL_SEG0__ISHARP_LBA_PWL_BASE_SEG0__SHIFT 0x0000000c +#define VPISHARP_LBA_PWL_SEG0__ISHARP_LBA_PWL_SLOPE_SEG0__SHIFT 0x00000014 + +// reg: VPISHARP_LBA_PWL_SEG1 block: VPDSCL comp: amd.com/lib/vpdpp-vpep2gn/1.0 +#define VPISHARP_LBA_PWL_SEG1__ISHARP_LBA_PWL_IN_SEG1__SHIFT 0x00000000 +#define VPISHARP_LBA_PWL_SEG1__ISHARP_LBA_PWL_BASE_SEG1__SHIFT 0x0000000c +#define VPISHARP_LBA_PWL_SEG1__ISHARP_LBA_PWL_SLOPE_SEG1__SHIFT 0x00000014 + +// reg: VPISHARP_LBA_PWL_SEG2 block: VPDSCL comp: amd.com/lib/vpdpp-vpep2gn/1.0 +#define VPISHARP_LBA_PWL_SEG2__ISHARP_LBA_PWL_IN_SEG2__SHIFT 0x00000000 +#define VPISHARP_LBA_PWL_SEG2__ISHARP_LBA_PWL_BASE_SEG2__SHIFT 0x0000000c +#define VPISHARP_LBA_PWL_SEG2__ISHARP_LBA_PWL_SLOPE_SEG2__SHIFT 0x00000014 + +// reg: VPISHARP_LBA_PWL_SEG3 block: VPDSCL comp: amd.com/lib/vpdpp-vpep2gn/1.0 +#define VPISHARP_LBA_PWL_SEG3__ISHARP_LBA_PWL_IN_SEG3__SHIFT 0x00000000 +#define VPISHARP_LBA_PWL_SEG3__ISHARP_LBA_PWL_BASE_SEG3__SHIFT 0x0000000c +#define VPISHARP_LBA_PWL_SEG3__ISHARP_LBA_PWL_SLOPE_SEG3__SHIFT 0x00000014 + +// reg: VPISHARP_LBA_PWL_SEG4 block: VPDSCL comp: amd.com/lib/vpdpp-vpep2gn/1.0 +#define VPISHARP_LBA_PWL_SEG4__ISHARP_LBA_PWL_IN_SEG4__SHIFT 0x00000000 +#define VPISHARP_LBA_PWL_SEG4__ISHARP_LBA_PWL_BASE_SEG4__SHIFT 0x0000000c +#define VPISHARP_LBA_PWL_SEG4__ISHARP_LBA_PWL_SLOPE_SEG4__SHIFT 0x00000014 + +// reg: VPISHARP_LBA_PWL_SEG5 block: VPDSCL comp: amd.com/lib/vpdpp-vpep2gn/1.0 +#define VPISHARP_LBA_PWL_SEG5__ISHARP_LBA_PWL_IN_SEG5__SHIFT 0x00000000 +#define VPISHARP_LBA_PWL_SEG5__ISHARP_LBA_PWL_BASE_SEG5__SHIFT 0x0000000c + +// reg: VPISHARP_DELTA_LUT_MEM_PWR_CTRL block: VPDSCL comp: amd.com/lib/vpdpp-vpep2gn/1.0 +#define VPISHARP_DELTA_LUT_MEM_PWR_CTRL__ISHARP_DELTA_LUT_MEM_PWR_FORCE__SHIFT 0x00000000 +#define VPISHARP_DELTA_LUT_MEM_PWR_CTRL__ISHARP_DELTA_LUT_MEM_PWR_DIS__SHIFT 0x00000002 +#define VPISHARP_DELTA_LUT_MEM_PWR_CTRL__ISHARP_DELTA_LUT_MEM_PWR_STATE__SHIFT 0x00000004 + +// reg: VPCM_CONTROL block: VPCM comp: amd.com/lib/vpdpp-vpep2gn/1.0 +#define VPCM_CONTROL__VPCM_BYPASS__SHIFT 0x00000000 +#define VPCM_CONTROL__VPCM_UPDATE_PENDING__SHIFT 0x00000008 + +// reg: VPCM_POST_CSC_CONTROL block: VPCM comp: amd.com/lib/vpdpp-vpep2gn/1.0 +#define VPCM_POST_CSC_CONTROL__VPCM_POST_CSC_MODE__SHIFT 0x00000000 +#define VPCM_POST_CSC_CONTROL__VPCM_POST_CSC_MODE_CURRENT__SHIFT 0x00000002 + +// reg: VPCM_POST_CSC_C11_C12 block: VPCM comp: amd.com/lib/vpdpp-vpep2gn/1.0 +#define VPCM_POST_CSC_C11_C12__VPCM_POST_CSC_C11__SHIFT 0x00000000 +#define VPCM_POST_CSC_C11_C12__VPCM_POST_CSC_C12__SHIFT 0x00000010 + +// reg: VPCM_POST_CSC_C13_C14 block: VPCM comp: amd.com/lib/vpdpp-vpep2gn/1.0 +#define VPCM_POST_CSC_C13_C14__VPCM_POST_CSC_C13__SHIFT 0x00000000 +#define VPCM_POST_CSC_C13_C14__VPCM_POST_CSC_C14__SHIFT 0x00000010 + +// reg: VPCM_POST_CSC_C21_C22 block: VPCM comp: amd.com/lib/vpdpp-vpep2gn/1.0 +#define VPCM_POST_CSC_C21_C22__VPCM_POST_CSC_C21__SHIFT 0x00000000 +#define VPCM_POST_CSC_C21_C22__VPCM_POST_CSC_C22__SHIFT 0x00000010 + +// reg: VPCM_POST_CSC_C23_C24 block: VPCM comp: amd.com/lib/vpdpp-vpep2gn/1.0 +#define VPCM_POST_CSC_C23_C24__VPCM_POST_CSC_C23__SHIFT 0x00000000 +#define VPCM_POST_CSC_C23_C24__VPCM_POST_CSC_C24__SHIFT 0x00000010 + +// reg: VPCM_POST_CSC_C31_C32 block: VPCM comp: amd.com/lib/vpdpp-vpep2gn/1.0 +#define VPCM_POST_CSC_C31_C32__VPCM_POST_CSC_C31__SHIFT 0x00000000 +#define VPCM_POST_CSC_C31_C32__VPCM_POST_CSC_C32__SHIFT 0x00000010 + +// reg: VPCM_POST_CSC_C33_C34 block: VPCM comp: amd.com/lib/vpdpp-vpep2gn/1.0 +#define VPCM_POST_CSC_C33_C34__VPCM_POST_CSC_C33__SHIFT 0x00000000 +#define VPCM_POST_CSC_C33_C34__VPCM_POST_CSC_C34__SHIFT 0x00000010 + +// reg: VPCM_BIAS_CR_R block: VPCM comp: amd.com/lib/vpdpp-vpep2gn/1.0 +#define VPCM_BIAS_CR_R__VPCM_BIAS_CR_R__SHIFT 0x00000000 + +// reg: VPCM_BIAS_Y_G_CB_B block: VPCM comp: amd.com/lib/vpdpp-vpep2gn/1.0 +#define VPCM_BIAS_Y_G_CB_B__VPCM_BIAS_Y_G__SHIFT 0x00000000 +#define VPCM_BIAS_Y_G_CB_B__VPCM_BIAS_CB_B__SHIFT 0x00000010 + +// reg: VPCM_GAMCOR_CONTROL block: VPCM comp: amd.com/lib/vpdpp-vpep2gn/1.0 +#define VPCM_GAMCOR_CONTROL__VPCM_GAMCOR_MODE__SHIFT 0x00000000 +#define VPCM_GAMCOR_CONTROL__VPCM_GAMCOR_PWL_DISABLE__SHIFT 0x00000003 +#define VPCM_GAMCOR_CONTROL__VPCM_GAMCOR_MODE_CURRENT__SHIFT 0x00000004 +#define VPCM_GAMCOR_CONTROL__VPCM_GAMCOR_SELECT_CURRENT__SHIFT 0x00000006 + +// reg: VPCM_GAMCOR_LUT_INDEX block: VPCM comp: amd.com/lib/vpdpp-vpep2gn/1.0 +#define VPCM_GAMCOR_LUT_INDEX__VPCM_GAMCOR_LUT_INDEX__SHIFT 0x00000000 + +// reg: VPCM_GAMCOR_LUT_DATA block: VPCM comp: amd.com/lib/vpdpp-vpep2gn/1.0 +#define VPCM_GAMCOR_LUT_DATA__VPCM_GAMCOR_LUT_DATA__SHIFT 0x00000000 + +// reg: VPCM_GAMCOR_LUT_CONTROL block: VPCM comp: amd.com/lib/vpdpp-vpep2gn/1.0 +#define VPCM_GAMCOR_LUT_CONTROL__VPCM_GAMCOR_LUT_WRITE_COLOR_MASK__SHIFT 0x00000000 +#define VPCM_GAMCOR_LUT_CONTROL__VPCM_GAMCOR_LUT_READ_COLOR_SEL__SHIFT 0x00000003 +#define VPCM_GAMCOR_LUT_CONTROL__VPCM_GAMCOR_LUT_READ_DBG__SHIFT 0x00000005 +#define VPCM_GAMCOR_LUT_CONTROL__VPCM_GAMCOR_LUT_HOST_SEL__SHIFT 0x00000006 +#define VPCM_GAMCOR_LUT_CONTROL__VPCM_GAMCOR_LUT_CONFIG_MODE__SHIFT 0x00000007 + +// reg: VPCM_GAMCOR_RAMA_START_CNTL_B block: VPCM comp: amd.com/lib/vpdpp-vpep2gn/1.0 +#define VPCM_GAMCOR_RAMA_START_CNTL_B__VPCM_GAMCOR_RAMA_EXP_REGION_START_B__SHIFT 0x00000000 +#define VPCM_GAMCOR_RAMA_START_CNTL_B__VPCM_GAMCOR_RAMA_EXP_REGION_START_SEGMENT_B__SHIFT 0x00000014 + +// reg: VPCM_GAMCOR_RAMA_START_CNTL_G block: VPCM comp: amd.com/lib/vpdpp-vpep2gn/1.0 +#define VPCM_GAMCOR_RAMA_START_CNTL_G__VPCM_GAMCOR_RAMA_EXP_REGION_START_G__SHIFT 0x00000000 +#define VPCM_GAMCOR_RAMA_START_CNTL_G__VPCM_GAMCOR_RAMA_EXP_REGION_START_SEGMENT_G__SHIFT 0x00000014 + +// reg: VPCM_GAMCOR_RAMA_START_CNTL_R block: VPCM comp: amd.com/lib/vpdpp-vpep2gn/1.0 +#define VPCM_GAMCOR_RAMA_START_CNTL_R__VPCM_GAMCOR_RAMA_EXP_REGION_START_R__SHIFT 0x00000000 +#define VPCM_GAMCOR_RAMA_START_CNTL_R__VPCM_GAMCOR_RAMA_EXP_REGION_START_SEGMENT_R__SHIFT 0x00000014 + +// reg: VPCM_GAMCOR_RAMA_START_SLOPE_CNTL_B block: VPCM comp: amd.com/lib/vpdpp-vpep2gn/1.0 +#define VPCM_GAMCOR_RAMA_START_SLOPE_CNTL_B__VPCM_GAMCOR_RAMA_EXP_REGION_START_SLOPE_B__SHIFT 0x00000000 + +// reg: VPCM_GAMCOR_RAMA_START_SLOPE_CNTL_G block: VPCM comp: amd.com/lib/vpdpp-vpep2gn/1.0 +#define VPCM_GAMCOR_RAMA_START_SLOPE_CNTL_G__VPCM_GAMCOR_RAMA_EXP_REGION_START_SLOPE_G__SHIFT 0x00000000 + +// reg: VPCM_GAMCOR_RAMA_START_SLOPE_CNTL_R block: VPCM comp: amd.com/lib/vpdpp-vpep2gn/1.0 +#define VPCM_GAMCOR_RAMA_START_SLOPE_CNTL_R__VPCM_GAMCOR_RAMA_EXP_REGION_START_SLOPE_R__SHIFT 0x00000000 + +// reg: VPCM_GAMCOR_RAMA_START_BASE_CNTL_B block: VPCM comp: amd.com/lib/vpdpp-vpep2gn/1.0 +#define VPCM_GAMCOR_RAMA_START_BASE_CNTL_B__VPCM_GAMCOR_RAMA_EXP_REGION_START_BASE_B__SHIFT 0x00000000 + +// reg: VPCM_GAMCOR_RAMA_START_BASE_CNTL_G block: VPCM comp: amd.com/lib/vpdpp-vpep2gn/1.0 +#define VPCM_GAMCOR_RAMA_START_BASE_CNTL_G__VPCM_GAMCOR_RAMA_EXP_REGION_START_BASE_G__SHIFT 0x00000000 + +// reg: VPCM_GAMCOR_RAMA_START_BASE_CNTL_R block: VPCM comp: amd.com/lib/vpdpp-vpep2gn/1.0 +#define VPCM_GAMCOR_RAMA_START_BASE_CNTL_R__VPCM_GAMCOR_RAMA_EXP_REGION_START_BASE_R__SHIFT 0x00000000 + +// reg: VPCM_GAMCOR_RAMA_END_CNTL1_B block: VPCM comp: amd.com/lib/vpdpp-vpep2gn/1.0 +#define VPCM_GAMCOR_RAMA_END_CNTL1_B__VPCM_GAMCOR_RAMA_EXP_REGION_END_BASE_B__SHIFT 0x00000000 + +// reg: VPCM_GAMCOR_RAMA_END_CNTL2_B block: VPCM comp: amd.com/lib/vpdpp-vpep2gn/1.0 +#define VPCM_GAMCOR_RAMA_END_CNTL2_B__VPCM_GAMCOR_RAMA_EXP_REGION_END_B__SHIFT 0x00000000 +#define VPCM_GAMCOR_RAMA_END_CNTL2_B__VPCM_GAMCOR_RAMA_EXP_REGION_END_SLOPE_B__SHIFT 0x00000010 + +// reg: VPCM_GAMCOR_RAMA_END_CNTL1_G block: VPCM comp: amd.com/lib/vpdpp-vpep2gn/1.0 +#define VPCM_GAMCOR_RAMA_END_CNTL1_G__VPCM_GAMCOR_RAMA_EXP_REGION_END_BASE_G__SHIFT 0x00000000 + +// reg: VPCM_GAMCOR_RAMA_END_CNTL2_G block: VPCM comp: amd.com/lib/vpdpp-vpep2gn/1.0 +#define VPCM_GAMCOR_RAMA_END_CNTL2_G__VPCM_GAMCOR_RAMA_EXP_REGION_END_G__SHIFT 0x00000000 +#define VPCM_GAMCOR_RAMA_END_CNTL2_G__VPCM_GAMCOR_RAMA_EXP_REGION_END_SLOPE_G__SHIFT 0x00000010 + +// reg: VPCM_GAMCOR_RAMA_END_CNTL1_R block: VPCM comp: amd.com/lib/vpdpp-vpep2gn/1.0 +#define VPCM_GAMCOR_RAMA_END_CNTL1_R__VPCM_GAMCOR_RAMA_EXP_REGION_END_BASE_R__SHIFT 0x00000000 + +// reg: VPCM_GAMCOR_RAMA_END_CNTL2_R block: VPCM comp: amd.com/lib/vpdpp-vpep2gn/1.0 +#define VPCM_GAMCOR_RAMA_END_CNTL2_R__VPCM_GAMCOR_RAMA_EXP_REGION_END_R__SHIFT 0x00000000 +#define VPCM_GAMCOR_RAMA_END_CNTL2_R__VPCM_GAMCOR_RAMA_EXP_REGION_END_SLOPE_R__SHIFT 0x00000010 + +// reg: VPCM_GAMCOR_RAMA_OFFSET_B block: VPCM comp: amd.com/lib/vpdpp-vpep2gn/1.0 +#define VPCM_GAMCOR_RAMA_OFFSET_B__VPCM_GAMCOR_RAMA_OFFSET_B__SHIFT 0x00000000 + +// reg: VPCM_GAMCOR_RAMA_OFFSET_G block: VPCM comp: amd.com/lib/vpdpp-vpep2gn/1.0 +#define VPCM_GAMCOR_RAMA_OFFSET_G__VPCM_GAMCOR_RAMA_OFFSET_G__SHIFT 0x00000000 + +// reg: VPCM_GAMCOR_RAMA_OFFSET_R block: VPCM comp: amd.com/lib/vpdpp-vpep2gn/1.0 +#define VPCM_GAMCOR_RAMA_OFFSET_R__VPCM_GAMCOR_RAMA_OFFSET_R__SHIFT 0x00000000 + +// reg: VPCM_GAMCOR_RAMA_REGION_0_1 block: VPCM comp: amd.com/lib/vpdpp-vpep2gn/1.0 +#define VPCM_GAMCOR_RAMA_REGION_0_1__VPCM_GAMCOR_RAMA_EXP_REGION0_LUT_OFFSET__SHIFT 0x00000000 +#define VPCM_GAMCOR_RAMA_REGION_0_1__VPCM_GAMCOR_RAMA_EXP_REGION0_NUM_SEGMENTS__SHIFT 0x0000000c +#define VPCM_GAMCOR_RAMA_REGION_0_1__VPCM_GAMCOR_RAMA_EXP_REGION1_LUT_OFFSET__SHIFT 0x00000010 +#define VPCM_GAMCOR_RAMA_REGION_0_1__VPCM_GAMCOR_RAMA_EXP_REGION1_NUM_SEGMENTS__SHIFT 0x0000001c + +// reg: VPCM_GAMCOR_RAMA_REGION_2_3 block: VPCM comp: amd.com/lib/vpdpp-vpep2gn/1.0 +#define VPCM_GAMCOR_RAMA_REGION_2_3__VPCM_GAMCOR_RAMA_EXP_REGION2_LUT_OFFSET__SHIFT 0x00000000 +#define VPCM_GAMCOR_RAMA_REGION_2_3__VPCM_GAMCOR_RAMA_EXP_REGION2_NUM_SEGMENTS__SHIFT 0x0000000c +#define VPCM_GAMCOR_RAMA_REGION_2_3__VPCM_GAMCOR_RAMA_EXP_REGION3_LUT_OFFSET__SHIFT 0x00000010 +#define VPCM_GAMCOR_RAMA_REGION_2_3__VPCM_GAMCOR_RAMA_EXP_REGION3_NUM_SEGMENTS__SHIFT 0x0000001c + +// reg: VPCM_GAMCOR_RAMA_REGION_4_5 block: VPCM comp: amd.com/lib/vpdpp-vpep2gn/1.0 +#define VPCM_GAMCOR_RAMA_REGION_4_5__VPCM_GAMCOR_RAMA_EXP_REGION4_LUT_OFFSET__SHIFT 0x00000000 +#define VPCM_GAMCOR_RAMA_REGION_4_5__VPCM_GAMCOR_RAMA_EXP_REGION4_NUM_SEGMENTS__SHIFT 0x0000000c +#define VPCM_GAMCOR_RAMA_REGION_4_5__VPCM_GAMCOR_RAMA_EXP_REGION5_LUT_OFFSET__SHIFT 0x00000010 +#define VPCM_GAMCOR_RAMA_REGION_4_5__VPCM_GAMCOR_RAMA_EXP_REGION5_NUM_SEGMENTS__SHIFT 0x0000001c + +// reg: VPCM_GAMCOR_RAMA_REGION_6_7 block: VPCM comp: amd.com/lib/vpdpp-vpep2gn/1.0 +#define VPCM_GAMCOR_RAMA_REGION_6_7__VPCM_GAMCOR_RAMA_EXP_REGION6_LUT_OFFSET__SHIFT 0x00000000 +#define VPCM_GAMCOR_RAMA_REGION_6_7__VPCM_GAMCOR_RAMA_EXP_REGION6_NUM_SEGMENTS__SHIFT 0x0000000c +#define VPCM_GAMCOR_RAMA_REGION_6_7__VPCM_GAMCOR_RAMA_EXP_REGION7_LUT_OFFSET__SHIFT 0x00000010 +#define VPCM_GAMCOR_RAMA_REGION_6_7__VPCM_GAMCOR_RAMA_EXP_REGION7_NUM_SEGMENTS__SHIFT 0x0000001c + +// reg: VPCM_GAMCOR_RAMA_REGION_8_9 block: VPCM comp: amd.com/lib/vpdpp-vpep2gn/1.0 +#define VPCM_GAMCOR_RAMA_REGION_8_9__VPCM_GAMCOR_RAMA_EXP_REGION8_LUT_OFFSET__SHIFT 0x00000000 +#define VPCM_GAMCOR_RAMA_REGION_8_9__VPCM_GAMCOR_RAMA_EXP_REGION8_NUM_SEGMENTS__SHIFT 0x0000000c +#define VPCM_GAMCOR_RAMA_REGION_8_9__VPCM_GAMCOR_RAMA_EXP_REGION9_LUT_OFFSET__SHIFT 0x00000010 +#define VPCM_GAMCOR_RAMA_REGION_8_9__VPCM_GAMCOR_RAMA_EXP_REGION9_NUM_SEGMENTS__SHIFT 0x0000001c + +// reg: VPCM_GAMCOR_RAMA_REGION_10_11 block: VPCM comp: amd.com/lib/vpdpp-vpep2gn/1.0 +#define VPCM_GAMCOR_RAMA_REGION_10_11__VPCM_GAMCOR_RAMA_EXP_REGION10_LUT_OFFSET__SHIFT 0x00000000 +#define VPCM_GAMCOR_RAMA_REGION_10_11__VPCM_GAMCOR_RAMA_EXP_REGION10_NUM_SEGMENTS__SHIFT 0x0000000c +#define VPCM_GAMCOR_RAMA_REGION_10_11__VPCM_GAMCOR_RAMA_EXP_REGION11_LUT_OFFSET__SHIFT 0x00000010 +#define VPCM_GAMCOR_RAMA_REGION_10_11__VPCM_GAMCOR_RAMA_EXP_REGION11_NUM_SEGMENTS__SHIFT 0x0000001c + +// reg: VPCM_GAMCOR_RAMA_REGION_12_13 block: VPCM comp: amd.com/lib/vpdpp-vpep2gn/1.0 +#define VPCM_GAMCOR_RAMA_REGION_12_13__VPCM_GAMCOR_RAMA_EXP_REGION12_LUT_OFFSET__SHIFT 0x00000000 +#define VPCM_GAMCOR_RAMA_REGION_12_13__VPCM_GAMCOR_RAMA_EXP_REGION12_NUM_SEGMENTS__SHIFT 0x0000000c +#define VPCM_GAMCOR_RAMA_REGION_12_13__VPCM_GAMCOR_RAMA_EXP_REGION13_LUT_OFFSET__SHIFT 0x00000010 +#define VPCM_GAMCOR_RAMA_REGION_12_13__VPCM_GAMCOR_RAMA_EXP_REGION13_NUM_SEGMENTS__SHIFT 0x0000001c + +// reg: VPCM_GAMCOR_RAMA_REGION_14_15 block: VPCM comp: amd.com/lib/vpdpp-vpep2gn/1.0 +#define VPCM_GAMCOR_RAMA_REGION_14_15__VPCM_GAMCOR_RAMA_EXP_REGION14_LUT_OFFSET__SHIFT 0x00000000 +#define VPCM_GAMCOR_RAMA_REGION_14_15__VPCM_GAMCOR_RAMA_EXP_REGION14_NUM_SEGMENTS__SHIFT 0x0000000c +#define VPCM_GAMCOR_RAMA_REGION_14_15__VPCM_GAMCOR_RAMA_EXP_REGION15_LUT_OFFSET__SHIFT 0x00000010 +#define VPCM_GAMCOR_RAMA_REGION_14_15__VPCM_GAMCOR_RAMA_EXP_REGION15_NUM_SEGMENTS__SHIFT 0x0000001c + +// reg: VPCM_GAMCOR_RAMA_REGION_16_17 block: VPCM comp: amd.com/lib/vpdpp-vpep2gn/1.0 +#define VPCM_GAMCOR_RAMA_REGION_16_17__VPCM_GAMCOR_RAMA_EXP_REGION16_LUT_OFFSET__SHIFT 0x00000000 +#define VPCM_GAMCOR_RAMA_REGION_16_17__VPCM_GAMCOR_RAMA_EXP_REGION16_NUM_SEGMENTS__SHIFT 0x0000000c +#define VPCM_GAMCOR_RAMA_REGION_16_17__VPCM_GAMCOR_RAMA_EXP_REGION17_LUT_OFFSET__SHIFT 0x00000010 +#define VPCM_GAMCOR_RAMA_REGION_16_17__VPCM_GAMCOR_RAMA_EXP_REGION17_NUM_SEGMENTS__SHIFT 0x0000001c + +// reg: VPCM_GAMCOR_RAMA_REGION_18_19 block: VPCM comp: amd.com/lib/vpdpp-vpep2gn/1.0 +#define VPCM_GAMCOR_RAMA_REGION_18_19__VPCM_GAMCOR_RAMA_EXP_REGION18_LUT_OFFSET__SHIFT 0x00000000 +#define VPCM_GAMCOR_RAMA_REGION_18_19__VPCM_GAMCOR_RAMA_EXP_REGION18_NUM_SEGMENTS__SHIFT 0x0000000c +#define VPCM_GAMCOR_RAMA_REGION_18_19__VPCM_GAMCOR_RAMA_EXP_REGION19_LUT_OFFSET__SHIFT 0x00000010 +#define VPCM_GAMCOR_RAMA_REGION_18_19__VPCM_GAMCOR_RAMA_EXP_REGION19_NUM_SEGMENTS__SHIFT 0x0000001c + +// reg: VPCM_GAMCOR_RAMA_REGION_20_21 block: VPCM comp: amd.com/lib/vpdpp-vpep2gn/1.0 +#define VPCM_GAMCOR_RAMA_REGION_20_21__VPCM_GAMCOR_RAMA_EXP_REGION20_LUT_OFFSET__SHIFT 0x00000000 +#define VPCM_GAMCOR_RAMA_REGION_20_21__VPCM_GAMCOR_RAMA_EXP_REGION20_NUM_SEGMENTS__SHIFT 0x0000000c +#define VPCM_GAMCOR_RAMA_REGION_20_21__VPCM_GAMCOR_RAMA_EXP_REGION21_LUT_OFFSET__SHIFT 0x00000010 +#define VPCM_GAMCOR_RAMA_REGION_20_21__VPCM_GAMCOR_RAMA_EXP_REGION21_NUM_SEGMENTS__SHIFT 0x0000001c + +// reg: VPCM_GAMCOR_RAMA_REGION_22_23 block: VPCM comp: amd.com/lib/vpdpp-vpep2gn/1.0 +#define VPCM_GAMCOR_RAMA_REGION_22_23__VPCM_GAMCOR_RAMA_EXP_REGION22_LUT_OFFSET__SHIFT 0x00000000 +#define VPCM_GAMCOR_RAMA_REGION_22_23__VPCM_GAMCOR_RAMA_EXP_REGION22_NUM_SEGMENTS__SHIFT 0x0000000c +#define VPCM_GAMCOR_RAMA_REGION_22_23__VPCM_GAMCOR_RAMA_EXP_REGION23_LUT_OFFSET__SHIFT 0x00000010 +#define VPCM_GAMCOR_RAMA_REGION_22_23__VPCM_GAMCOR_RAMA_EXP_REGION23_NUM_SEGMENTS__SHIFT 0x0000001c + +// reg: VPCM_GAMCOR_RAMA_REGION_24_25 block: VPCM comp: amd.com/lib/vpdpp-vpep2gn/1.0 +#define VPCM_GAMCOR_RAMA_REGION_24_25__VPCM_GAMCOR_RAMA_EXP_REGION24_LUT_OFFSET__SHIFT 0x00000000 +#define VPCM_GAMCOR_RAMA_REGION_24_25__VPCM_GAMCOR_RAMA_EXP_REGION24_NUM_SEGMENTS__SHIFT 0x0000000c +#define VPCM_GAMCOR_RAMA_REGION_24_25__VPCM_GAMCOR_RAMA_EXP_REGION25_LUT_OFFSET__SHIFT 0x00000010 +#define VPCM_GAMCOR_RAMA_REGION_24_25__VPCM_GAMCOR_RAMA_EXP_REGION25_NUM_SEGMENTS__SHIFT 0x0000001c + +// reg: VPCM_GAMCOR_RAMA_REGION_26_27 block: VPCM comp: amd.com/lib/vpdpp-vpep2gn/1.0 +#define VPCM_GAMCOR_RAMA_REGION_26_27__VPCM_GAMCOR_RAMA_EXP_REGION26_LUT_OFFSET__SHIFT 0x00000000 +#define VPCM_GAMCOR_RAMA_REGION_26_27__VPCM_GAMCOR_RAMA_EXP_REGION26_NUM_SEGMENTS__SHIFT 0x0000000c +#define VPCM_GAMCOR_RAMA_REGION_26_27__VPCM_GAMCOR_RAMA_EXP_REGION27_LUT_OFFSET__SHIFT 0x00000010 +#define VPCM_GAMCOR_RAMA_REGION_26_27__VPCM_GAMCOR_RAMA_EXP_REGION27_NUM_SEGMENTS__SHIFT 0x0000001c + +// reg: VPCM_GAMCOR_RAMA_REGION_28_29 block: VPCM comp: amd.com/lib/vpdpp-vpep2gn/1.0 +#define VPCM_GAMCOR_RAMA_REGION_28_29__VPCM_GAMCOR_RAMA_EXP_REGION28_LUT_OFFSET__SHIFT 0x00000000 +#define VPCM_GAMCOR_RAMA_REGION_28_29__VPCM_GAMCOR_RAMA_EXP_REGION28_NUM_SEGMENTS__SHIFT 0x0000000c +#define VPCM_GAMCOR_RAMA_REGION_28_29__VPCM_GAMCOR_RAMA_EXP_REGION29_LUT_OFFSET__SHIFT 0x00000010 +#define VPCM_GAMCOR_RAMA_REGION_28_29__VPCM_GAMCOR_RAMA_EXP_REGION29_NUM_SEGMENTS__SHIFT 0x0000001c + +// reg: VPCM_GAMCOR_RAMA_REGION_30_31 block: VPCM comp: amd.com/lib/vpdpp-vpep2gn/1.0 +#define VPCM_GAMCOR_RAMA_REGION_30_31__VPCM_GAMCOR_RAMA_EXP_REGION30_LUT_OFFSET__SHIFT 0x00000000 +#define VPCM_GAMCOR_RAMA_REGION_30_31__VPCM_GAMCOR_RAMA_EXP_REGION30_NUM_SEGMENTS__SHIFT 0x0000000c +#define VPCM_GAMCOR_RAMA_REGION_30_31__VPCM_GAMCOR_RAMA_EXP_REGION31_LUT_OFFSET__SHIFT 0x00000010 +#define VPCM_GAMCOR_RAMA_REGION_30_31__VPCM_GAMCOR_RAMA_EXP_REGION31_NUM_SEGMENTS__SHIFT 0x0000001c + +// reg: VPCM_GAMCOR_RAMA_REGION_32_33 block: VPCM comp: amd.com/lib/vpdpp-vpep2gn/1.0 +#define VPCM_GAMCOR_RAMA_REGION_32_33__VPCM_GAMCOR_RAMA_EXP_REGION32_LUT_OFFSET__SHIFT 0x00000000 +#define VPCM_GAMCOR_RAMA_REGION_32_33__VPCM_GAMCOR_RAMA_EXP_REGION32_NUM_SEGMENTS__SHIFT 0x0000000c +#define VPCM_GAMCOR_RAMA_REGION_32_33__VPCM_GAMCOR_RAMA_EXP_REGION33_LUT_OFFSET__SHIFT 0x00000010 +#define VPCM_GAMCOR_RAMA_REGION_32_33__VPCM_GAMCOR_RAMA_EXP_REGION33_NUM_SEGMENTS__SHIFT 0x0000001c + +// reg: VPCM_HDR_MULT_COEF block: VPCM comp: amd.com/lib/vpdpp-vpep2gn/1.0 +#define VPCM_HDR_MULT_COEF__VPCM_HDR_MULT_COEF__SHIFT 0x00000000 + +// reg: VPCM_MEM_PWR_CTRL block: VPCM comp: amd.com/lib/vpdpp-vpep2gn/1.0 +#define VPCM_MEM_PWR_CTRL__GAMCOR_MEM_PWR_FORCE__SHIFT 0x00000000 +#define VPCM_MEM_PWR_CTRL__GAMCOR_MEM_PWR_DIS__SHIFT 0x00000002 + +// reg: VPCM_MEM_PWR_STATUS block: VPCM comp: amd.com/lib/vpdpp-vpep2gn/1.0 +#define VPCM_MEM_PWR_STATUS__GAMCOR_MEM_PWR_STATE__SHIFT 0x00000000 + +// reg: VPCM_DEALPHA block: VPCM comp: amd.com/lib/vpdpp-vpep2gn/1.0 +#define VPCM_DEALPHA__VPCM_DEALPHA_EN__SHIFT 0x00000000 +#define VPCM_DEALPHA__VPCM_DEALPHA_ABLND__SHIFT 0x00000001 + +// reg: VPCM_COEF_FORMAT block: VPCM comp: amd.com/lib/vpdpp-vpep2gn/1.0 +#define VPCM_COEF_FORMAT__VPCM_BIAS_FORMAT__SHIFT 0x00000000 +#define VPCM_COEF_FORMAT__VPCM_POST_CSC_COEF_FORMAT__SHIFT 0x00000004 + +// reg: VPCM_HIST_CNTL block: VPCM comp: amd.com/lib/vpdpp-vpep2gn/1.0 +#define VPCM_HIST_CNTL__VPCM_HIST_SEL__SHIFT 0x00000000 +#define VPCM_HIST_CNTL__VPCM_HIST_CH_EN__SHIFT 0x00000002 +#define VPCM_HIST_CNTL__VPCM_HIST_SRC1_SEL__SHIFT 0x00000004 +#define VPCM_HIST_CNTL__VPCM_HIST_SRC2_SEL__SHIFT 0x00000005 +#define VPCM_HIST_CNTL__VPCM_HIST_SRC3_SEL__SHIFT 0x00000006 +#define VPCM_HIST_CNTL__VPCM_HIST_CH1_XBAR__SHIFT 0x00000007 +#define VPCM_HIST_CNTL__VPCM_HIST_CH2_XBAR__SHIFT 0x00000009 +#define VPCM_HIST_CNTL__VPCM_HIST_CH3_XBAR__SHIFT 0x0000000b +#define VPCM_HIST_CNTL__VPCM_HIST_FORMAT__SHIFT 0x0000000d +#define VPCM_HIST_CNTL__VPCM_HIST_READ_CHANNEL_MASK__SHIFT 0x0000000f + +// reg: VPCM_HIST_SCALE_SRC1 block: VPCM comp: amd.com/lib/vpdpp-vpep2gn/1.0 +#define VPCM_HIST_SCALE_SRC1__VPCM_HIST_SCALE_SRC1__SHIFT 0x00000000 + +// reg: VPCM_HIST_COEFA_SRC2 block: VPCM comp: amd.com/lib/vpdpp-vpep2gn/1.0 +#define VPCM_HIST_COEFA_SRC2__VPCM_HIST_COEFA_SRC2__SHIFT 0x00000000 + +// reg: VPCM_HIST_COEFB_SRC2 block: VPCM comp: amd.com/lib/vpdpp-vpep2gn/1.0 +#define VPCM_HIST_COEFB_SRC2__VPCM_HIST_COEFB_SRC2__SHIFT 0x00000000 + +// reg: VPCM_HIST_COEFC_SRC2 block: VPCM comp: amd.com/lib/vpdpp-vpep2gn/1.0 +#define VPCM_HIST_COEFC_SRC2__VPCM_HIST_COEFC_SRC2__SHIFT 0x00000000 + +// reg: VPCM_HIST_SCALE_SRC3 block: VPCM comp: amd.com/lib/vpdpp-vpep2gn/1.0 +#define VPCM_HIST_SCALE_SRC3__VPCM_HIST_SCALE_SRC3__SHIFT 0x00000000 + +// reg: VPCM_HIST_BIAS_SRC1 block: VPCM comp: amd.com/lib/vpdpp-vpep2gn/1.0 +#define VPCM_HIST_BIAS_SRC1__VPCM_HIST_BIAS_SRC1__SHIFT 0x00000000 + +// reg: VPCM_HIST_BIAS_SRC2 block: VPCM comp: amd.com/lib/vpdpp-vpep2gn/1.0 +#define VPCM_HIST_BIAS_SRC2__VPCM_HIST_BIAS_SRC2__SHIFT 0x00000000 + +// reg: VPCM_HIST_BIAS_SRC3 block: VPCM comp: amd.com/lib/vpdpp-vpep2gn/1.0 +#define VPCM_HIST_BIAS_SRC3__VPCM_HIST_BIAS_SRC3__SHIFT 0x00000000 + +// reg: VPDPP_CONTROL block: VPDPP_TOP comp: amd.com/lib/vpdpp-vpep2gn/1.0 +#define VPDPP_CONTROL__VPECLK_G_GATE_DISABLE__SHIFT 0x00000008 +#define VPDPP_CONTROL__VPECLK_G_VPDSCL_GATE_DISABLE__SHIFT 0x0000000c +#define VPDPP_CONTROL__VPDPP_FGCG_REP_DIS__SHIFT 0x00000018 + +// reg: VPDPP_CRC_CTRL block: VPDPP_TOP comp: amd.com/lib/vpdpp-vpep2gn/1.0 +#define VPDPP_CRC_CTRL__VPDPP_CRC_EN__SHIFT 0x00000000 +#define VPDPP_CRC_CTRL__VPDPP_CRC_CONT_EN__SHIFT 0x00000001 +#define VPDPP_CRC_CTRL__VPDPP_CRC_420_COMP_SEL__SHIFT 0x00000003 +#define VPDPP_CRC_CTRL__VPDPP_CRC_SRC_SEL__SHIFT 0x00000004 +#define VPDPP_CRC_CTRL__VPDPP_CRC_PIX_FORMAT_SEL__SHIFT 0x0000000b +#define VPDPP_CRC_CTRL__VPDPP_CRC_MASK__SHIFT 0x00000010 + +// reg: VPMPC_CLOCK_CONTROL block: VPMPC_CFG comp: amd.com/lib/vpmpc-vpep2gn/1.0 +#define VPMPC_CLOCK_CONTROL__VPECLK_R_GATE_DISABLE__SHIFT 0x00000001 + +// reg: VPMPC_SOFT_RESET block: VPMPC_CFG comp: amd.com/lib/vpmpc-vpep2gn/1.0 +#define VPMPC_SOFT_RESET__VPMPCC0_SOFT_RESET__SHIFT 0x00000000 +#define VPMPC_SOFT_RESET__VPMPC_SFR0_SOFT_RESET__SHIFT 0x0000000a +#define VPMPC_SOFT_RESET__VPMPC_SFT0_SOFT_RESET__SHIFT 0x00000014 +#define VPMPC_SOFT_RESET__VPMPC_SOFT_RESET__SHIFT 0x0000001f + +// reg: VPMPC_CRC_CTRL block: VPMPC_CFG comp: amd.com/lib/vpmpc-vpep2gn/1.0 +#define VPMPC_CRC_CTRL__VPMPC_CRC_EN__SHIFT 0x00000000 +#define VPMPC_CRC_CTRL__VPMPC_CRC_CONT_EN__SHIFT 0x00000004 +#define VPMPC_CRC_CTRL__VPMPC_CRC_SRC_SEL__SHIFT 0x00000018 +#define VPMPC_CRC_CTRL__VPMPC_CRC_ONE_SHOT_PENDING__SHIFT 0x0000001c +#define VPMPC_CRC_CTRL__VPMPC_CRC_UPDATE_ENABLED__SHIFT 0x0000001e +#define VPMPC_CRC_CTRL__VPMPC_CRC_UPDATE_LOCK__SHIFT 0x0000001f + +// reg: VPMPC_CRC_SEL_CONTROL block: VPMPC_CFG comp: amd.com/lib/vpmpc-vpep2gn/1.0 +#define VPMPC_CRC_SEL_CONTROL__VPMPC_CRC_VPDPP_SEL__SHIFT 0x00000000 +#define VPMPC_CRC_SEL_CONTROL__VPMPC_CRC_VPOPP_SEL__SHIFT 0x00000004 +#define VPMPC_CRC_SEL_CONTROL__VPMPC_CRC_MASK__SHIFT 0x00000010 + +// reg: VPMPC_CRC_RESULT_AR block: VPMPC_CFG comp: amd.com/lib/vpmpc-vpep2gn/1.0 +#define VPMPC_CRC_RESULT_AR__VPMPC_CRC_RESULT_A__SHIFT 0x00000000 +#define VPMPC_CRC_RESULT_AR__VPMPC_CRC_RESULT_R__SHIFT 0x00000010 + +// reg: VPMPC_CRC_RESULT_GB block: VPMPC_CFG comp: amd.com/lib/vpmpc-vpep2gn/1.0 +#define VPMPC_CRC_RESULT_GB__VPMPC_CRC_RESULT_G__SHIFT 0x00000000 +#define VPMPC_CRC_RESULT_GB__VPMPC_CRC_RESULT_B__SHIFT 0x00000010 + +// reg: VPMPC_CRC_RESULT_C block: VPMPC_CFG comp: amd.com/lib/vpmpc-vpep2gn/1.0 +#define VPMPC_CRC_RESULT_C__VPMPC_CRC_RESULT_C__SHIFT 0x00000000 + +// reg: VPMPC_BYPASS_BG_AR block: VPMPC_CFG comp: amd.com/lib/vpmpc-vpep2gn/1.0 +#define VPMPC_BYPASS_BG_AR__VPMPC_BYPASS_BG_ALPHA__SHIFT 0x00000000 +#define VPMPC_BYPASS_BG_AR__VPMPC_BYPASS_BG_R_CR__SHIFT 0x00000010 + +// reg: VPMPC_BYPASS_BG_GB block: VPMPC_CFG comp: amd.com/lib/vpmpc-vpep2gn/1.0 +#define VPMPC_BYPASS_BG_GB__VPMPC_BYPASS_BG_G_Y__SHIFT 0x00000000 +#define VPMPC_BYPASS_BG_GB__VPMPC_BYPASS_BG_B_CB__SHIFT 0x00000010 + +// reg: VPMPC_HOST_READ_CONTROL block: VPMPC_CFG comp: amd.com/lib/vpmpc-vpep2gn/1.0 +#define VPMPC_HOST_READ_CONTROL__HOST_READ_RATE_CONTROL__SHIFT 0x00000000 + +// reg: VPMPC_PENDING_STATUS_MISC block: VPMPC_CFG comp: amd.com/lib/vpmpc-vpep2gn/1.0 +#define VPMPC_PENDING_STATUS_MISC__VPMPCC0_CONFIG_UPDATE_PENDING__SHIFT 0x00000008 + +// reg: VPMPC_VPCDC0_3DLUT_FL_CONFIG block: VPMPC_CFG comp: amd.com/lib/vpmpc-vpep2gn/1.0 +#define VPMPC_VPCDC0_3DLUT_FL_CONFIG__VPCDC0_3DLUT_FL_MODE__SHIFT 0x00000000 +#define VPMPC_VPCDC0_3DLUT_FL_CONFIG__VPCDC0_3DLUT_FL_FORMAT__SHIFT 0x00000004 + +// reg: VPMPC_VPCDC0_3DLUT_FL_BIAS_SCALE block: VPMPC_CFG comp: amd.com/lib/vpmpc-vpep2gn/1.0 +#define VPMPC_VPCDC0_3DLUT_FL_BIAS_SCALE__VPCDC0_3DLUT_FL_BIAS__SHIFT 0x00000000 +#define VPMPC_VPCDC0_3DLUT_FL_BIAS_SCALE__VPCDC0_3DLUT_FL_SCALE__SHIFT 0x00000010 + +// reg: VPMPC_OUT0_MUX block: VPMPC_OCSC comp: amd.com/lib/vpmpc-vpep2gn/1.0 +#define VPMPC_OUT0_MUX__VPMPC_OUT_MUX__SHIFT 0x00000000 + +// reg: VPMPC_OUT0_FLOAT_CONTROL block: VPMPC_OCSC comp: amd.com/lib/vpmpc-vpep2gn/1.0 +#define VPMPC_OUT0_FLOAT_CONTROL__VPMPC_OUT_FLOAT_EN__SHIFT 0x00000000 + +// reg: VPMPC_OUT0_DENORM_CONTROL block: VPMPC_OCSC comp: amd.com/lib/vpmpc-vpep2gn/1.0 +#define VPMPC_OUT0_DENORM_CONTROL__VPMPC_OUT_DENORM_CLAMP_MIN_R_CR__SHIFT 0x00000000 +#define VPMPC_OUT0_DENORM_CONTROL__VPMPC_OUT_DENORM_CLAMP_MAX_R_CR__SHIFT 0x0000000c +#define VPMPC_OUT0_DENORM_CONTROL__VPMPC_OUT_DENORM_MODE__SHIFT 0x00000018 + +// reg: VPMPC_OUT0_DENORM_CLAMP_G_Y block: VPMPC_OCSC comp: amd.com/lib/vpmpc-vpep2gn/1.0 +#define VPMPC_OUT0_DENORM_CLAMP_G_Y__VPMPC_OUT_DENORM_CLAMP_MIN_G_Y__SHIFT 0x00000000 +#define VPMPC_OUT0_DENORM_CLAMP_G_Y__VPMPC_OUT_DENORM_CLAMP_MAX_G_Y__SHIFT 0x0000000c + +// reg: VPMPC_OUT0_DENORM_CLAMP_B_CB block: VPMPC_OCSC comp: amd.com/lib/vpmpc-vpep2gn/1.0 +#define VPMPC_OUT0_DENORM_CLAMP_B_CB__VPMPC_OUT_DENORM_CLAMP_MIN_B_CB__SHIFT 0x00000000 +#define VPMPC_OUT0_DENORM_CLAMP_B_CB__VPMPC_OUT_DENORM_CLAMP_MAX_B_CB__SHIFT 0x0000000c + +// reg: VPMPC_OUT_CSC_COEF_FORMAT block: VPMPC_OCSC comp: amd.com/lib/vpmpc-vpep2gn/1.0 +#define VPMPC_OUT_CSC_COEF_FORMAT__VPMPC_OCSC0_COEF_FORMAT__SHIFT 0x00000000 + +// reg: VPMPC_OUT0_CSC_MODE block: VPMPC_OCSC comp: amd.com/lib/vpmpc-vpep2gn/1.0 +#define VPMPC_OUT0_CSC_MODE__VPMPC_OCSC_MODE__SHIFT 0x00000000 +#define VPMPC_OUT0_CSC_MODE__VPMPC_OCSC_MODE_CURRENT__SHIFT 0x00000007 + +// reg: VPMPC_OUT0_CSC_C11_C12_A block: VPMPC_OCSC comp: amd.com/lib/vpmpc-vpep2gn/1.0 +#define VPMPC_OUT0_CSC_C11_C12_A__VPMPC_OCSC_C11_A__SHIFT 0x00000000 +#define VPMPC_OUT0_CSC_C11_C12_A__VPMPC_OCSC_C12_A__SHIFT 0x00000010 + +// reg: VPMPC_OUT0_CSC_C13_C14_A block: VPMPC_OCSC comp: amd.com/lib/vpmpc-vpep2gn/1.0 +#define VPMPC_OUT0_CSC_C13_C14_A__VPMPC_OCSC_C13_A__SHIFT 0x00000000 +#define VPMPC_OUT0_CSC_C13_C14_A__VPMPC_OCSC_C14_A__SHIFT 0x00000010 + +// reg: VPMPC_OUT0_CSC_C21_C22_A block: VPMPC_OCSC comp: amd.com/lib/vpmpc-vpep2gn/1.0 +#define VPMPC_OUT0_CSC_C21_C22_A__VPMPC_OCSC_C21_A__SHIFT 0x00000000 +#define VPMPC_OUT0_CSC_C21_C22_A__VPMPC_OCSC_C22_A__SHIFT 0x00000010 + +// reg: VPMPC_OUT0_CSC_C23_C24_A block: VPMPC_OCSC comp: amd.com/lib/vpmpc-vpep2gn/1.0 +#define VPMPC_OUT0_CSC_C23_C24_A__VPMPC_OCSC_C23_A__SHIFT 0x00000000 +#define VPMPC_OUT0_CSC_C23_C24_A__VPMPC_OCSC_C24_A__SHIFT 0x00000010 + +// reg: VPMPC_OUT0_CSC_C31_C32_A block: VPMPC_OCSC comp: amd.com/lib/vpmpc-vpep2gn/1.0 +#define VPMPC_OUT0_CSC_C31_C32_A__VPMPC_OCSC_C31_A__SHIFT 0x00000000 +#define VPMPC_OUT0_CSC_C31_C32_A__VPMPC_OCSC_C32_A__SHIFT 0x00000010 + +// reg: VPMPC_OUT0_CSC_C33_C34_A block: VPMPC_OCSC comp: amd.com/lib/vpmpc-vpep2gn/1.0 +#define VPMPC_OUT0_CSC_C33_C34_A__VPMPC_OCSC_C33_A__SHIFT 0x00000000 +#define VPMPC_OUT0_CSC_C33_C34_A__VPMPC_OCSC_C34_A__SHIFT 0x00000010 + +// reg: VPMPCC_TOP_SEL block: VPMPCC comp: amd.com/lib/vpmpc-vpep2gn/1.0 +#define VPMPCC_TOP_SEL__VPMPCC_TOP_SEL__SHIFT 0x00000000 + +// reg: VPMPCC_BOT_SEL block: VPMPCC comp: amd.com/lib/vpmpc-vpep2gn/1.0 +#define VPMPCC_BOT_SEL__VPMPCC_BOT_SEL__SHIFT 0x00000000 + +// reg: VPMPCC_VPOPP_ID block: VPMPCC comp: amd.com/lib/vpmpc-vpep2gn/1.0 +#define VPMPCC_VPOPP_ID__VPMPCC_VPOPP_ID__SHIFT 0x00000000 + +// reg: VPMPCC_CONTROL block: VPMPCC comp: amd.com/lib/vpmpc-vpep2gn/1.0 +#define VPMPCC_CONTROL__VPMPCC_MODE__SHIFT 0x00000000 +#define VPMPCC_CONTROL__VPMPCC_ALPHA_BLND_MODE__SHIFT 0x00000004 +#define VPMPCC_CONTROL__VPMPCC_ALPHA_MULTIPLIED_MODE__SHIFT 0x00000006 +#define VPMPCC_CONTROL__VPMPCC_BLND_ACTIVE_OVERLAP_ONLY__SHIFT 0x00000007 +#define VPMPCC_CONTROL__VPMPCC_BOT_GAIN_MODE__SHIFT 0x0000000b + +// reg: VPMPCC_CONTROL2 block: VPMPCC comp: amd.com/lib/vpmpc-vpep2gn/1.0 +#define VPMPCC_CONTROL2__VPMPCC_GLOBAL_ALPHA__SHIFT 0x00000000 +#define VPMPCC_CONTROL2__VPMPCC_GLOBAL_GAIN__SHIFT 0x00000010 + +// reg: VPMPCC_TOP_GAIN block: VPMPCC comp: amd.com/lib/vpmpc-vpep2gn/1.0 +#define VPMPCC_TOP_GAIN__VPMPCC_TOP_GAIN__SHIFT 0x00000000 + +// reg: VPMPCC_BOT_GAIN_INSIDE block: VPMPCC comp: amd.com/lib/vpmpc-vpep2gn/1.0 +#define VPMPCC_BOT_GAIN_INSIDE__VPMPCC_BOT_GAIN_INSIDE__SHIFT 0x00000000 + +// reg: VPMPCC_BOT_GAIN_OUTSIDE block: VPMPCC comp: amd.com/lib/vpmpc-vpep2gn/1.0 +#define VPMPCC_BOT_GAIN_OUTSIDE__VPMPCC_BOT_GAIN_OUTSIDE__SHIFT 0x00000000 + +// reg: VPMPCC_MOVABLE_CM_LOCATION_CONTROL block: VPMPCC comp: amd.com/lib/vpmpc-vpep2gn/1.0 +#define VPMPCC_MOVABLE_CM_LOCATION_CONTROL__VPMPCC_MOVABLE_CM_LOCATION_CNTL__SHIFT 0x00000000 +#define VPMPCC_MOVABLE_CM_LOCATION_CONTROL__VPMPCC_MOVABLE_CM_LOCATION_CNTL_CURRENT__SHIFT 0x00000004 + +// reg: VPMPCC_BG_R_CR block: VPMPCC comp: amd.com/lib/vpmpc-vpep2gn/1.0 +#define VPMPCC_BG_R_CR__VPMPCC_BG_R_CR__SHIFT 0x00000000 + +// reg: VPMPCC_BG_G_Y block: VPMPCC comp: amd.com/lib/vpmpc-vpep2gn/1.0 +#define VPMPCC_BG_G_Y__VPMPCC_BG_G_Y__SHIFT 0x00000000 + +// reg: VPMPCC_BG_B_CB block: VPMPCC comp: amd.com/lib/vpmpc-vpep2gn/1.0 +#define VPMPCC_BG_B_CB__VPMPCC_BG_B_CB__SHIFT 0x00000000 + +// reg: VPMPCC_MEM_PWR_CTRL block: VPMPCC comp: amd.com/lib/vpmpc-vpep2gn/1.0 +#define VPMPCC_MEM_PWR_CTRL__VPMPCC_OGAM_MEM_PWR_FORCE__SHIFT 0x00000000 +#define VPMPCC_MEM_PWR_CTRL__VPMPCC_OGAM_MEM_PWR_DIS__SHIFT 0x00000002 +#define VPMPCC_MEM_PWR_CTRL__VPMPCC_OGAM_MEM_LOW_PWR_MODE__SHIFT 0x00000004 +#define VPMPCC_MEM_PWR_CTRL__VPMPCC_OGAM_MEM_PWR_STATE__SHIFT 0x00000008 + +// reg: VPMPCC_STATUS block: VPMPCC comp: amd.com/lib/vpmpc-vpep2gn/1.0 +#define VPMPCC_STATUS__VPMPCC_IDLE__SHIFT 0x00000000 +#define VPMPCC_STATUS__VPMPCC_BUSY__SHIFT 0x00000001 +#define VPMPCC_STATUS__VPMPCC_DISABLED__SHIFT 0x00000002 + +// reg: VPMPCC_OGAM_CONTROL block: VPMPCC_OGAM comp: amd.com/lib/vpmpc-vpep2gn/1.0 +#define VPMPCC_OGAM_CONTROL__VPMPCC_OGAM_MODE__SHIFT 0x00000000 +#define VPMPCC_OGAM_CONTROL__VPMPCC_OGAM_PWL_DISABLE__SHIFT 0x00000003 +#define VPMPCC_OGAM_CONTROL__VPMPCC_OGAM_MODE_CURRENT__SHIFT 0x00000007 +#define VPMPCC_OGAM_CONTROL__VPMPCC_OGAM_SELECT_CURRENT__SHIFT 0x00000009 + +// reg: VPMPCC_OGAM_LUT_INDEX block: VPMPCC_OGAM comp: amd.com/lib/vpmpc-vpep2gn/1.0 +#define VPMPCC_OGAM_LUT_INDEX__VPMPCC_OGAM_LUT_INDEX__SHIFT 0x00000000 + +// reg: VPMPCC_OGAM_LUT_DATA block: VPMPCC_OGAM comp: amd.com/lib/vpmpc-vpep2gn/1.0 +#define VPMPCC_OGAM_LUT_DATA__VPMPCC_OGAM_LUT_DATA__SHIFT 0x00000000 + +// reg: VPMPCC_OGAM_LUT_CONTROL block: VPMPCC_OGAM comp: amd.com/lib/vpmpc-vpep2gn/1.0 +#define VPMPCC_OGAM_LUT_CONTROL__VPMPCC_OGAM_LUT_WRITE_COLOR_MASK__SHIFT 0x00000000 +#define VPMPCC_OGAM_LUT_CONTROL__VPMPCC_OGAM_LUT_READ_COLOR_SEL__SHIFT 0x00000003 +#define VPMPCC_OGAM_LUT_CONTROL__VPMPCC_OGAM_LUT_READ_DBG__SHIFT 0x00000005 +#define VPMPCC_OGAM_LUT_CONTROL__VPMPCC_OGAM_LUT_HOST_SEL__SHIFT 0x00000006 +#define VPMPCC_OGAM_LUT_CONTROL__VPMPCC_OGAM_LUT_CONFIG_MODE__SHIFT 0x00000007 + +// reg: VPMPCC_OGAM_RAMA_START_CNTL_B block: VPMPCC_OGAM comp: amd.com/lib/vpmpc-vpep2gn/1.0 +#define VPMPCC_OGAM_RAMA_START_CNTL_B__VPMPCC_OGAM_RAMA_EXP_REGION_START_B__SHIFT 0x00000000 +#define VPMPCC_OGAM_RAMA_START_CNTL_B__VPMPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_B__SHIFT 0x00000014 + +// reg: VPMPCC_OGAM_RAMA_START_CNTL_G block: VPMPCC_OGAM comp: amd.com/lib/vpmpc-vpep2gn/1.0 +#define VPMPCC_OGAM_RAMA_START_CNTL_G__VPMPCC_OGAM_RAMA_EXP_REGION_START_G__SHIFT 0x00000000 +#define VPMPCC_OGAM_RAMA_START_CNTL_G__VPMPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_G__SHIFT 0x00000014 + +// reg: VPMPCC_OGAM_RAMA_START_CNTL_R block: VPMPCC_OGAM comp: amd.com/lib/vpmpc-vpep2gn/1.0 +#define VPMPCC_OGAM_RAMA_START_CNTL_R__VPMPCC_OGAM_RAMA_EXP_REGION_START_R__SHIFT 0x00000000 +#define VPMPCC_OGAM_RAMA_START_CNTL_R__VPMPCC_OGAM_RAMA_EXP_REGION_START_SEGMENT_R__SHIFT 0x00000014 + +// reg: VPMPCC_OGAM_RAMA_START_SLOPE_CNTL_B block: VPMPCC_OGAM comp: amd.com/lib/vpmpc-vpep2gn/1.0 +#define VPMPCC_OGAM_RAMA_START_SLOPE_CNTL_B__VPMPCC_OGAM_RAMA_EXP_REGION_START_SLOPE_B__SHIFT 0x00000000 + +// reg: VPMPCC_OGAM_RAMA_START_SLOPE_CNTL_G block: VPMPCC_OGAM comp: amd.com/lib/vpmpc-vpep2gn/1.0 +#define VPMPCC_OGAM_RAMA_START_SLOPE_CNTL_G__VPMPCC_OGAM_RAMA_EXP_REGION_START_SLOPE_G__SHIFT 0x00000000 + +// reg: VPMPCC_OGAM_RAMA_START_SLOPE_CNTL_R block: VPMPCC_OGAM comp: amd.com/lib/vpmpc-vpep2gn/1.0 +#define VPMPCC_OGAM_RAMA_START_SLOPE_CNTL_R__VPMPCC_OGAM_RAMA_EXP_REGION_START_SLOPE_R__SHIFT 0x00000000 + +// reg: VPMPCC_OGAM_RAMA_START_BASE_CNTL_B block: VPMPCC_OGAM comp: amd.com/lib/vpmpc-vpep2gn/1.0 +#define VPMPCC_OGAM_RAMA_START_BASE_CNTL_B__VPMPCC_OGAM_RAMA_EXP_REGION_START_BASE_B__SHIFT 0x00000000 + +// reg: VPMPCC_OGAM_RAMA_START_BASE_CNTL_G block: VPMPCC_OGAM comp: amd.com/lib/vpmpc-vpep2gn/1.0 +#define VPMPCC_OGAM_RAMA_START_BASE_CNTL_G__VPMPCC_OGAM_RAMA_EXP_REGION_START_BASE_G__SHIFT 0x00000000 + +// reg: VPMPCC_OGAM_RAMA_START_BASE_CNTL_R block: VPMPCC_OGAM comp: amd.com/lib/vpmpc-vpep2gn/1.0 +#define VPMPCC_OGAM_RAMA_START_BASE_CNTL_R__VPMPCC_OGAM_RAMA_EXP_REGION_START_BASE_R__SHIFT 0x00000000 + +// reg: VPMPCC_OGAM_RAMA_END_CNTL1_B block: VPMPCC_OGAM comp: amd.com/lib/vpmpc-vpep2gn/1.0 +#define VPMPCC_OGAM_RAMA_END_CNTL1_B__VPMPCC_OGAM_RAMA_EXP_REGION_END_BASE_B__SHIFT 0x00000000 + +// reg: VPMPCC_OGAM_RAMA_END_CNTL2_B block: VPMPCC_OGAM comp: amd.com/lib/vpmpc-vpep2gn/1.0 +#define VPMPCC_OGAM_RAMA_END_CNTL2_B__VPMPCC_OGAM_RAMA_EXP_REGION_END_B__SHIFT 0x00000000 +#define VPMPCC_OGAM_RAMA_END_CNTL2_B__VPMPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_B__SHIFT 0x00000010 + +// reg: VPMPCC_OGAM_RAMA_END_CNTL1_G block: VPMPCC_OGAM comp: amd.com/lib/vpmpc-vpep2gn/1.0 +#define VPMPCC_OGAM_RAMA_END_CNTL1_G__VPMPCC_OGAM_RAMA_EXP_REGION_END_BASE_G__SHIFT 0x00000000 + +// reg: VPMPCC_OGAM_RAMA_END_CNTL2_G block: VPMPCC_OGAM comp: amd.com/lib/vpmpc-vpep2gn/1.0 +#define VPMPCC_OGAM_RAMA_END_CNTL2_G__VPMPCC_OGAM_RAMA_EXP_REGION_END_G__SHIFT 0x00000000 +#define VPMPCC_OGAM_RAMA_END_CNTL2_G__VPMPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_G__SHIFT 0x00000010 + +// reg: VPMPCC_OGAM_RAMA_END_CNTL1_R block: VPMPCC_OGAM comp: amd.com/lib/vpmpc-vpep2gn/1.0 +#define VPMPCC_OGAM_RAMA_END_CNTL1_R__VPMPCC_OGAM_RAMA_EXP_REGION_END_BASE_R__SHIFT 0x00000000 + +// reg: VPMPCC_OGAM_RAMA_END_CNTL2_R block: VPMPCC_OGAM comp: amd.com/lib/vpmpc-vpep2gn/1.0 +#define VPMPCC_OGAM_RAMA_END_CNTL2_R__VPMPCC_OGAM_RAMA_EXP_REGION_END_R__SHIFT 0x00000000 +#define VPMPCC_OGAM_RAMA_END_CNTL2_R__VPMPCC_OGAM_RAMA_EXP_REGION_END_SLOPE_R__SHIFT 0x00000010 + +// reg: VPMPCC_OGAM_RAMA_OFFSET_B block: VPMPCC_OGAM comp: amd.com/lib/vpmpc-vpep2gn/1.0 +#define VPMPCC_OGAM_RAMA_OFFSET_B__VPMPCC_OGAM_RAMA_OFFSET_B__SHIFT 0x00000000 + +// reg: VPMPCC_OGAM_RAMA_OFFSET_G block: VPMPCC_OGAM comp: amd.com/lib/vpmpc-vpep2gn/1.0 +#define VPMPCC_OGAM_RAMA_OFFSET_G__VPMPCC_OGAM_RAMA_OFFSET_G__SHIFT 0x00000000 + +// reg: VPMPCC_OGAM_RAMA_OFFSET_R block: VPMPCC_OGAM comp: amd.com/lib/vpmpc-vpep2gn/1.0 +#define VPMPCC_OGAM_RAMA_OFFSET_R__VPMPCC_OGAM_RAMA_OFFSET_R__SHIFT 0x00000000 + +// reg: VPMPCC_OGAM_RAMA_REGION_0_1 block: VPMPCC_OGAM comp: amd.com/lib/vpmpc-vpep2gn/1.0 +#define VPMPCC_OGAM_RAMA_REGION_0_1__VPMPCC_OGAM_RAMA_EXP_REGION0_LUT_OFFSET__SHIFT 0x00000000 +#define VPMPCC_OGAM_RAMA_REGION_0_1__VPMPCC_OGAM_RAMA_EXP_REGION0_NUM_SEGMENTS__SHIFT 0x0000000c +#define VPMPCC_OGAM_RAMA_REGION_0_1__VPMPCC_OGAM_RAMA_EXP_REGION1_LUT_OFFSET__SHIFT 0x00000010 +#define VPMPCC_OGAM_RAMA_REGION_0_1__VPMPCC_OGAM_RAMA_EXP_REGION1_NUM_SEGMENTS__SHIFT 0x0000001c + +// reg: VPMPCC_OGAM_RAMA_REGION_2_3 block: VPMPCC_OGAM comp: amd.com/lib/vpmpc-vpep2gn/1.0 +#define VPMPCC_OGAM_RAMA_REGION_2_3__VPMPCC_OGAM_RAMA_EXP_REGION2_LUT_OFFSET__SHIFT 0x00000000 +#define VPMPCC_OGAM_RAMA_REGION_2_3__VPMPCC_OGAM_RAMA_EXP_REGION2_NUM_SEGMENTS__SHIFT 0x0000000c +#define VPMPCC_OGAM_RAMA_REGION_2_3__VPMPCC_OGAM_RAMA_EXP_REGION3_LUT_OFFSET__SHIFT 0x00000010 +#define VPMPCC_OGAM_RAMA_REGION_2_3__VPMPCC_OGAM_RAMA_EXP_REGION3_NUM_SEGMENTS__SHIFT 0x0000001c + +// reg: VPMPCC_OGAM_RAMA_REGION_4_5 block: VPMPCC_OGAM comp: amd.com/lib/vpmpc-vpep2gn/1.0 +#define VPMPCC_OGAM_RAMA_REGION_4_5__VPMPCC_OGAM_RAMA_EXP_REGION4_LUT_OFFSET__SHIFT 0x00000000 +#define VPMPCC_OGAM_RAMA_REGION_4_5__VPMPCC_OGAM_RAMA_EXP_REGION4_NUM_SEGMENTS__SHIFT 0x0000000c +#define VPMPCC_OGAM_RAMA_REGION_4_5__VPMPCC_OGAM_RAMA_EXP_REGION5_LUT_OFFSET__SHIFT 0x00000010 +#define VPMPCC_OGAM_RAMA_REGION_4_5__VPMPCC_OGAM_RAMA_EXP_REGION5_NUM_SEGMENTS__SHIFT 0x0000001c + +// reg: VPMPCC_OGAM_RAMA_REGION_6_7 block: VPMPCC_OGAM comp: amd.com/lib/vpmpc-vpep2gn/1.0 +#define VPMPCC_OGAM_RAMA_REGION_6_7__VPMPCC_OGAM_RAMA_EXP_REGION6_LUT_OFFSET__SHIFT 0x00000000 +#define VPMPCC_OGAM_RAMA_REGION_6_7__VPMPCC_OGAM_RAMA_EXP_REGION6_NUM_SEGMENTS__SHIFT 0x0000000c +#define VPMPCC_OGAM_RAMA_REGION_6_7__VPMPCC_OGAM_RAMA_EXP_REGION7_LUT_OFFSET__SHIFT 0x00000010 +#define VPMPCC_OGAM_RAMA_REGION_6_7__VPMPCC_OGAM_RAMA_EXP_REGION7_NUM_SEGMENTS__SHIFT 0x0000001c + +// reg: VPMPCC_OGAM_RAMA_REGION_8_9 block: VPMPCC_OGAM comp: amd.com/lib/vpmpc-vpep2gn/1.0 +#define VPMPCC_OGAM_RAMA_REGION_8_9__VPMPCC_OGAM_RAMA_EXP_REGION8_LUT_OFFSET__SHIFT 0x00000000 +#define VPMPCC_OGAM_RAMA_REGION_8_9__VPMPCC_OGAM_RAMA_EXP_REGION8_NUM_SEGMENTS__SHIFT 0x0000000c +#define VPMPCC_OGAM_RAMA_REGION_8_9__VPMPCC_OGAM_RAMA_EXP_REGION9_LUT_OFFSET__SHIFT 0x00000010 +#define VPMPCC_OGAM_RAMA_REGION_8_9__VPMPCC_OGAM_RAMA_EXP_REGION9_NUM_SEGMENTS__SHIFT 0x0000001c + +// reg: VPMPCC_OGAM_RAMA_REGION_10_11 block: VPMPCC_OGAM comp: amd.com/lib/vpmpc-vpep2gn/1.0 +#define VPMPCC_OGAM_RAMA_REGION_10_11__VPMPCC_OGAM_RAMA_EXP_REGION10_LUT_OFFSET__SHIFT 0x00000000 +#define VPMPCC_OGAM_RAMA_REGION_10_11__VPMPCC_OGAM_RAMA_EXP_REGION10_NUM_SEGMENTS__SHIFT 0x0000000c +#define VPMPCC_OGAM_RAMA_REGION_10_11__VPMPCC_OGAM_RAMA_EXP_REGION11_LUT_OFFSET__SHIFT 0x00000010 +#define VPMPCC_OGAM_RAMA_REGION_10_11__VPMPCC_OGAM_RAMA_EXP_REGION11_NUM_SEGMENTS__SHIFT 0x0000001c + +// reg: VPMPCC_OGAM_RAMA_REGION_12_13 block: VPMPCC_OGAM comp: amd.com/lib/vpmpc-vpep2gn/1.0 +#define VPMPCC_OGAM_RAMA_REGION_12_13__VPMPCC_OGAM_RAMA_EXP_REGION12_LUT_OFFSET__SHIFT 0x00000000 +#define VPMPCC_OGAM_RAMA_REGION_12_13__VPMPCC_OGAM_RAMA_EXP_REGION12_NUM_SEGMENTS__SHIFT 0x0000000c +#define VPMPCC_OGAM_RAMA_REGION_12_13__VPMPCC_OGAM_RAMA_EXP_REGION13_LUT_OFFSET__SHIFT 0x00000010 +#define VPMPCC_OGAM_RAMA_REGION_12_13__VPMPCC_OGAM_RAMA_EXP_REGION13_NUM_SEGMENTS__SHIFT 0x0000001c + +// reg: VPMPCC_OGAM_RAMA_REGION_14_15 block: VPMPCC_OGAM comp: amd.com/lib/vpmpc-vpep2gn/1.0 +#define VPMPCC_OGAM_RAMA_REGION_14_15__VPMPCC_OGAM_RAMA_EXP_REGION14_LUT_OFFSET__SHIFT 0x00000000 +#define VPMPCC_OGAM_RAMA_REGION_14_15__VPMPCC_OGAM_RAMA_EXP_REGION14_NUM_SEGMENTS__SHIFT 0x0000000c +#define VPMPCC_OGAM_RAMA_REGION_14_15__VPMPCC_OGAM_RAMA_EXP_REGION15_LUT_OFFSET__SHIFT 0x00000010 +#define VPMPCC_OGAM_RAMA_REGION_14_15__VPMPCC_OGAM_RAMA_EXP_REGION15_NUM_SEGMENTS__SHIFT 0x0000001c + +// reg: VPMPCC_OGAM_RAMA_REGION_16_17 block: VPMPCC_OGAM comp: amd.com/lib/vpmpc-vpep2gn/1.0 +#define VPMPCC_OGAM_RAMA_REGION_16_17__VPMPCC_OGAM_RAMA_EXP_REGION16_LUT_OFFSET__SHIFT 0x00000000 +#define VPMPCC_OGAM_RAMA_REGION_16_17__VPMPCC_OGAM_RAMA_EXP_REGION16_NUM_SEGMENTS__SHIFT 0x0000000c +#define VPMPCC_OGAM_RAMA_REGION_16_17__VPMPCC_OGAM_RAMA_EXP_REGION17_LUT_OFFSET__SHIFT 0x00000010 +#define VPMPCC_OGAM_RAMA_REGION_16_17__VPMPCC_OGAM_RAMA_EXP_REGION17_NUM_SEGMENTS__SHIFT 0x0000001c + +// reg: VPMPCC_OGAM_RAMA_REGION_18_19 block: VPMPCC_OGAM comp: amd.com/lib/vpmpc-vpep2gn/1.0 +#define VPMPCC_OGAM_RAMA_REGION_18_19__VPMPCC_OGAM_RAMA_EXP_REGION18_LUT_OFFSET__SHIFT 0x00000000 +#define VPMPCC_OGAM_RAMA_REGION_18_19__VPMPCC_OGAM_RAMA_EXP_REGION18_NUM_SEGMENTS__SHIFT 0x0000000c +#define VPMPCC_OGAM_RAMA_REGION_18_19__VPMPCC_OGAM_RAMA_EXP_REGION19_LUT_OFFSET__SHIFT 0x00000010 +#define VPMPCC_OGAM_RAMA_REGION_18_19__VPMPCC_OGAM_RAMA_EXP_REGION19_NUM_SEGMENTS__SHIFT 0x0000001c + +// reg: VPMPCC_OGAM_RAMA_REGION_20_21 block: VPMPCC_OGAM comp: amd.com/lib/vpmpc-vpep2gn/1.0 +#define VPMPCC_OGAM_RAMA_REGION_20_21__VPMPCC_OGAM_RAMA_EXP_REGION20_LUT_OFFSET__SHIFT 0x00000000 +#define VPMPCC_OGAM_RAMA_REGION_20_21__VPMPCC_OGAM_RAMA_EXP_REGION20_NUM_SEGMENTS__SHIFT 0x0000000c +#define VPMPCC_OGAM_RAMA_REGION_20_21__VPMPCC_OGAM_RAMA_EXP_REGION21_LUT_OFFSET__SHIFT 0x00000010 +#define VPMPCC_OGAM_RAMA_REGION_20_21__VPMPCC_OGAM_RAMA_EXP_REGION21_NUM_SEGMENTS__SHIFT 0x0000001c + +// reg: VPMPCC_OGAM_RAMA_REGION_22_23 block: VPMPCC_OGAM comp: amd.com/lib/vpmpc-vpep2gn/1.0 +#define VPMPCC_OGAM_RAMA_REGION_22_23__VPMPCC_OGAM_RAMA_EXP_REGION22_LUT_OFFSET__SHIFT 0x00000000 +#define VPMPCC_OGAM_RAMA_REGION_22_23__VPMPCC_OGAM_RAMA_EXP_REGION22_NUM_SEGMENTS__SHIFT 0x0000000c +#define VPMPCC_OGAM_RAMA_REGION_22_23__VPMPCC_OGAM_RAMA_EXP_REGION23_LUT_OFFSET__SHIFT 0x00000010 +#define VPMPCC_OGAM_RAMA_REGION_22_23__VPMPCC_OGAM_RAMA_EXP_REGION23_NUM_SEGMENTS__SHIFT 0x0000001c + +// reg: VPMPCC_OGAM_RAMA_REGION_24_25 block: VPMPCC_OGAM comp: amd.com/lib/vpmpc-vpep2gn/1.0 +#define VPMPCC_OGAM_RAMA_REGION_24_25__VPMPCC_OGAM_RAMA_EXP_REGION24_LUT_OFFSET__SHIFT 0x00000000 +#define VPMPCC_OGAM_RAMA_REGION_24_25__VPMPCC_OGAM_RAMA_EXP_REGION24_NUM_SEGMENTS__SHIFT 0x0000000c +#define VPMPCC_OGAM_RAMA_REGION_24_25__VPMPCC_OGAM_RAMA_EXP_REGION25_LUT_OFFSET__SHIFT 0x00000010 +#define VPMPCC_OGAM_RAMA_REGION_24_25__VPMPCC_OGAM_RAMA_EXP_REGION25_NUM_SEGMENTS__SHIFT 0x0000001c + +// reg: VPMPCC_OGAM_RAMA_REGION_26_27 block: VPMPCC_OGAM comp: amd.com/lib/vpmpc-vpep2gn/1.0 +#define VPMPCC_OGAM_RAMA_REGION_26_27__VPMPCC_OGAM_RAMA_EXP_REGION26_LUT_OFFSET__SHIFT 0x00000000 +#define VPMPCC_OGAM_RAMA_REGION_26_27__VPMPCC_OGAM_RAMA_EXP_REGION26_NUM_SEGMENTS__SHIFT 0x0000000c +#define VPMPCC_OGAM_RAMA_REGION_26_27__VPMPCC_OGAM_RAMA_EXP_REGION27_LUT_OFFSET__SHIFT 0x00000010 +#define VPMPCC_OGAM_RAMA_REGION_26_27__VPMPCC_OGAM_RAMA_EXP_REGION27_NUM_SEGMENTS__SHIFT 0x0000001c + +// reg: VPMPCC_OGAM_RAMA_REGION_28_29 block: VPMPCC_OGAM comp: amd.com/lib/vpmpc-vpep2gn/1.0 +#define VPMPCC_OGAM_RAMA_REGION_28_29__VPMPCC_OGAM_RAMA_EXP_REGION28_LUT_OFFSET__SHIFT 0x00000000 +#define VPMPCC_OGAM_RAMA_REGION_28_29__VPMPCC_OGAM_RAMA_EXP_REGION28_NUM_SEGMENTS__SHIFT 0x0000000c +#define VPMPCC_OGAM_RAMA_REGION_28_29__VPMPCC_OGAM_RAMA_EXP_REGION29_LUT_OFFSET__SHIFT 0x00000010 +#define VPMPCC_OGAM_RAMA_REGION_28_29__VPMPCC_OGAM_RAMA_EXP_REGION29_NUM_SEGMENTS__SHIFT 0x0000001c + +// reg: VPMPCC_OGAM_RAMA_REGION_30_31 block: VPMPCC_OGAM comp: amd.com/lib/vpmpc-vpep2gn/1.0 +#define VPMPCC_OGAM_RAMA_REGION_30_31__VPMPCC_OGAM_RAMA_EXP_REGION30_LUT_OFFSET__SHIFT 0x00000000 +#define VPMPCC_OGAM_RAMA_REGION_30_31__VPMPCC_OGAM_RAMA_EXP_REGION30_NUM_SEGMENTS__SHIFT 0x0000000c +#define VPMPCC_OGAM_RAMA_REGION_30_31__VPMPCC_OGAM_RAMA_EXP_REGION31_LUT_OFFSET__SHIFT 0x00000010 +#define VPMPCC_OGAM_RAMA_REGION_30_31__VPMPCC_OGAM_RAMA_EXP_REGION31_NUM_SEGMENTS__SHIFT 0x0000001c + +// reg: VPMPCC_OGAM_RAMA_REGION_32_33 block: VPMPCC_OGAM comp: amd.com/lib/vpmpc-vpep2gn/1.0 +#define VPMPCC_OGAM_RAMA_REGION_32_33__VPMPCC_OGAM_RAMA_EXP_REGION32_LUT_OFFSET__SHIFT 0x00000000 +#define VPMPCC_OGAM_RAMA_REGION_32_33__VPMPCC_OGAM_RAMA_EXP_REGION32_NUM_SEGMENTS__SHIFT 0x0000000c +#define VPMPCC_OGAM_RAMA_REGION_32_33__VPMPCC_OGAM_RAMA_EXP_REGION33_LUT_OFFSET__SHIFT 0x00000010 +#define VPMPCC_OGAM_RAMA_REGION_32_33__VPMPCC_OGAM_RAMA_EXP_REGION33_NUM_SEGMENTS__SHIFT 0x0000001c + +// reg: VPMPCC_GAMUT_REMAP_COEF_FORMAT block: VPMPCC_OGAM comp: amd.com/lib/vpmpc-vpep2gn/1.0 +#define VPMPCC_GAMUT_REMAP_COEF_FORMAT__VPMPCC_GAMUT_REMAP_COEF_FORMAT__SHIFT 0x00000000 + +// reg: VPMPCC_GAMUT_REMAP_MODE block: VPMPCC_OGAM comp: amd.com/lib/vpmpc-vpep2gn/1.0 +#define VPMPCC_GAMUT_REMAP_MODE__VPMPCC_GAMUT_REMAP_MODE__SHIFT 0x00000000 +#define VPMPCC_GAMUT_REMAP_MODE__VPMPCC_GAMUT_REMAP_MODE_CURRENT__SHIFT 0x00000007 + +// reg: VPMPC_GAMUT_REMAP_C11_C12_A block: VPMPCC_OGAM comp: amd.com/lib/vpmpc-vpep2gn/1.0 +#define VPMPC_GAMUT_REMAP_C11_C12_A__VPMPCC_GAMUT_REMAP_C11_A__SHIFT 0x00000000 +#define VPMPC_GAMUT_REMAP_C11_C12_A__VPMPCC_GAMUT_REMAP_C12_A__SHIFT 0x00000010 + +// reg: VPMPC_GAMUT_REMAP_C13_C14_A block: VPMPCC_OGAM comp: amd.com/lib/vpmpc-vpep2gn/1.0 +#define VPMPC_GAMUT_REMAP_C13_C14_A__VPMPCC_GAMUT_REMAP_C13_A__SHIFT 0x00000000 +#define VPMPC_GAMUT_REMAP_C13_C14_A__VPMPCC_GAMUT_REMAP_C14_A__SHIFT 0x00000010 + +// reg: VPMPC_GAMUT_REMAP_C21_C22_A block: VPMPCC_OGAM comp: amd.com/lib/vpmpc-vpep2gn/1.0 +#define VPMPC_GAMUT_REMAP_C21_C22_A__VPMPCC_GAMUT_REMAP_C21_A__SHIFT 0x00000000 +#define VPMPC_GAMUT_REMAP_C21_C22_A__VPMPCC_GAMUT_REMAP_C22_A__SHIFT 0x00000010 + +// reg: VPMPC_GAMUT_REMAP_C23_C24_A block: VPMPCC_OGAM comp: amd.com/lib/vpmpc-vpep2gn/1.0 +#define VPMPC_GAMUT_REMAP_C23_C24_A__VPMPCC_GAMUT_REMAP_C23_A__SHIFT 0x00000000 +#define VPMPC_GAMUT_REMAP_C23_C24_A__VPMPCC_GAMUT_REMAP_C24_A__SHIFT 0x00000010 + +// reg: VPMPC_GAMUT_REMAP_C31_C32_A block: VPMPCC_OGAM comp: amd.com/lib/vpmpc-vpep2gn/1.0 +#define VPMPC_GAMUT_REMAP_C31_C32_A__VPMPCC_GAMUT_REMAP_C31_A__SHIFT 0x00000000 +#define VPMPC_GAMUT_REMAP_C31_C32_A__VPMPCC_GAMUT_REMAP_C32_A__SHIFT 0x00000010 + +// reg: VPMPC_GAMUT_REMAP_C33_C34_A block: VPMPCC_OGAM comp: amd.com/lib/vpmpc-vpep2gn/1.0 +#define VPMPC_GAMUT_REMAP_C33_C34_A__VPMPCC_GAMUT_REMAP_C33_A__SHIFT 0x00000000 +#define VPMPC_GAMUT_REMAP_C33_C34_A__VPMPCC_GAMUT_REMAP_C34_A__SHIFT 0x00000010 + +// reg: VPMPCC_MCM_1DLUT_CONTROL block: VPMPCC_MCM comp: amd.com/lib/vpmpc-vpep2gn/1.0 +#define VPMPCC_MCM_1DLUT_CONTROL__VPMPCC_MCM_1DLUT_MODE__SHIFT 0x00000000 +#define VPMPCC_MCM_1DLUT_CONTROL__VPMPCC_MCM_1DLUT_PWL_DISABLE__SHIFT 0x00000003 +#define VPMPCC_MCM_1DLUT_CONTROL__VPMPCC_MCM_1DLUT_MODE_CURRENT__SHIFT 0x00000004 +#define VPMPCC_MCM_1DLUT_CONTROL__VPMPCC_MCM_1DLUT_SELECT_CURRENT__SHIFT 0x00000006 + +// reg: VPMPCC_MCM_1DLUT_LUT_INDEX block: VPMPCC_MCM comp: amd.com/lib/vpmpc-vpep2gn/1.0 +#define VPMPCC_MCM_1DLUT_LUT_INDEX__VPMPCC_MCM_1DLUT_LUT_INDEX__SHIFT 0x00000000 + +// reg: VPMPCC_MCM_1DLUT_LUT_DATA block: VPMPCC_MCM comp: amd.com/lib/vpmpc-vpep2gn/1.0 +#define VPMPCC_MCM_1DLUT_LUT_DATA__VPMPCC_MCM_1DLUT_LUT_DATA__SHIFT 0x00000000 + +// reg: VPMPCC_MCM_1DLUT_LUT_CONTROL block: VPMPCC_MCM comp: amd.com/lib/vpmpc-vpep2gn/1.0 +#define VPMPCC_MCM_1DLUT_LUT_CONTROL__VPMPCC_MCM_1DLUT_LUT_WRITE_COLOR_MASK__SHIFT 0x00000000 +#define VPMPCC_MCM_1DLUT_LUT_CONTROL__VPMPCC_MCM_1DLUT_LUT_READ_COLOR_SEL__SHIFT 0x00000003 +#define VPMPCC_MCM_1DLUT_LUT_CONTROL__VPMPCC_MCM_1DLUT_LUT_READ_DBG__SHIFT 0x00000005 +#define VPMPCC_MCM_1DLUT_LUT_CONTROL__VPMPCC_MCM_1DLUT_LUT_HOST_SEL__SHIFT 0x00000006 +#define VPMPCC_MCM_1DLUT_LUT_CONTROL__VPMPCC_MCM_1DLUT_LUT_CONFIG_MODE__SHIFT 0x00000007 + +// reg: VPMPCC_MCM_1DLUT_RAMA_START_CNTL_B block: VPMPCC_MCM comp: amd.com/lib/vpmpc-vpep2gn/1.0 +#define VPMPCC_MCM_1DLUT_RAMA_START_CNTL_B__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION_START_B__SHIFT 0x00000000 +#define VPMPCC_MCM_1DLUT_RAMA_START_CNTL_B__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SEGMENT_B__SHIFT 0x00000014 + +// reg: VPMPCC_MCM_1DLUT_RAMA_START_CNTL_G block: VPMPCC_MCM comp: amd.com/lib/vpmpc-vpep2gn/1.0 +#define VPMPCC_MCM_1DLUT_RAMA_START_CNTL_G__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION_START_G__SHIFT 0x00000000 +#define VPMPCC_MCM_1DLUT_RAMA_START_CNTL_G__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SEGMENT_G__SHIFT 0x00000014 + +// reg: VPMPCC_MCM_1DLUT_RAMA_START_CNTL_R block: VPMPCC_MCM comp: amd.com/lib/vpmpc-vpep2gn/1.0 +#define VPMPCC_MCM_1DLUT_RAMA_START_CNTL_R__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION_START_R__SHIFT 0x00000000 +#define VPMPCC_MCM_1DLUT_RAMA_START_CNTL_R__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SEGMENT_R__SHIFT 0x00000014 + +// reg: VPMPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_B block: VPMPCC_MCM comp: amd.com/lib/vpmpc-vpep2gn/1.0 +#define VPMPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_B__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SLOPE_B__SHIFT 0x00000000 + +// reg: VPMPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_G block: VPMPCC_MCM comp: amd.com/lib/vpmpc-vpep2gn/1.0 +#define VPMPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_G__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SLOPE_G__SHIFT 0x00000000 + +// reg: VPMPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_R block: VPMPCC_MCM comp: amd.com/lib/vpmpc-vpep2gn/1.0 +#define VPMPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_R__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION_START_SLOPE_R__SHIFT 0x00000000 + +// reg: VPMPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_B block: VPMPCC_MCM comp: amd.com/lib/vpmpc-vpep2gn/1.0 +#define VPMPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_B__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION_START_BASE_B__SHIFT 0x00000000 + +// reg: VPMPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_G block: VPMPCC_MCM comp: amd.com/lib/vpmpc-vpep2gn/1.0 +#define VPMPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_G__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION_START_BASE_G__SHIFT 0x00000000 + +// reg: VPMPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_R block: VPMPCC_MCM comp: amd.com/lib/vpmpc-vpep2gn/1.0 +#define VPMPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_R__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION_START_BASE_R__SHIFT 0x00000000 + +// reg: VPMPCC_MCM_1DLUT_RAMA_END_CNTL1_B block: VPMPCC_MCM comp: amd.com/lib/vpmpc-vpep2gn/1.0 +#define VPMPCC_MCM_1DLUT_RAMA_END_CNTL1_B__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION_END_BASE_B__SHIFT 0x00000000 + +// reg: VPMPCC_MCM_1DLUT_RAMA_END_CNTL2_B block: VPMPCC_MCM comp: amd.com/lib/vpmpc-vpep2gn/1.0 +#define VPMPCC_MCM_1DLUT_RAMA_END_CNTL2_B__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION_END_B__SHIFT 0x00000000 +#define VPMPCC_MCM_1DLUT_RAMA_END_CNTL2_B__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION_END_SLOPE_B__SHIFT 0x00000010 + +// reg: VPMPCC_MCM_1DLUT_RAMA_END_CNTL1_G block: VPMPCC_MCM comp: amd.com/lib/vpmpc-vpep2gn/1.0 +#define VPMPCC_MCM_1DLUT_RAMA_END_CNTL1_G__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION_END_BASE_G__SHIFT 0x00000000 + +// reg: VPMPCC_MCM_1DLUT_RAMA_END_CNTL2_G block: VPMPCC_MCM comp: amd.com/lib/vpmpc-vpep2gn/1.0 +#define VPMPCC_MCM_1DLUT_RAMA_END_CNTL2_G__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION_END_G__SHIFT 0x00000000 +#define VPMPCC_MCM_1DLUT_RAMA_END_CNTL2_G__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION_END_SLOPE_G__SHIFT 0x00000010 + +// reg: VPMPCC_MCM_1DLUT_RAMA_END_CNTL1_R block: VPMPCC_MCM comp: amd.com/lib/vpmpc-vpep2gn/1.0 +#define VPMPCC_MCM_1DLUT_RAMA_END_CNTL1_R__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION_END_BASE_R__SHIFT 0x00000000 + +// reg: VPMPCC_MCM_1DLUT_RAMA_END_CNTL2_R block: VPMPCC_MCM comp: amd.com/lib/vpmpc-vpep2gn/1.0 +#define VPMPCC_MCM_1DLUT_RAMA_END_CNTL2_R__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION_END_R__SHIFT 0x00000000 +#define VPMPCC_MCM_1DLUT_RAMA_END_CNTL2_R__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION_END_SLOPE_R__SHIFT 0x00000010 + +// reg: VPMPCC_MCM_1DLUT_RAMA_OFFSET_B block: VPMPCC_MCM comp: amd.com/lib/vpmpc-vpep2gn/1.0 +#define VPMPCC_MCM_1DLUT_RAMA_OFFSET_B__VPMPCC_MCM_1DLUT_RAMA_OFFSET_B__SHIFT 0x00000000 + +// reg: VPMPCC_MCM_1DLUT_RAMA_OFFSET_G block: VPMPCC_MCM comp: amd.com/lib/vpmpc-vpep2gn/1.0 +#define VPMPCC_MCM_1DLUT_RAMA_OFFSET_G__VPMPCC_MCM_1DLUT_RAMA_OFFSET_G__SHIFT 0x00000000 + +// reg: VPMPCC_MCM_1DLUT_RAMA_OFFSET_R block: VPMPCC_MCM comp: amd.com/lib/vpmpc-vpep2gn/1.0 +#define VPMPCC_MCM_1DLUT_RAMA_OFFSET_R__VPMPCC_MCM_1DLUT_RAMA_OFFSET_R__SHIFT 0x00000000 + +// reg: VPMPCC_MCM_1DLUT_RAMA_REGION_0_1 block: VPMPCC_MCM comp: amd.com/lib/vpmpc-vpep2gn/1.0 +#define VPMPCC_MCM_1DLUT_RAMA_REGION_0_1__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION0_LUT_OFFSET__SHIFT 0x00000000 +#define VPMPCC_MCM_1DLUT_RAMA_REGION_0_1__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION0_NUM_SEGMENTS__SHIFT 0x0000000c +#define VPMPCC_MCM_1DLUT_RAMA_REGION_0_1__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION1_LUT_OFFSET__SHIFT 0x00000010 +#define VPMPCC_MCM_1DLUT_RAMA_REGION_0_1__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION1_NUM_SEGMENTS__SHIFT 0x0000001c + +// reg: VPMPCC_MCM_1DLUT_RAMA_REGION_2_3 block: VPMPCC_MCM comp: amd.com/lib/vpmpc-vpep2gn/1.0 +#define VPMPCC_MCM_1DLUT_RAMA_REGION_2_3__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION2_LUT_OFFSET__SHIFT 0x00000000 +#define VPMPCC_MCM_1DLUT_RAMA_REGION_2_3__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION2_NUM_SEGMENTS__SHIFT 0x0000000c +#define VPMPCC_MCM_1DLUT_RAMA_REGION_2_3__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION3_LUT_OFFSET__SHIFT 0x00000010 +#define VPMPCC_MCM_1DLUT_RAMA_REGION_2_3__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION3_NUM_SEGMENTS__SHIFT 0x0000001c + +// reg: VPMPCC_MCM_1DLUT_RAMA_REGION_4_5 block: VPMPCC_MCM comp: amd.com/lib/vpmpc-vpep2gn/1.0 +#define VPMPCC_MCM_1DLUT_RAMA_REGION_4_5__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION4_LUT_OFFSET__SHIFT 0x00000000 +#define VPMPCC_MCM_1DLUT_RAMA_REGION_4_5__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION4_NUM_SEGMENTS__SHIFT 0x0000000c +#define VPMPCC_MCM_1DLUT_RAMA_REGION_4_5__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION5_LUT_OFFSET__SHIFT 0x00000010 +#define VPMPCC_MCM_1DLUT_RAMA_REGION_4_5__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION5_NUM_SEGMENTS__SHIFT 0x0000001c + +// reg: VPMPCC_MCM_1DLUT_RAMA_REGION_6_7 block: VPMPCC_MCM comp: amd.com/lib/vpmpc-vpep2gn/1.0 +#define VPMPCC_MCM_1DLUT_RAMA_REGION_6_7__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION6_LUT_OFFSET__SHIFT 0x00000000 +#define VPMPCC_MCM_1DLUT_RAMA_REGION_6_7__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION6_NUM_SEGMENTS__SHIFT 0x0000000c +#define VPMPCC_MCM_1DLUT_RAMA_REGION_6_7__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION7_LUT_OFFSET__SHIFT 0x00000010 +#define VPMPCC_MCM_1DLUT_RAMA_REGION_6_7__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION7_NUM_SEGMENTS__SHIFT 0x0000001c + +// reg: VPMPCC_MCM_1DLUT_RAMA_REGION_8_9 block: VPMPCC_MCM comp: amd.com/lib/vpmpc-vpep2gn/1.0 +#define VPMPCC_MCM_1DLUT_RAMA_REGION_8_9__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION8_LUT_OFFSET__SHIFT 0x00000000 +#define VPMPCC_MCM_1DLUT_RAMA_REGION_8_9__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION8_NUM_SEGMENTS__SHIFT 0x0000000c +#define VPMPCC_MCM_1DLUT_RAMA_REGION_8_9__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION9_LUT_OFFSET__SHIFT 0x00000010 +#define VPMPCC_MCM_1DLUT_RAMA_REGION_8_9__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION9_NUM_SEGMENTS__SHIFT 0x0000001c + +// reg: VPMPCC_MCM_1DLUT_RAMA_REGION_10_11 block: VPMPCC_MCM comp: amd.com/lib/vpmpc-vpep2gn/1.0 +#define VPMPCC_MCM_1DLUT_RAMA_REGION_10_11__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION10_LUT_OFFSET__SHIFT 0x00000000 +#define VPMPCC_MCM_1DLUT_RAMA_REGION_10_11__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION10_NUM_SEGMENTS__SHIFT 0x0000000c +#define VPMPCC_MCM_1DLUT_RAMA_REGION_10_11__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION11_LUT_OFFSET__SHIFT 0x00000010 +#define VPMPCC_MCM_1DLUT_RAMA_REGION_10_11__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION11_NUM_SEGMENTS__SHIFT 0x0000001c + +// reg: VPMPCC_MCM_1DLUT_RAMA_REGION_12_13 block: VPMPCC_MCM comp: amd.com/lib/vpmpc-vpep2gn/1.0 +#define VPMPCC_MCM_1DLUT_RAMA_REGION_12_13__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION12_LUT_OFFSET__SHIFT 0x00000000 +#define VPMPCC_MCM_1DLUT_RAMA_REGION_12_13__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION12_NUM_SEGMENTS__SHIFT 0x0000000c +#define VPMPCC_MCM_1DLUT_RAMA_REGION_12_13__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION13_LUT_OFFSET__SHIFT 0x00000010 +#define VPMPCC_MCM_1DLUT_RAMA_REGION_12_13__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION13_NUM_SEGMENTS__SHIFT 0x0000001c + +// reg: VPMPCC_MCM_1DLUT_RAMA_REGION_14_15 block: VPMPCC_MCM comp: amd.com/lib/vpmpc-vpep2gn/1.0 +#define VPMPCC_MCM_1DLUT_RAMA_REGION_14_15__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION14_LUT_OFFSET__SHIFT 0x00000000 +#define VPMPCC_MCM_1DLUT_RAMA_REGION_14_15__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION14_NUM_SEGMENTS__SHIFT 0x0000000c +#define VPMPCC_MCM_1DLUT_RAMA_REGION_14_15__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION15_LUT_OFFSET__SHIFT 0x00000010 +#define VPMPCC_MCM_1DLUT_RAMA_REGION_14_15__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION15_NUM_SEGMENTS__SHIFT 0x0000001c + +// reg: VPMPCC_MCM_1DLUT_RAMA_REGION_16_17 block: VPMPCC_MCM comp: amd.com/lib/vpmpc-vpep2gn/1.0 +#define VPMPCC_MCM_1DLUT_RAMA_REGION_16_17__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION16_LUT_OFFSET__SHIFT 0x00000000 +#define VPMPCC_MCM_1DLUT_RAMA_REGION_16_17__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION16_NUM_SEGMENTS__SHIFT 0x0000000c +#define VPMPCC_MCM_1DLUT_RAMA_REGION_16_17__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION17_LUT_OFFSET__SHIFT 0x00000010 +#define VPMPCC_MCM_1DLUT_RAMA_REGION_16_17__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION17_NUM_SEGMENTS__SHIFT 0x0000001c + +// reg: VPMPCC_MCM_1DLUT_RAMA_REGION_18_19 block: VPMPCC_MCM comp: amd.com/lib/vpmpc-vpep2gn/1.0 +#define VPMPCC_MCM_1DLUT_RAMA_REGION_18_19__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION18_LUT_OFFSET__SHIFT 0x00000000 +#define VPMPCC_MCM_1DLUT_RAMA_REGION_18_19__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION18_NUM_SEGMENTS__SHIFT 0x0000000c +#define VPMPCC_MCM_1DLUT_RAMA_REGION_18_19__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION19_LUT_OFFSET__SHIFT 0x00000010 +#define VPMPCC_MCM_1DLUT_RAMA_REGION_18_19__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION19_NUM_SEGMENTS__SHIFT 0x0000001c + +// reg: VPMPCC_MCM_1DLUT_RAMA_REGION_20_21 block: VPMPCC_MCM comp: amd.com/lib/vpmpc-vpep2gn/1.0 +#define VPMPCC_MCM_1DLUT_RAMA_REGION_20_21__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION20_LUT_OFFSET__SHIFT 0x00000000 +#define VPMPCC_MCM_1DLUT_RAMA_REGION_20_21__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION20_NUM_SEGMENTS__SHIFT 0x0000000c +#define VPMPCC_MCM_1DLUT_RAMA_REGION_20_21__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION21_LUT_OFFSET__SHIFT 0x00000010 +#define VPMPCC_MCM_1DLUT_RAMA_REGION_20_21__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION21_NUM_SEGMENTS__SHIFT 0x0000001c + +// reg: VPMPCC_MCM_1DLUT_RAMA_REGION_22_23 block: VPMPCC_MCM comp: amd.com/lib/vpmpc-vpep2gn/1.0 +#define VPMPCC_MCM_1DLUT_RAMA_REGION_22_23__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION22_LUT_OFFSET__SHIFT 0x00000000 +#define VPMPCC_MCM_1DLUT_RAMA_REGION_22_23__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION22_NUM_SEGMENTS__SHIFT 0x0000000c +#define VPMPCC_MCM_1DLUT_RAMA_REGION_22_23__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION23_LUT_OFFSET__SHIFT 0x00000010 +#define VPMPCC_MCM_1DLUT_RAMA_REGION_22_23__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION23_NUM_SEGMENTS__SHIFT 0x0000001c + +// reg: VPMPCC_MCM_1DLUT_RAMA_REGION_24_25 block: VPMPCC_MCM comp: amd.com/lib/vpmpc-vpep2gn/1.0 +#define VPMPCC_MCM_1DLUT_RAMA_REGION_24_25__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION24_LUT_OFFSET__SHIFT 0x00000000 +#define VPMPCC_MCM_1DLUT_RAMA_REGION_24_25__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION24_NUM_SEGMENTS__SHIFT 0x0000000c +#define VPMPCC_MCM_1DLUT_RAMA_REGION_24_25__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION25_LUT_OFFSET__SHIFT 0x00000010 +#define VPMPCC_MCM_1DLUT_RAMA_REGION_24_25__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION25_NUM_SEGMENTS__SHIFT 0x0000001c + +// reg: VPMPCC_MCM_1DLUT_RAMA_REGION_26_27 block: VPMPCC_MCM comp: amd.com/lib/vpmpc-vpep2gn/1.0 +#define VPMPCC_MCM_1DLUT_RAMA_REGION_26_27__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION26_LUT_OFFSET__SHIFT 0x00000000 +#define VPMPCC_MCM_1DLUT_RAMA_REGION_26_27__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION26_NUM_SEGMENTS__SHIFT 0x0000000c +#define VPMPCC_MCM_1DLUT_RAMA_REGION_26_27__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION27_LUT_OFFSET__SHIFT 0x00000010 +#define VPMPCC_MCM_1DLUT_RAMA_REGION_26_27__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION27_NUM_SEGMENTS__SHIFT 0x0000001c + +// reg: VPMPCC_MCM_1DLUT_RAMA_REGION_28_29 block: VPMPCC_MCM comp: amd.com/lib/vpmpc-vpep2gn/1.0 +#define VPMPCC_MCM_1DLUT_RAMA_REGION_28_29__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION28_LUT_OFFSET__SHIFT 0x00000000 +#define VPMPCC_MCM_1DLUT_RAMA_REGION_28_29__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION28_NUM_SEGMENTS__SHIFT 0x0000000c +#define VPMPCC_MCM_1DLUT_RAMA_REGION_28_29__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION29_LUT_OFFSET__SHIFT 0x00000010 +#define VPMPCC_MCM_1DLUT_RAMA_REGION_28_29__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION29_NUM_SEGMENTS__SHIFT 0x0000001c + +// reg: VPMPCC_MCM_1DLUT_RAMA_REGION_30_31 block: VPMPCC_MCM comp: amd.com/lib/vpmpc-vpep2gn/1.0 +#define VPMPCC_MCM_1DLUT_RAMA_REGION_30_31__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION30_LUT_OFFSET__SHIFT 0x00000000 +#define VPMPCC_MCM_1DLUT_RAMA_REGION_30_31__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION30_NUM_SEGMENTS__SHIFT 0x0000000c +#define VPMPCC_MCM_1DLUT_RAMA_REGION_30_31__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION31_LUT_OFFSET__SHIFT 0x00000010 +#define VPMPCC_MCM_1DLUT_RAMA_REGION_30_31__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION31_NUM_SEGMENTS__SHIFT 0x0000001c + +// reg: VPMPCC_MCM_1DLUT_RAMA_REGION_32_33 block: VPMPCC_MCM comp: amd.com/lib/vpmpc-vpep2gn/1.0 +#define VPMPCC_MCM_1DLUT_RAMA_REGION_32_33__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION32_LUT_OFFSET__SHIFT 0x00000000 +#define VPMPCC_MCM_1DLUT_RAMA_REGION_32_33__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION32_NUM_SEGMENTS__SHIFT 0x0000000c +#define VPMPCC_MCM_1DLUT_RAMA_REGION_32_33__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION33_LUT_OFFSET__SHIFT 0x00000010 +#define VPMPCC_MCM_1DLUT_RAMA_REGION_32_33__VPMPCC_MCM_1DLUT_RAMA_EXP_REGION33_NUM_SEGMENTS__SHIFT 0x0000001c + +// reg: VPMPCC_MCM_FIRST_GAMUT_REMAP_COEF_FORMAT block: VPMPCC_MCM comp: amd.com/lib/vpmpc-vpep2gn/1.0 +#define VPMPCC_MCM_FIRST_GAMUT_REMAP_COEF_FORMAT__VPMPCC_MCM_FIRST_GAMUT_REMAP_COEF_FORMAT__SHIFT 0x00000000 + +// reg: VPMPCC_MCM_FIRST_GAMUT_REMAP_MODE block: VPMPCC_MCM comp: amd.com/lib/vpmpc-vpep2gn/1.0 +#define VPMPCC_MCM_FIRST_GAMUT_REMAP_MODE__VPMPCC_MCM_FIRST_GAMUT_REMAP_MODE__SHIFT 0x00000000 +#define VPMPCC_MCM_FIRST_GAMUT_REMAP_MODE__VPMPCC_MCM_FIRST_GAMUT_REMAP_MODE_CURRENT__SHIFT 0x00000007 + +// reg: VPMPC_MCM_FIRST_GAMUT_REMAP_C11_C12_SETA block: VPMPCC_MCM comp: amd.com/lib/vpmpc-vpep2gn/1.0 +#define VPMPC_MCM_FIRST_GAMUT_REMAP_C11_C12_SETA__VPMPCC_MCM_FIRST_GAMUT_REMAP_C11_SETA__SHIFT 0x00000000 +#define VPMPC_MCM_FIRST_GAMUT_REMAP_C11_C12_SETA__VPMPCC_MCM_FIRST_GAMUT_REMAP_C12_SETA__SHIFT 0x00000010 + +// reg: VPMPC_MCM_FIRST_GAMUT_REMAP_C13_C14_SETA block: VPMPCC_MCM comp: amd.com/lib/vpmpc-vpep2gn/1.0 +#define VPMPC_MCM_FIRST_GAMUT_REMAP_C13_C14_SETA__VPMPCC_MCM_FIRST_GAMUT_REMAP_C13_SETA__SHIFT 0x00000000 +#define VPMPC_MCM_FIRST_GAMUT_REMAP_C13_C14_SETA__VPMPCC_MCM_FIRST_GAMUT_REMAP_C14_SETA__SHIFT 0x00000010 + +// reg: VPMPC_MCM_FIRST_GAMUT_REMAP_C21_C22_SETA block: VPMPCC_MCM comp: amd.com/lib/vpmpc-vpep2gn/1.0 +#define VPMPC_MCM_FIRST_GAMUT_REMAP_C21_C22_SETA__VPMPCC_MCM_FIRST_GAMUT_REMAP_C21_SETA__SHIFT 0x00000000 +#define VPMPC_MCM_FIRST_GAMUT_REMAP_C21_C22_SETA__VPMPCC_MCM_FIRST_GAMUT_REMAP_C22_SETA__SHIFT 0x00000010 + +// reg: VPMPC_MCM_FIRST_GAMUT_REMAP_C23_C24_SETA block: VPMPCC_MCM comp: amd.com/lib/vpmpc-vpep2gn/1.0 +#define VPMPC_MCM_FIRST_GAMUT_REMAP_C23_C24_SETA__VPMPCC_MCM_FIRST_GAMUT_REMAP_C23_SETA__SHIFT 0x00000000 +#define VPMPC_MCM_FIRST_GAMUT_REMAP_C23_C24_SETA__VPMPCC_MCM_FIRST_GAMUT_REMAP_C24_SETA__SHIFT 0x00000010 + +// reg: VPMPC_MCM_FIRST_GAMUT_REMAP_C31_C32_SETA block: VPMPCC_MCM comp: amd.com/lib/vpmpc-vpep2gn/1.0 +#define VPMPC_MCM_FIRST_GAMUT_REMAP_C31_C32_SETA__VPMPCC_MCM_FIRST_GAMUT_REMAP_C31_SETA__SHIFT 0x00000000 +#define VPMPC_MCM_FIRST_GAMUT_REMAP_C31_C32_SETA__VPMPCC_MCM_FIRST_GAMUT_REMAP_C32_SETA__SHIFT 0x00000010 + +// reg: VPMPC_MCM_FIRST_GAMUT_REMAP_C33_C34_SETA block: VPMPCC_MCM comp: amd.com/lib/vpmpc-vpep2gn/1.0 +#define VPMPC_MCM_FIRST_GAMUT_REMAP_C33_C34_SETA__VPMPCC_MCM_FIRST_GAMUT_REMAP_C33_SETA__SHIFT 0x00000000 +#define VPMPC_MCM_FIRST_GAMUT_REMAP_C33_C34_SETA__VPMPCC_MCM_FIRST_GAMUT_REMAP_C34_SETA__SHIFT 0x00000010 + +// reg: VPMPCC_MCM_SECOND_GAMUT_REMAP_COEF_FORMAT block: VPMPCC_MCM comp: amd.com/lib/vpmpc-vpep2gn/1.0 +#define VPMPCC_MCM_SECOND_GAMUT_REMAP_COEF_FORMAT__VPMPCC_MCM_SECOND_GAMUT_REMAP_COEF_FORMAT__SHIFT 0x00000000 + +// reg: VPMPCC_MCM_SECOND_GAMUT_REMAP_MODE block: VPMPCC_MCM comp: amd.com/lib/vpmpc-vpep2gn/1.0 +#define VPMPCC_MCM_SECOND_GAMUT_REMAP_MODE__VPMPCC_MCM_SECOND_GAMUT_REMAP_MODE__SHIFT 0x00000000 +#define VPMPCC_MCM_SECOND_GAMUT_REMAP_MODE__VPMPCC_MCM_SECOND_GAMUT_REMAP_MODE_CURRENT__SHIFT 0x00000007 + +// reg: VPMPC_MCM_SECOND_GAMUT_REMAP_C11_C12_SETA block: VPMPCC_MCM comp: amd.com/lib/vpmpc-vpep2gn/1.0 +#define VPMPC_MCM_SECOND_GAMUT_REMAP_C11_C12_SETA__VPMPCC_MCM_SECOND_GAMUT_REMAP_C11_SETA__SHIFT 0x00000000 +#define VPMPC_MCM_SECOND_GAMUT_REMAP_C11_C12_SETA__VPMPCC_MCM_SECOND_GAMUT_REMAP_C12_SETA__SHIFT 0x00000010 + +// reg: VPMPC_MCM_SECOND_GAMUT_REMAP_C13_C14_SETA block: VPMPCC_MCM comp: amd.com/lib/vpmpc-vpep2gn/1.0 +#define VPMPC_MCM_SECOND_GAMUT_REMAP_C13_C14_SETA__VPMPCC_MCM_SECOND_GAMUT_REMAP_C13_SETA__SHIFT 0x00000000 +#define VPMPC_MCM_SECOND_GAMUT_REMAP_C13_C14_SETA__VPMPCC_MCM_SECOND_GAMUT_REMAP_C14_SETA__SHIFT 0x00000010 + +// reg: VPMPC_MCM_SECOND_GAMUT_REMAP_C21_C22_SETA block: VPMPCC_MCM comp: amd.com/lib/vpmpc-vpep2gn/1.0 +#define VPMPC_MCM_SECOND_GAMUT_REMAP_C21_C22_SETA__VPMPCC_MCM_SECOND_GAMUT_REMAP_C21_SETA__SHIFT 0x00000000 +#define VPMPC_MCM_SECOND_GAMUT_REMAP_C21_C22_SETA__VPMPCC_MCM_SECOND_GAMUT_REMAP_C22_SETA__SHIFT 0x00000010 + +// reg: VPMPC_MCM_SECOND_GAMUT_REMAP_C23_C24_SETA block: VPMPCC_MCM comp: amd.com/lib/vpmpc-vpep2gn/1.0 +#define VPMPC_MCM_SECOND_GAMUT_REMAP_C23_C24_SETA__VPMPCC_MCM_SECOND_GAMUT_REMAP_C23_SETA__SHIFT 0x00000000 +#define VPMPC_MCM_SECOND_GAMUT_REMAP_C23_C24_SETA__VPMPCC_MCM_SECOND_GAMUT_REMAP_C24_SETA__SHIFT 0x00000010 + +// reg: VPMPC_MCM_SECOND_GAMUT_REMAP_C31_C32_SETA block: VPMPCC_MCM comp: amd.com/lib/vpmpc-vpep2gn/1.0 +#define VPMPC_MCM_SECOND_GAMUT_REMAP_C31_C32_SETA__VPMPCC_MCM_SECOND_GAMUT_REMAP_C31_SETA__SHIFT 0x00000000 +#define VPMPC_MCM_SECOND_GAMUT_REMAP_C31_C32_SETA__VPMPCC_MCM_SECOND_GAMUT_REMAP_C32_SETA__SHIFT 0x00000010 + +// reg: VPMPC_MCM_SECOND_GAMUT_REMAP_C33_C34_SETA block: VPMPCC_MCM comp: amd.com/lib/vpmpc-vpep2gn/1.0 +#define VPMPC_MCM_SECOND_GAMUT_REMAP_C33_C34_SETA__VPMPCC_MCM_SECOND_GAMUT_REMAP_C33_SETA__SHIFT 0x00000000 +#define VPMPC_MCM_SECOND_GAMUT_REMAP_C33_C34_SETA__VPMPCC_MCM_SECOND_GAMUT_REMAP_C34_SETA__SHIFT 0x00000010 + +// reg: VPMPCC_MCM_MEM_PWR_CTRL block: VPMPCC_MCM comp: amd.com/lib/vpmpc-vpep2gn/1.0 +#define VPMPCC_MCM_MEM_PWR_CTRL__VPMPCC_MCM_1DLUT_MEM_PWR_FORCE__SHIFT 0x00000010 +#define VPMPCC_MCM_MEM_PWR_CTRL__VPMPCC_MCM_1DLUT_MEM_PWR_DIS__SHIFT 0x00000012 +#define VPMPCC_MCM_MEM_PWR_CTRL__VPMPCC_MCM_1DLUT_MEM_LOW_PWR_MODE__SHIFT 0x00000014 +#define VPMPCC_MCM_MEM_PWR_CTRL__VPMPCC_MCM_1DLUT_MEM_PWR_STATE__SHIFT 0x0000001c + +// reg: VPMPC_RMCM_SHAPER_CONTROL block: VPMPC_RMCM comp: amd.com/lib/vpmpc-vpep2gn/1.0 +#define VPMPC_RMCM_SHAPER_CONTROL__VPMPC_RMCM_SHAPER_LUT_MODE__SHIFT 0x00000000 +#define VPMPC_RMCM_SHAPER_CONTROL__VPMPC_RMCM_SHAPER_MODE_CURRENT__SHIFT 0x00000002 +#define VPMPC_RMCM_SHAPER_CONTROL__VPMPC_RMCM_SHAPER_SELECT_CURRENT__SHIFT 0x00000004 + +// reg: VPMPC_RMCM_SHAPER_OFFSET_R block: VPMPC_RMCM comp: amd.com/lib/vpmpc-vpep2gn/1.0 +#define VPMPC_RMCM_SHAPER_OFFSET_R__VPMPC_RMCM_SHAPER_OFFSET_R__SHIFT 0x00000000 + +// reg: VPMPC_RMCM_SHAPER_OFFSET_G block: VPMPC_RMCM comp: amd.com/lib/vpmpc-vpep2gn/1.0 +#define VPMPC_RMCM_SHAPER_OFFSET_G__VPMPC_RMCM_SHAPER_OFFSET_G__SHIFT 0x00000000 + +// reg: VPMPC_RMCM_SHAPER_OFFSET_B block: VPMPC_RMCM comp: amd.com/lib/vpmpc-vpep2gn/1.0 +#define VPMPC_RMCM_SHAPER_OFFSET_B__VPMPC_RMCM_SHAPER_OFFSET_B__SHIFT 0x00000000 + +// reg: VPMPC_RMCM_SHAPER_SCALE_R block: VPMPC_RMCM comp: amd.com/lib/vpmpc-vpep2gn/1.0 +#define VPMPC_RMCM_SHAPER_SCALE_R__VPMPC_RMCM_SHAPER_SCALE_R__SHIFT 0x00000000 + +// reg: VPMPC_RMCM_SHAPER_SCALE_G_B block: VPMPC_RMCM comp: amd.com/lib/vpmpc-vpep2gn/1.0 +#define VPMPC_RMCM_SHAPER_SCALE_G_B__VPMPC_RMCM_SHAPER_SCALE_G__SHIFT 0x00000000 +#define VPMPC_RMCM_SHAPER_SCALE_G_B__VPMPC_RMCM_SHAPER_SCALE_B__SHIFT 0x00000010 + +// reg: VPMPC_RMCM_SHAPER_LUT_INDEX block: VPMPC_RMCM comp: amd.com/lib/vpmpc-vpep2gn/1.0 +#define VPMPC_RMCM_SHAPER_LUT_INDEX__VPMPC_RMCM_SHAPER_LUT_INDEX__SHIFT 0x00000000 + +// reg: VPMPC_RMCM_SHAPER_LUT_DATA block: VPMPC_RMCM comp: amd.com/lib/vpmpc-vpep2gn/1.0 +#define VPMPC_RMCM_SHAPER_LUT_DATA__VPMPC_RMCM_SHAPER_LUT_DATA__SHIFT 0x00000000 + +// reg: VPMPC_RMCM_SHAPER_LUT_WRITE_EN_MASK block: VPMPC_RMCM comp: amd.com/lib/vpmpc-vpep2gn/1.0 +#define VPMPC_RMCM_SHAPER_LUT_WRITE_EN_MASK__VPMPC_RMCM_SHAPER_LUT_WRITE_EN_MASK__SHIFT 0x00000000 +#define VPMPC_RMCM_SHAPER_LUT_WRITE_EN_MASK__VPMPC_RMCM_SHAPER_LUT_WRITE_SEL__SHIFT 0x00000004 + +// reg: VPMPC_RMCM_SHAPER_RAMA_START_CNTL_B block: VPMPC_RMCM comp: amd.com/lib/vpmpc-vpep2gn/1.0 +#define VPMPC_RMCM_SHAPER_RAMA_START_CNTL_B__VPMPC_RMCM_SHAPER_RAMA_EXP_REGION_START_B__SHIFT 0x00000000 +#define VPMPC_RMCM_SHAPER_RAMA_START_CNTL_B__VPMPC_RMCM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_B__SHIFT 0x00000014 + +// reg: VPMPC_RMCM_SHAPER_RAMA_START_CNTL_G block: VPMPC_RMCM comp: amd.com/lib/vpmpc-vpep2gn/1.0 +#define VPMPC_RMCM_SHAPER_RAMA_START_CNTL_G__VPMPC_RMCM_SHAPER_RAMA_EXP_REGION_START_G__SHIFT 0x00000000 +#define VPMPC_RMCM_SHAPER_RAMA_START_CNTL_G__VPMPC_RMCM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_G__SHIFT 0x00000014 + +// reg: VPMPC_RMCM_SHAPER_RAMA_START_CNTL_R block: VPMPC_RMCM comp: amd.com/lib/vpmpc-vpep2gn/1.0 +#define VPMPC_RMCM_SHAPER_RAMA_START_CNTL_R__VPMPC_RMCM_SHAPER_RAMA_EXP_REGION_START_R__SHIFT 0x00000000 +#define VPMPC_RMCM_SHAPER_RAMA_START_CNTL_R__VPMPC_RMCM_SHAPER_RAMA_EXP_REGION_START_SEGMENT_R__SHIFT 0x00000014 + +// reg: VPMPC_RMCM_SHAPER_RAMA_END_CNTL_B block: VPMPC_RMCM comp: amd.com/lib/vpmpc-vpep2gn/1.0 +#define VPMPC_RMCM_SHAPER_RAMA_END_CNTL_B__VPMPC_RMCM_SHAPER_RAMA_EXP_REGION_END_B__SHIFT 0x00000000 +#define VPMPC_RMCM_SHAPER_RAMA_END_CNTL_B__VPMPC_RMCM_SHAPER_RAMA_EXP_REGION_END_BASE_B__SHIFT 0x00000010 + +// reg: VPMPC_RMCM_SHAPER_RAMA_END_CNTL_G block: VPMPC_RMCM comp: amd.com/lib/vpmpc-vpep2gn/1.0 +#define VPMPC_RMCM_SHAPER_RAMA_END_CNTL_G__VPMPC_RMCM_SHAPER_RAMA_EXP_REGION_END_G__SHIFT 0x00000000 +#define VPMPC_RMCM_SHAPER_RAMA_END_CNTL_G__VPMPC_RMCM_SHAPER_RAMA_EXP_REGION_END_BASE_G__SHIFT 0x00000010 + +// reg: VPMPC_RMCM_SHAPER_RAMA_END_CNTL_R block: VPMPC_RMCM comp: amd.com/lib/vpmpc-vpep2gn/1.0 +#define VPMPC_RMCM_SHAPER_RAMA_END_CNTL_R__VPMPC_RMCM_SHAPER_RAMA_EXP_REGION_END_R__SHIFT 0x00000000 +#define VPMPC_RMCM_SHAPER_RAMA_END_CNTL_R__VPMPC_RMCM_SHAPER_RAMA_EXP_REGION_END_BASE_R__SHIFT 0x00000010 + +// reg: VPMPC_RMCM_SHAPER_RAMA_REGION_0_1 block: VPMPC_RMCM comp: amd.com/lib/vpmpc-vpep2gn/1.0 +#define VPMPC_RMCM_SHAPER_RAMA_REGION_0_1__VPMPC_RMCM_SHAPER_RAMA_EXP_REGION0_LUT_OFFSET__SHIFT 0x00000000 +#define VPMPC_RMCM_SHAPER_RAMA_REGION_0_1__VPMPC_RMCM_SHAPER_RAMA_EXP_REGION0_NUM_SEGMENTS__SHIFT 0x0000000c +#define VPMPC_RMCM_SHAPER_RAMA_REGION_0_1__VPMPC_RMCM_SHAPER_RAMA_EXP_REGION1_LUT_OFFSET__SHIFT 0x00000010 +#define VPMPC_RMCM_SHAPER_RAMA_REGION_0_1__VPMPC_RMCM_SHAPER_RAMA_EXP_REGION1_NUM_SEGMENTS__SHIFT 0x0000001c + +// reg: VPMPC_RMCM_SHAPER_RAMA_REGION_2_3 block: VPMPC_RMCM comp: amd.com/lib/vpmpc-vpep2gn/1.0 +#define VPMPC_RMCM_SHAPER_RAMA_REGION_2_3__VPMPC_RMCM_SHAPER_RAMA_EXP_REGION2_LUT_OFFSET__SHIFT 0x00000000 +#define VPMPC_RMCM_SHAPER_RAMA_REGION_2_3__VPMPC_RMCM_SHAPER_RAMA_EXP_REGION2_NUM_SEGMENTS__SHIFT 0x0000000c +#define VPMPC_RMCM_SHAPER_RAMA_REGION_2_3__VPMPC_RMCM_SHAPER_RAMA_EXP_REGION3_LUT_OFFSET__SHIFT 0x00000010 +#define VPMPC_RMCM_SHAPER_RAMA_REGION_2_3__VPMPC_RMCM_SHAPER_RAMA_EXP_REGION3_NUM_SEGMENTS__SHIFT 0x0000001c + +// reg: VPMPC_RMCM_SHAPER_RAMA_REGION_4_5 block: VPMPC_RMCM comp: amd.com/lib/vpmpc-vpep2gn/1.0 +#define VPMPC_RMCM_SHAPER_RAMA_REGION_4_5__VPMPC_RMCM_SHAPER_RAMA_EXP_REGION4_LUT_OFFSET__SHIFT 0x00000000 +#define VPMPC_RMCM_SHAPER_RAMA_REGION_4_5__VPMPC_RMCM_SHAPER_RAMA_EXP_REGION4_NUM_SEGMENTS__SHIFT 0x0000000c +#define VPMPC_RMCM_SHAPER_RAMA_REGION_4_5__VPMPC_RMCM_SHAPER_RAMA_EXP_REGION5_LUT_OFFSET__SHIFT 0x00000010 +#define VPMPC_RMCM_SHAPER_RAMA_REGION_4_5__VPMPC_RMCM_SHAPER_RAMA_EXP_REGION5_NUM_SEGMENTS__SHIFT 0x0000001c + +// reg: VPMPC_RMCM_SHAPER_RAMA_REGION_6_7 block: VPMPC_RMCM comp: amd.com/lib/vpmpc-vpep2gn/1.0 +#define VPMPC_RMCM_SHAPER_RAMA_REGION_6_7__VPMPC_RMCM_SHAPER_RAMA_EXP_REGION6_LUT_OFFSET__SHIFT 0x00000000 +#define VPMPC_RMCM_SHAPER_RAMA_REGION_6_7__VPMPC_RMCM_SHAPER_RAMA_EXP_REGION6_NUM_SEGMENTS__SHIFT 0x0000000c +#define VPMPC_RMCM_SHAPER_RAMA_REGION_6_7__VPMPC_RMCM_SHAPER_RAMA_EXP_REGION7_LUT_OFFSET__SHIFT 0x00000010 +#define VPMPC_RMCM_SHAPER_RAMA_REGION_6_7__VPMPC_RMCM_SHAPER_RAMA_EXP_REGION7_NUM_SEGMENTS__SHIFT 0x0000001c + +// reg: VPMPC_RMCM_SHAPER_RAMA_REGION_8_9 block: VPMPC_RMCM comp: amd.com/lib/vpmpc-vpep2gn/1.0 +#define VPMPC_RMCM_SHAPER_RAMA_REGION_8_9__VPMPC_RMCM_SHAPER_RAMA_EXP_REGION8_LUT_OFFSET__SHIFT 0x00000000 +#define VPMPC_RMCM_SHAPER_RAMA_REGION_8_9__VPMPC_RMCM_SHAPER_RAMA_EXP_REGION8_NUM_SEGMENTS__SHIFT 0x0000000c +#define VPMPC_RMCM_SHAPER_RAMA_REGION_8_9__VPMPC_RMCM_SHAPER_RAMA_EXP_REGION9_LUT_OFFSET__SHIFT 0x00000010 +#define VPMPC_RMCM_SHAPER_RAMA_REGION_8_9__VPMPC_RMCM_SHAPER_RAMA_EXP_REGION9_NUM_SEGMENTS__SHIFT 0x0000001c + +// reg: VPMPC_RMCM_SHAPER_RAMA_REGION_10_11 block: VPMPC_RMCM comp: amd.com/lib/vpmpc-vpep2gn/1.0 +#define VPMPC_RMCM_SHAPER_RAMA_REGION_10_11__VPMPC_RMCM_SHAPER_RAMA_EXP_REGION10_LUT_OFFSET__SHIFT 0x00000000 +#define VPMPC_RMCM_SHAPER_RAMA_REGION_10_11__VPMPC_RMCM_SHAPER_RAMA_EXP_REGION10_NUM_SEGMENTS__SHIFT 0x0000000c +#define VPMPC_RMCM_SHAPER_RAMA_REGION_10_11__VPMPC_RMCM_SHAPER_RAMA_EXP_REGION11_LUT_OFFSET__SHIFT 0x00000010 +#define VPMPC_RMCM_SHAPER_RAMA_REGION_10_11__VPMPC_RMCM_SHAPER_RAMA_EXP_REGION11_NUM_SEGMENTS__SHIFT 0x0000001c + +// reg: VPMPC_RMCM_SHAPER_RAMA_REGION_12_13 block: VPMPC_RMCM comp: amd.com/lib/vpmpc-vpep2gn/1.0 +#define VPMPC_RMCM_SHAPER_RAMA_REGION_12_13__VPMPC_RMCM_SHAPER_RAMA_EXP_REGION12_LUT_OFFSET__SHIFT 0x00000000 +#define VPMPC_RMCM_SHAPER_RAMA_REGION_12_13__VPMPC_RMCM_SHAPER_RAMA_EXP_REGION12_NUM_SEGMENTS__SHIFT 0x0000000c +#define VPMPC_RMCM_SHAPER_RAMA_REGION_12_13__VPMPC_RMCM_SHAPER_RAMA_EXP_REGION13_LUT_OFFSET__SHIFT 0x00000010 +#define VPMPC_RMCM_SHAPER_RAMA_REGION_12_13__VPMPC_RMCM_SHAPER_RAMA_EXP_REGION13_NUM_SEGMENTS__SHIFT 0x0000001c + +// reg: VPMPC_RMCM_SHAPER_RAMA_REGION_14_15 block: VPMPC_RMCM comp: amd.com/lib/vpmpc-vpep2gn/1.0 +#define VPMPC_RMCM_SHAPER_RAMA_REGION_14_15__VPMPC_RMCM_SHAPER_RAMA_EXP_REGION14_LUT_OFFSET__SHIFT 0x00000000 +#define VPMPC_RMCM_SHAPER_RAMA_REGION_14_15__VPMPC_RMCM_SHAPER_RAMA_EXP_REGION14_NUM_SEGMENTS__SHIFT 0x0000000c +#define VPMPC_RMCM_SHAPER_RAMA_REGION_14_15__VPMPC_RMCM_SHAPER_RAMA_EXP_REGION15_LUT_OFFSET__SHIFT 0x00000010 +#define VPMPC_RMCM_SHAPER_RAMA_REGION_14_15__VPMPC_RMCM_SHAPER_RAMA_EXP_REGION15_NUM_SEGMENTS__SHIFT 0x0000001c + +// reg: VPMPC_RMCM_SHAPER_RAMA_REGION_16_17 block: VPMPC_RMCM comp: amd.com/lib/vpmpc-vpep2gn/1.0 +#define VPMPC_RMCM_SHAPER_RAMA_REGION_16_17__VPMPC_RMCM_SHAPER_RAMA_EXP_REGION16_LUT_OFFSET__SHIFT 0x00000000 +#define VPMPC_RMCM_SHAPER_RAMA_REGION_16_17__VPMPC_RMCM_SHAPER_RAMA_EXP_REGION16_NUM_SEGMENTS__SHIFT 0x0000000c +#define VPMPC_RMCM_SHAPER_RAMA_REGION_16_17__VPMPC_RMCM_SHAPER_RAMA_EXP_REGION17_LUT_OFFSET__SHIFT 0x00000010 +#define VPMPC_RMCM_SHAPER_RAMA_REGION_16_17__VPMPC_RMCM_SHAPER_RAMA_EXP_REGION17_NUM_SEGMENTS__SHIFT 0x0000001c + +// reg: VPMPC_RMCM_SHAPER_RAMA_REGION_18_19 block: VPMPC_RMCM comp: amd.com/lib/vpmpc-vpep2gn/1.0 +#define VPMPC_RMCM_SHAPER_RAMA_REGION_18_19__VPMPC_RMCM_SHAPER_RAMA_EXP_REGION18_LUT_OFFSET__SHIFT 0x00000000 +#define VPMPC_RMCM_SHAPER_RAMA_REGION_18_19__VPMPC_RMCM_SHAPER_RAMA_EXP_REGION18_NUM_SEGMENTS__SHIFT 0x0000000c +#define VPMPC_RMCM_SHAPER_RAMA_REGION_18_19__VPMPC_RMCM_SHAPER_RAMA_EXP_REGION19_LUT_OFFSET__SHIFT 0x00000010 +#define VPMPC_RMCM_SHAPER_RAMA_REGION_18_19__VPMPC_RMCM_SHAPER_RAMA_EXP_REGION19_NUM_SEGMENTS__SHIFT 0x0000001c + +// reg: VPMPC_RMCM_SHAPER_RAMA_REGION_20_21 block: VPMPC_RMCM comp: amd.com/lib/vpmpc-vpep2gn/1.0 +#define VPMPC_RMCM_SHAPER_RAMA_REGION_20_21__VPMPC_RMCM_SHAPER_RAMA_EXP_REGION20_LUT_OFFSET__SHIFT 0x00000000 +#define VPMPC_RMCM_SHAPER_RAMA_REGION_20_21__VPMPC_RMCM_SHAPER_RAMA_EXP_REGION20_NUM_SEGMENTS__SHIFT 0x0000000c +#define VPMPC_RMCM_SHAPER_RAMA_REGION_20_21__VPMPC_RMCM_SHAPER_RAMA_EXP_REGION21_LUT_OFFSET__SHIFT 0x00000010 +#define VPMPC_RMCM_SHAPER_RAMA_REGION_20_21__VPMPC_RMCM_SHAPER_RAMA_EXP_REGION21_NUM_SEGMENTS__SHIFT 0x0000001c + +// reg: VPMPC_RMCM_SHAPER_RAMA_REGION_22_23 block: VPMPC_RMCM comp: amd.com/lib/vpmpc-vpep2gn/1.0 +#define VPMPC_RMCM_SHAPER_RAMA_REGION_22_23__VPMPC_RMCM_SHAPER_RAMA_EXP_REGION22_LUT_OFFSET__SHIFT 0x00000000 +#define VPMPC_RMCM_SHAPER_RAMA_REGION_22_23__VPMPC_RMCM_SHAPER_RAMA_EXP_REGION22_NUM_SEGMENTS__SHIFT 0x0000000c +#define VPMPC_RMCM_SHAPER_RAMA_REGION_22_23__VPMPC_RMCM_SHAPER_RAMA_EXP_REGION23_LUT_OFFSET__SHIFT 0x00000010 +#define VPMPC_RMCM_SHAPER_RAMA_REGION_22_23__VPMPC_RMCM_SHAPER_RAMA_EXP_REGION23_NUM_SEGMENTS__SHIFT 0x0000001c + +// reg: VPMPC_RMCM_SHAPER_RAMA_REGION_24_25 block: VPMPC_RMCM comp: amd.com/lib/vpmpc-vpep2gn/1.0 +#define VPMPC_RMCM_SHAPER_RAMA_REGION_24_25__VPMPC_RMCM_SHAPER_RAMA_EXP_REGION24_LUT_OFFSET__SHIFT 0x00000000 +#define VPMPC_RMCM_SHAPER_RAMA_REGION_24_25__VPMPC_RMCM_SHAPER_RAMA_EXP_REGION24_NUM_SEGMENTS__SHIFT 0x0000000c +#define VPMPC_RMCM_SHAPER_RAMA_REGION_24_25__VPMPC_RMCM_SHAPER_RAMA_EXP_REGION25_LUT_OFFSET__SHIFT 0x00000010 +#define VPMPC_RMCM_SHAPER_RAMA_REGION_24_25__VPMPC_RMCM_SHAPER_RAMA_EXP_REGION25_NUM_SEGMENTS__SHIFT 0x0000001c + +// reg: VPMPC_RMCM_SHAPER_RAMA_REGION_26_27 block: VPMPC_RMCM comp: amd.com/lib/vpmpc-vpep2gn/1.0 +#define VPMPC_RMCM_SHAPER_RAMA_REGION_26_27__VPMPC_RMCM_SHAPER_RAMA_EXP_REGION26_LUT_OFFSET__SHIFT 0x00000000 +#define VPMPC_RMCM_SHAPER_RAMA_REGION_26_27__VPMPC_RMCM_SHAPER_RAMA_EXP_REGION26_NUM_SEGMENTS__SHIFT 0x0000000c +#define VPMPC_RMCM_SHAPER_RAMA_REGION_26_27__VPMPC_RMCM_SHAPER_RAMA_EXP_REGION27_LUT_OFFSET__SHIFT 0x00000010 +#define VPMPC_RMCM_SHAPER_RAMA_REGION_26_27__VPMPC_RMCM_SHAPER_RAMA_EXP_REGION27_NUM_SEGMENTS__SHIFT 0x0000001c + +// reg: VPMPC_RMCM_SHAPER_RAMA_REGION_28_29 block: VPMPC_RMCM comp: amd.com/lib/vpmpc-vpep2gn/1.0 +#define VPMPC_RMCM_SHAPER_RAMA_REGION_28_29__VPMPC_RMCM_SHAPER_RAMA_EXP_REGION28_LUT_OFFSET__SHIFT 0x00000000 +#define VPMPC_RMCM_SHAPER_RAMA_REGION_28_29__VPMPC_RMCM_SHAPER_RAMA_EXP_REGION28_NUM_SEGMENTS__SHIFT 0x0000000c +#define VPMPC_RMCM_SHAPER_RAMA_REGION_28_29__VPMPC_RMCM_SHAPER_RAMA_EXP_REGION29_LUT_OFFSET__SHIFT 0x00000010 +#define VPMPC_RMCM_SHAPER_RAMA_REGION_28_29__VPMPC_RMCM_SHAPER_RAMA_EXP_REGION29_NUM_SEGMENTS__SHIFT 0x0000001c + +// reg: VPMPC_RMCM_SHAPER_RAMA_REGION_30_31 block: VPMPC_RMCM comp: amd.com/lib/vpmpc-vpep2gn/1.0 +#define VPMPC_RMCM_SHAPER_RAMA_REGION_30_31__VPMPC_RMCM_SHAPER_RAMA_EXP_REGION30_LUT_OFFSET__SHIFT 0x00000000 +#define VPMPC_RMCM_SHAPER_RAMA_REGION_30_31__VPMPC_RMCM_SHAPER_RAMA_EXP_REGION30_NUM_SEGMENTS__SHIFT 0x0000000c +#define VPMPC_RMCM_SHAPER_RAMA_REGION_30_31__VPMPC_RMCM_SHAPER_RAMA_EXP_REGION31_LUT_OFFSET__SHIFT 0x00000010 +#define VPMPC_RMCM_SHAPER_RAMA_REGION_30_31__VPMPC_RMCM_SHAPER_RAMA_EXP_REGION31_NUM_SEGMENTS__SHIFT 0x0000001c + +// reg: VPMPC_RMCM_SHAPER_RAMA_REGION_32_33 block: VPMPC_RMCM comp: amd.com/lib/vpmpc-vpep2gn/1.0 +#define VPMPC_RMCM_SHAPER_RAMA_REGION_32_33__VPMPC_RMCM_SHAPER_RAMA_EXP_REGION32_LUT_OFFSET__SHIFT 0x00000000 +#define VPMPC_RMCM_SHAPER_RAMA_REGION_32_33__VPMPC_RMCM_SHAPER_RAMA_EXP_REGION32_NUM_SEGMENTS__SHIFT 0x0000000c +#define VPMPC_RMCM_SHAPER_RAMA_REGION_32_33__VPMPC_RMCM_SHAPER_RAMA_EXP_REGION33_LUT_OFFSET__SHIFT 0x00000010 +#define VPMPC_RMCM_SHAPER_RAMA_REGION_32_33__VPMPC_RMCM_SHAPER_RAMA_EXP_REGION33_NUM_SEGMENTS__SHIFT 0x0000001c + +// reg: VPMPC_RMCM_3DLUT_MODE block: VPMPC_RMCM comp: amd.com/lib/vpmpc-vpep2gn/1.0 +#define VPMPC_RMCM_3DLUT_MODE__VPMPC_RMCM_3DLUT_MODE__SHIFT 0x00000000 +#define VPMPC_RMCM_3DLUT_MODE__VPMPC_RMCM_3DLUT_SIZE__SHIFT 0x00000004 +#define VPMPC_RMCM_3DLUT_MODE__VPMPC_RMCM_3DLUT_MODE_CURRENT__SHIFT 0x00000008 +#define VPMPC_RMCM_3DLUT_MODE__VPMPC_RMCM_3DLUT_SELECT_CURRENT__SHIFT 0x0000000a + +// reg: VPMPC_RMCM_3DLUT_INDEX block: VPMPC_RMCM comp: amd.com/lib/vpmpc-vpep2gn/1.0 +#define VPMPC_RMCM_3DLUT_INDEX__VPMPC_RMCM_3DLUT_INDEX__SHIFT 0x00000000 + +// reg: VPMPC_RMCM_3DLUT_DATA block: VPMPC_RMCM comp: amd.com/lib/vpmpc-vpep2gn/1.0 +#define VPMPC_RMCM_3DLUT_DATA__VPMPC_RMCM_3DLUT_DATA0__SHIFT 0x00000000 +#define VPMPC_RMCM_3DLUT_DATA__VPMPC_RMCM_3DLUT_DATA1__SHIFT 0x00000010 + +// reg: VPMPC_RMCM_3DLUT_DATA_30BIT block: VPMPC_RMCM comp: amd.com/lib/vpmpc-vpep2gn/1.0 +#define VPMPC_RMCM_3DLUT_DATA_30BIT__VPMPC_RMCM_3DLUT_DATA_30BIT__SHIFT 0x00000002 + +// reg: VPMPC_RMCM_3DLUT_READ_WRITE_CONTROL block: VPMPC_RMCM comp: amd.com/lib/vpmpc-vpep2gn/1.0 +#define VPMPC_RMCM_3DLUT_READ_WRITE_CONTROL__VPMPC_RMCM_3DLUT_WRITE_EN_MASK__SHIFT 0x00000000 +#define VPMPC_RMCM_3DLUT_READ_WRITE_CONTROL__VPMPC_RMCM_3DLUT_RAM_SEL__SHIFT 0x00000004 +#define VPMPC_RMCM_3DLUT_READ_WRITE_CONTROL__VPMPC_RMCM_3DLUT_30BIT_EN__SHIFT 0x00000008 +#define VPMPC_RMCM_3DLUT_READ_WRITE_CONTROL__VPMPC_RMCM_3DLUT_READ_SEL__SHIFT 0x00000010 + +// reg: VPMPC_RMCM_3DLUT_OUT_NORM_FACTOR block: VPMPC_RMCM comp: amd.com/lib/vpmpc-vpep2gn/1.0 +#define VPMPC_RMCM_3DLUT_OUT_NORM_FACTOR__VPMPC_RMCM_3DLUT_OUT_NORM_FACTOR__SHIFT 0x00000000 + +// reg: VPMPC_RMCM_3DLUT_OUT_OFFSET_R block: VPMPC_RMCM comp: amd.com/lib/vpmpc-vpep2gn/1.0 +#define VPMPC_RMCM_3DLUT_OUT_OFFSET_R__VPMPC_RMCM_3DLUT_OUT_OFFSET_R__SHIFT 0x00000000 +#define VPMPC_RMCM_3DLUT_OUT_OFFSET_R__VPMPC_RMCM_3DLUT_OUT_SCALE_R__SHIFT 0x00000010 + +// reg: VPMPC_RMCM_3DLUT_OUT_OFFSET_G block: VPMPC_RMCM comp: amd.com/lib/vpmpc-vpep2gn/1.0 +#define VPMPC_RMCM_3DLUT_OUT_OFFSET_G__VPMPC_RMCM_3DLUT_OUT_OFFSET_G__SHIFT 0x00000000 +#define VPMPC_RMCM_3DLUT_OUT_OFFSET_G__VPMPC_RMCM_3DLUT_OUT_SCALE_G__SHIFT 0x00000010 + +// reg: VPMPC_RMCM_3DLUT_OUT_OFFSET_B block: VPMPC_RMCM comp: amd.com/lib/vpmpc-vpep2gn/1.0 +#define VPMPC_RMCM_3DLUT_OUT_OFFSET_B__VPMPC_RMCM_3DLUT_OUT_OFFSET_B__SHIFT 0x00000000 +#define VPMPC_RMCM_3DLUT_OUT_OFFSET_B__VPMPC_RMCM_3DLUT_OUT_SCALE_B__SHIFT 0x00000010 + +// reg: VPMPC_RMCM_GAMUT_REMAP_COEF_FORMAT block: VPMPC_RMCM comp: amd.com/lib/vpmpc-vpep2gn/1.0 +#define VPMPC_RMCM_GAMUT_REMAP_COEF_FORMAT__VPMPC_RMCM_GAMUT_REMAP_COEF_FORMAT__SHIFT 0x00000000 + +// reg: VPMPC_RMCM_GAMUT_REMAP_MODE block: VPMPC_RMCM comp: amd.com/lib/vpmpc-vpep2gn/1.0 +#define VPMPC_RMCM_GAMUT_REMAP_MODE__VPMPC_RMCM_GAMUT_REMAP_MODE__SHIFT 0x00000000 +#define VPMPC_RMCM_GAMUT_REMAP_MODE__VPMPC_RMCM_GAMUT_REMAP_MODE_CURRENT__SHIFT 0x00000007 + +// reg: VPMPC_RMCM_GAMUT_REMAP_C11_C12_SETA block: VPMPC_RMCM comp: amd.com/lib/vpmpc-vpep2gn/1.0 +#define VPMPC_RMCM_GAMUT_REMAP_C11_C12_SETA__VPMPC_RMCM_GAMUT_REMAP_C11_SETA__SHIFT 0x00000000 +#define VPMPC_RMCM_GAMUT_REMAP_C11_C12_SETA__VPMPC_RMCM_GAMUT_REMAP_C12_SETA__SHIFT 0x00000010 + +// reg: VPMPC_RMCM_GAMUT_REMAP_C13_C14_SETA block: VPMPC_RMCM comp: amd.com/lib/vpmpc-vpep2gn/1.0 +#define VPMPC_RMCM_GAMUT_REMAP_C13_C14_SETA__VPMPC_RMCM_GAMUT_REMAP_C13_SETA__SHIFT 0x00000000 +#define VPMPC_RMCM_GAMUT_REMAP_C13_C14_SETA__VPMPC_RMCM_GAMUT_REMAP_C14_SETA__SHIFT 0x00000010 + +// reg: VPMPC_RMCM_GAMUT_REMAP_C21_C22_SETA block: VPMPC_RMCM comp: amd.com/lib/vpmpc-vpep2gn/1.0 +#define VPMPC_RMCM_GAMUT_REMAP_C21_C22_SETA__VPMPC_RMCM_GAMUT_REMAP_C21_SETA__SHIFT 0x00000000 +#define VPMPC_RMCM_GAMUT_REMAP_C21_C22_SETA__VPMPC_RMCM_GAMUT_REMAP_C22_SETA__SHIFT 0x00000010 + +// reg: VPMPC_RMCM_GAMUT_REMAP_C23_C24_SETA block: VPMPC_RMCM comp: amd.com/lib/vpmpc-vpep2gn/1.0 +#define VPMPC_RMCM_GAMUT_REMAP_C23_C24_SETA__VPMPC_RMCM_GAMUT_REMAP_C23_SETA__SHIFT 0x00000000 +#define VPMPC_RMCM_GAMUT_REMAP_C23_C24_SETA__VPMPC_RMCM_GAMUT_REMAP_C24_SETA__SHIFT 0x00000010 + +// reg: VPMPC_RMCM_GAMUT_REMAP_C31_C32_SETA block: VPMPC_RMCM comp: amd.com/lib/vpmpc-vpep2gn/1.0 +#define VPMPC_RMCM_GAMUT_REMAP_C31_C32_SETA__VPMPC_RMCM_GAMUT_REMAP_C31_SETA__SHIFT 0x00000000 +#define VPMPC_RMCM_GAMUT_REMAP_C31_C32_SETA__VPMPC_RMCM_GAMUT_REMAP_C32_SETA__SHIFT 0x00000010 + +// reg: VPMPC_RMCM_GAMUT_REMAP_C33_C34_SETA block: VPMPC_RMCM comp: amd.com/lib/vpmpc-vpep2gn/1.0 +#define VPMPC_RMCM_GAMUT_REMAP_C33_C34_SETA__VPMPC_RMCM_GAMUT_REMAP_C33_SETA__SHIFT 0x00000000 +#define VPMPC_RMCM_GAMUT_REMAP_C33_C34_SETA__VPMPC_RMCM_GAMUT_REMAP_C34_SETA__SHIFT 0x00000010 + +// reg: VPMPC_RMCM_MEM_PWR_CTRL block: VPMPC_RMCM comp: amd.com/lib/vpmpc-vpep2gn/1.0 +#define VPMPC_RMCM_MEM_PWR_CTRL__VPMPC_RMCM_SHAPER_MEM_PWR_FORCE__SHIFT 0x00000000 +#define VPMPC_RMCM_MEM_PWR_CTRL__VPMPC_RMCM_SHAPER_MEM_PWR_DIS__SHIFT 0x00000002 +#define VPMPC_RMCM_MEM_PWR_CTRL__VPMPC_RMCM_SHAPER_MEM_LOW_PWR_MODE__SHIFT 0x00000004 +#define VPMPC_RMCM_MEM_PWR_CTRL__VPMPC_RMCM_3DLUT_MEM_PWR_FORCE__SHIFT 0x00000008 +#define VPMPC_RMCM_MEM_PWR_CTRL__VPMPC_RMCM_3DLUT_MEM_PWR_DIS__SHIFT 0x0000000a +#define VPMPC_RMCM_MEM_PWR_CTRL__VPMPC_RMCM_3DLUT_MEM_LOW_PWR_MODE__SHIFT 0x0000000c +#define VPMPC_RMCM_MEM_PWR_CTRL__VPMPC_RMCM_SHAPER_MEM_PWR_STATE__SHIFT 0x00000018 +#define VPMPC_RMCM_MEM_PWR_CTRL__VPMPC_RMCM_3DLUT_MEM_PWR_STATE__SHIFT 0x0000001a + +// reg: VPMPC_RMCM_3DLUT_FAST_LOAD_SELECT block: VPMPC_RMCM comp: amd.com/lib/vpmpc-vpep2gn/1.0 +#define VPMPC_RMCM_3DLUT_FAST_LOAD_SELECT__VPMPC_RMCM_3DLUT_FL_SEL__SHIFT 0x00000000 + +// reg: VPMPC_RMCM_CNTL block: VPMPC_RMCM comp: amd.com/lib/vpmpc-vpep2gn/1.0 +#define VPMPC_RMCM_CNTL__VPMPC_RMCM_CNTL__SHIFT 0x00000000 + +// reg: VPFMT_CLAMP_COMPONENT_R block: VPFMT comp: amd.com/lib/vpopp-vpep2gn/1.0 +#define VPFMT_CLAMP_COMPONENT_R__VPFMT_CLAMP_LOWER_R__SHIFT 0x00000000 +#define VPFMT_CLAMP_COMPONENT_R__VPFMT_CLAMP_UPPER_R__SHIFT 0x00000010 + +// reg: VPFMT_CLAMP_COMPONENT_G block: VPFMT comp: amd.com/lib/vpopp-vpep2gn/1.0 +#define VPFMT_CLAMP_COMPONENT_G__VPFMT_CLAMP_LOWER_G__SHIFT 0x00000000 +#define VPFMT_CLAMP_COMPONENT_G__VPFMT_CLAMP_UPPER_G__SHIFT 0x00000010 + +// reg: VPFMT_CLAMP_COMPONENT_B block: VPFMT comp: amd.com/lib/vpopp-vpep2gn/1.0 +#define VPFMT_CLAMP_COMPONENT_B__VPFMT_CLAMP_LOWER_B__SHIFT 0x00000000 +#define VPFMT_CLAMP_COMPONENT_B__VPFMT_CLAMP_UPPER_B__SHIFT 0x00000010 + +// reg: VPFMT_DYNAMIC_EXP_CNTL block: VPFMT comp: amd.com/lib/vpopp-vpep2gn/1.0 +#define VPFMT_DYNAMIC_EXP_CNTL__VPFMT_DYNAMIC_EXP_EN__SHIFT 0x00000000 +#define VPFMT_DYNAMIC_EXP_CNTL__VPFMT_DYNAMIC_EXP_MODE__SHIFT 0x00000004 + +// reg: VPFMT_CONTROL block: VPFMT comp: amd.com/lib/vpopp-vpep2gn/1.0 +#define VPFMT_CONTROL__VPFMT_PIXEL_ENCODING__SHIFT 0x00000000 +#define VPFMT_CONTROL__VPFMT_CBCR_BIT_REDUCTION_BYPASS__SHIFT 0x00000004 +#define VPFMT_CONTROL__VPFMT_SPATIAL_DITHER_FRAME_COUNTER_MAX__SHIFT 0x00000008 +#define VPFMT_CONTROL__VPFMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP__SHIFT 0x0000000c +#define VPFMT_CONTROL__VPFMT_SUBSAMPLE_HTAPS__SHIFT 0x00000010 +#define VPFMT_CONTROL__VPFMT_SUBSAMPLE_LEFT_EDGE__SHIFT 0x00000012 +#define VPFMT_CONTROL__VPFMT_SUBSAMPLE_RIGHT_EDGE__SHIFT 0x00000013 +#define VPFMT_CONTROL__VPFMT_SUBSAMPLE_VTAPS__SHIFT 0x00000014 +#define VPFMT_CONTROL__VPFMT_SUBSAMPLE_TOP_EDGE__SHIFT 0x00000016 +#define VPFMT_CONTROL__VPFMT_SUBSAMPLE_BOTTOM_EDGE__SHIFT 0x00000017 +#define VPFMT_CONTROL__VPFMT_DOUBLE_BUFFER_REG_UPDATE_PENDING__SHIFT 0x00000018 + +// reg: VPFMT_BIT_DEPTH_CONTROL block: VPFMT comp: amd.com/lib/vpopp-vpep2gn/1.0 +#define VPFMT_BIT_DEPTH_CONTROL__VPFMT_TRUNCATE_EN__SHIFT 0x00000000 +#define VPFMT_BIT_DEPTH_CONTROL__VPFMT_TRUNCATE_MODE__SHIFT 0x00000001 +#define VPFMT_BIT_DEPTH_CONTROL__VPFMT_TRUNCATE_DEPTH__SHIFT 0x00000004 +#define VPFMT_BIT_DEPTH_CONTROL__VPFMT_SPATIAL_DITHER_EN__SHIFT 0x00000008 +#define VPFMT_BIT_DEPTH_CONTROL__VPFMT_SPATIAL_DITHER_MODE__SHIFT 0x00000009 +#define VPFMT_BIT_DEPTH_CONTROL__VPFMT_SPATIAL_DITHER_DEPTH__SHIFT 0x0000000b +#define VPFMT_BIT_DEPTH_CONTROL__VPFMT_FRAME_RANDOM_ENABLE__SHIFT 0x0000000d +#define VPFMT_BIT_DEPTH_CONTROL__VPFMT_RGB_RANDOM_ENABLE__SHIFT 0x0000000e +#define VPFMT_BIT_DEPTH_CONTROL__VPFMT_HIGHPASS_RANDOM_ENABLE__SHIFT 0x0000000f + +// reg: VPFMT_DITHER_RAND_R_SEED block: VPFMT comp: amd.com/lib/vpopp-vpep2gn/1.0 +#define VPFMT_DITHER_RAND_R_SEED__VPFMT_RAND_R_SEED__SHIFT 0x00000000 +#define VPFMT_DITHER_RAND_R_SEED__VPFMT_OFFSET_R_CR__SHIFT 0x00000010 + +// reg: VPFMT_DITHER_RAND_G_SEED block: VPFMT comp: amd.com/lib/vpopp-vpep2gn/1.0 +#define VPFMT_DITHER_RAND_G_SEED__VPFMT_RAND_G_SEED__SHIFT 0x00000000 +#define VPFMT_DITHER_RAND_G_SEED__VPFMT_OFFSET_G_Y__SHIFT 0x00000010 + +// reg: VPFMT_DITHER_RAND_B_SEED block: VPFMT comp: amd.com/lib/vpopp-vpep2gn/1.0 +#define VPFMT_DITHER_RAND_B_SEED__VPFMT_RAND_B_SEED__SHIFT 0x00000000 +#define VPFMT_DITHER_RAND_B_SEED__VPFMT_OFFSET_B_CB__SHIFT 0x00000010 + +// reg: VPFMT_CLAMP_CNTL block: VPFMT comp: amd.com/lib/vpopp-vpep2gn/1.0 +#define VPFMT_CLAMP_CNTL__VPFMT_CLAMP_DATA_EN__SHIFT 0x00000000 +#define VPFMT_CLAMP_CNTL__VPFMT_CLAMP_COLOR_FORMAT__SHIFT 0x00000010 + +// reg: VPFMT_SUBSAMPLER_MEMORY_CONTROL block: VPFMT comp: amd.com/lib/vpopp-vpep2gn/1.0 +#define VPFMT_SUBSAMPLER_MEMORY_CONTROL__VPFMT_SUBSAMPLER_MEM_PWR_FORCE__SHIFT 0x00000000 +#define VPFMT_SUBSAMPLER_MEMORY_CONTROL__VPFMT_SUBSAMPLER_MEM_PWR_DIS__SHIFT 0x00000004 +#define VPFMT_SUBSAMPLER_MEMORY_CONTROL__VPFMT_SUBSAMPLER_MEM_PWR_STATE__SHIFT 0x00000008 +#define VPFMT_SUBSAMPLER_MEMORY_CONTROL__VPFMT_DEFAULT_MEM_LOW_POWER_STATE__SHIFT 0x0000000c + +// reg: VPOPP_PIPE_CONTROL block: VPOPP_PIPE comp: amd.com/lib/vpopp-vpep2gn/1.0 +#define VPOPP_PIPE_CONTROL__VPOPP_PIPE_CLOCK_ON__SHIFT 0x00000001 +#define VPOPP_PIPE_CONTROL__VPOPP_PIPE_DIGITAL_BYPASS_EN__SHIFT 0x00000004 +#define VPOPP_PIPE_CONTROL__VPOPP_PIPE_ALPHA_SEL__SHIFT 0x00000005 +#define VPOPP_PIPE_CONTROL__VPOPP_PIPE_ALPHA__SHIFT 0x00000010 + +// reg: VPOPP_PIPE_OUTBG_EXT1 block: VPOPP_PIPE comp: amd.com/lib/vpopp-vpep2gn/1.0 +#define VPOPP_PIPE_OUTBG_EXT1__OUTBG_EXT_TOP__SHIFT 0x00000000 +#define VPOPP_PIPE_OUTBG_EXT1__OUTBG_EXT_BOT__SHIFT 0x0000000e + +// reg: VPOPP_PIPE_OUTBG_EXT2 block: VPOPP_PIPE comp: amd.com/lib/vpopp-vpep2gn/1.0 +#define VPOPP_PIPE_OUTBG_EXT2__OUTBG_EXT_LEFT__SHIFT 0x00000000 +#define VPOPP_PIPE_OUTBG_EXT2__OUTBG_EXT_RIGHT__SHIFT 0x0000000b + +// reg: VPOPP_PIPE_OUTBG_COL1 block: VPOPP_PIPE comp: amd.com/lib/vpopp-vpep2gn/1.0 +#define VPOPP_PIPE_OUTBG_COL1__OUTBG_R_CR__SHIFT 0x00000000 +#define VPOPP_PIPE_OUTBG_COL1__OUTBG_B_CB__SHIFT 0x00000010 + +// reg: VPOPP_PIPE_OUTBG_COL2 block: VPOPP_PIPE comp: amd.com/lib/vpopp-vpep2gn/1.0 +#define VPOPP_PIPE_OUTBG_COL2__OUTBG_Y__SHIFT 0x00000000 + +// reg: VPOPP_TOP_CLK_CONTROL block: VPOPP_TOP comp: amd.com/lib/vpopp-vpep2gn/1.0 +#define VPOPP_TOP_CLK_CONTROL__VPOPP_VPECLK_R_GATE_DIS__SHIFT 0x00000000 +#define VPOPP_TOP_CLK_CONTROL__VPOPP_VPECLK_G_GATE_DIS__SHIFT 0x00000001 + +// reg: VPOPP_CRC_CONTROL block: VPOPP_TOP comp: amd.com/lib/vpopp-vpep2gn/1.0 +#define VPOPP_CRC_CONTROL__VPOPP_CRC_EN__SHIFT 0x00000000 +#define VPOPP_CRC_CONTROL__VPOPP_CRC_CONT_EN__SHIFT 0x00000001 +#define VPOPP_CRC_CONTROL__VPOPP_CRC_PIXEL_SELECT__SHIFT 0x00000002 +#define VPOPP_CRC_CONTROL__VPOPP_CRC_SOURCE_SELECT__SHIFT 0x00000004 +#define VPOPP_CRC_CONTROL__VPOPP_CRC_PIPE_SELECT__SHIFT 0x00000006 +#define VPOPP_CRC_CONTROL__VPOPP_CRC_MASK__SHIFT 0x00000008 +#define VPOPP_CRC_CONTROL__VPOPP_CRC_ONE_SHOT_PENDING__SHIFT 0x0000001f + +// reg: VPOPP_CRC_RESULT_RG block: VPOPP_TOP comp: amd.com/lib/vpopp-vpep2gn/1.0 +#define VPOPP_CRC_RESULT_RG__VPOPP_CRC_RESULT_R__SHIFT 0x00000000 +#define VPOPP_CRC_RESULT_RG__VPOPP_CRC_RESULT_G__SHIFT 0x00000010 + +// reg: VPOPP_CRC_RESULT_BC block: VPOPP_TOP comp: amd.com/lib/vpopp-vpep2gn/1.0 +#define VPOPP_CRC_RESULT_BC__VPOPP_CRC_RESULT_B__SHIFT 0x00000000 +#define VPOPP_CRC_RESULT_BC__VPOPP_CRC_RESULT_C__SHIFT 0x00000010 + +// reg: VPOPP_FROD_CONTROL block: VPOPP_TOP comp: amd.com/lib/vpopp-vpep2gn/1.0 +#define VPOPP_FROD_CONTROL__FROD_EN__SHIFT 0x00000000 + +// reg: VPOPP_FROD_MEM_PWR_CONTROL block: VPOPP_TOP comp: amd.com/lib/vpopp-vpep2gn/1.0 +#define VPOPP_FROD_MEM_PWR_CONTROL__FROD_MEM_PWR_FORCE__SHIFT 0x00000000 +#define VPOPP_FROD_MEM_PWR_CONTROL__FROD_MEM_PWR_DIS__SHIFT 0x00000004 +#define VPOPP_FROD_MEM_PWR_CONTROL__FROD_MEM_PWR_STATE__SHIFT 0x00000008 +#define VPOPP_FROD_MEM_PWR_CONTROL__FROD_MEM_DEFAULT_LOW_PWR_STATE__SHIFT 0x0000000c + +#endif diff --git a/src/amd/vpelib/src/chip/vpe22/inc/vpe22_resource.h b/src/amd/vpelib/src/chip/vpe22/inc/vpe22_resource.h new file mode 100644 index 00000000000..7161b378cdf --- /dev/null +++ b/src/amd/vpelib/src/chip/vpe22/inc/vpe22_resource.h @@ -0,0 +1,48 @@ +/* Copyright 2025 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: AMD + * + */ +#pragma once + +#include "resource.h" + +#ifdef __cplusplus +extern "C" { +#endif + +enum vpe_status vpe22_construct_resource(struct vpe_priv *vpe_priv, struct resource *res); + +const struct vpe_caps *vpe22_get_capability(void); + +struct cdc_fe *vpe22_cdc_fe_create(struct vpe_priv *vpe_priv, int inst); +struct cdc_be *vpe22_cdc_be_create(struct vpe_priv *vpe_priv, int inst); +struct dpp *vpe22_dpp_create(struct vpe_priv *vpe_priv, int inst); +struct opp *vpe22_opp_create(struct vpe_priv *vpe_priv, int inst); +struct mpc *vpe22_mpc_create(struct vpe_priv *vpe_priv, int inst); + +void vpe22_setup_check_funcs(struct vpe_check_support_funcs *funcs); + +bool vpe22_check_input_format(enum vpe_surface_pixel_format format); + +#ifdef __cplusplus +} +#endif diff --git a/src/amd/vpelib/src/chip/vpe22/vpe22_resource.c b/src/amd/vpelib/src/chip/vpe22/vpe22_resource.c new file mode 100644 index 00000000000..b1a5813e0c8 --- /dev/null +++ b/src/amd/vpelib/src/chip/vpe22/vpe22_resource.c @@ -0,0 +1,551 @@ +/* Copyright 2025 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: AMD + * + */ +#include +#include "vpe_priv.h" +#include "common.h" +#include "vpe20_cmd_builder.h" +#include "vpe20_vpe_desc_writer.h" +#include "vpe20_plane_desc_writer.h" +#include "vpe20_config_writer.h" +#include "vpe20_resource.h" +#include "vpe22_resource.h" +#include "vpe10_resource.h" +#include "vpe10_vpec.h" +#include "vpe10_cdc_fe.h" +#include "vpe10_cdc_be.h" +#include "vpe20_cdc_fe.h" +#include "vpe20_cdc_be.h" +#include "vpe10_dpp.h" +#include "vpe20_dpp.h" +#include "vpe10_mpc.h" +#include "vpe20_mpc.h" +#include "vpe10_opp.h" +#include "vpe20_opp.h" +#include "vpe10_background.h" +#include "vpe22/inc/asic/chip_offset.h" +#include "vpe22/inc/asic/chip_mask.h" +#include "vpe22/inc/asic/chip_shift.h" +#include "vpe22/inc/asic/chip_default.h" +#include "custom_fp16.h" +#include "custom_float.h" +#include "background.h" +#include "vpe_visual_confirm.h" +#include "vpe_spl_translation.h" +#include "SPL/dc_spl.h" + +#define LUT_NUM_ENTRIES (17 * 17 * 17) +#define LUT_ENTRY_SIZE (2) +#define LUT_NUM_COMPONENT (3) +#define LUT_BUFFER_SIZE (LUT_NUM_ENTRIES * LUT_ENTRY_SIZE * LUT_NUM_COMPONENT) + +#define LUT_FL_SIZE_17X17X17 (4916) +#define LUT_FL_SIZE_33X33X33 (35940) + +#define BYTES_PER_ENTRY (4) +#define SHAPER_LUT_CHANNELS (3) +#define SHAPER_LUT_DATA_POINTS_PER_CHANNEL (256) +#define SHAPER_LUT_CONFIG_ENTRIES (28) +#define SHAPER_LUT_DMA_DATA_SIZE \ + (SHAPER_LUT_DATA_POINTS_PER_CHANNEL * SHAPER_LUT_CHANNELS * BYTES_PER_ENTRY) +#define SHAPER_LUT_DMA_CONFIG_SIZE \ + (SHAPER_LUT_CONFIG_ENTRIES * (BYTES_PER_ENTRY + SHAPER_LUT_DMA_CONFIG_PADDING)) +#define SHAPER_LUT_DMA_DATA_ALIGNMENT (64) +#define SHAPER_LUT_DMA_CONFIG_ALIGNMENT (64) +#define SHAPER_LUT_DMA_CONFIG_PADDING (60) +#define LUT_3D_DMA_ALIGNMENT (256) + +#define VPE_DESTINATION_AS_INPUT_STREAM_INDEX 0xff + +// set field/register/bitfield name +#define SFRB(field_name, reg_name, post_fix) .field_name = reg_name##__##field_name##post_fix + +// #ifdef SOC_BRINGUP + +#define SRIDFVL(reg_name, block, id) \ + .reg_name = {mm##block##id##_##reg_name, mm##block##id##_##reg_name##_##DEFAULT, \ + mm##block##id##_##reg_name##_##DEFAULT, false} + +#define SRIDFVL1(reg_name) \ + .reg_name = {mm##reg_name, mm##reg_name##_##DEFAULT, mm##reg_name##_##DEFAULT, false} + +#define SRIDFVL2(reg_name, block, id) \ + .block##_##reg_name = {mm##block##id##_##reg_name, mm##block##id##_##reg_name##_##DEFAULT, \ + mm##block##id##_##reg_name##_##DEFAULT, false} + +#define SRIDFVL3(reg_name, block, id) \ + .block##_##reg_name = {mm##block##_##reg_name, mm##block##_##reg_name##_##DEFAULT, \ + mm##block##_##reg_name##_##DEFAULT, false} + +#define SRIDFVL_CDC(reg_name, block, id) \ + .block##0##_##reg_name = {mm##block##id##_##reg_name, mm##block##id##_##reg_name##_##DEFAULT, \ + mm##block##id##_##reg_name##_##DEFAULT, false} + +/***************** CDC FE registers ****************/ +#define cdc_fe_regs(id) [id] = {CDC_FE_REG_LIST_VPE20(id)} + +static struct vpe20_cdc_fe_registers cdc_fe_regs[] = {cdc_fe_regs(0), cdc_fe_regs(1)}; + +static const struct vpe20_cdc_fe_shift cdc_fe_shift = {CDC_FE_FIELD_LIST_VPE20(__SHIFT)}; + +static const struct vpe20_cdc_fe_mask cdc_fe_mask = {CDC_FE_FIELD_LIST_VPE20(_MASK)}; + +/***************** CDC BE registers ****************/ +#define cdc_be_regs(id) [id] = {CDC_BE_REG_LIST_VPE20(id)} +static struct vpe20_cdc_be_registers cdc_be_regs[] = { + cdc_be_regs(0), cdc_be_regs(1), cdc_be_regs(2), cdc_be_regs(3)}; + +static const struct vpe20_cdc_be_shift cdc_be_shift = {CDC_BE_FIELD_LIST_VPE20(__SHIFT)}; + +static const struct vpe20_cdc_be_mask cdc_be_mask = {CDC_BE_FIELD_LIST_VPE20(_MASK)}; + +/***************** DPP registers ****************/ +#define dpp_regs(id) [id] = {DPP_REG_LIST_VPE20(id)} + +static struct vpe20_dpp_registers dpp_regs[] = {dpp_regs(0), dpp_regs(1)}; + +static const struct vpe20_dpp_shift dpp_shift = {DPP_FIELD_LIST_VPE20(__SHIFT)}; + +static const struct vpe20_dpp_mask dpp_mask = {DPP_FIELD_LIST_VPE20(_MASK)}; + +/***************** OPP registers ****************/ +#define opp_regs(id) [id] = {OPP_REG_LIST_VPE20(id)} + +static struct vpe20_opp_registers opp_regs[] = {opp_regs(0), opp_regs(1)}; + +static const struct vpe20_opp_shift opp_shift = {OPP_FIELD_LIST_VPE20(__SHIFT)}; + +static const struct vpe20_opp_mask opp_mask = {OPP_FIELD_LIST_VPE20(_MASK)}; + +/***************** MPC registers ****************/ +#define mpc_regs(id) [id] = {MPC_REG_LIST_VPE20(id)} + +static struct vpe20_mpc_registers mpc_regs[] = {mpc_regs(0), mpc_regs(1)}; + +static const struct vpe20_mpc_shift mpc_shift = {MPC_FIELD_LIST_VPE20(__SHIFT)}; + +static const struct vpe20_mpc_mask mpc_mask = {MPC_FIELD_LIST_VPE20(_MASK)}; + +static struct vpe_caps + caps = + { + .max_input_size = + { + .width = 16384, + .height = 16384, + }, + .max_output_size = + { + .width = 16384, + .height = 16384, + }, + .min_input_size = + { + .width = 1, + .height = 1, + }, + .min_output_size = + { + .width = 1, + .height = 1, + }, + .lut_size = LUT_BUFFER_SIZE, + .rotation_support = 1, + .h_mirror_support = 1, + .v_mirror_support = 1, + .is_apu = 1, + .bg_color_check_support = 0, + + .prefer_external_scaler_coef = 0, + + .resource_caps = + { + .num_dpp = 2, + .num_opp = 2, + .num_mpc_3dlut = 1, + .num_queue = 8, + .num_cdc_be = 4, + }, + .color_caps = {.dpp = + { + .pre_csc = 1, + .luma_key = 1, + .color_key = 1, + .dgam_ram = 0, + .post_csc = 1, + .gamma_corr = 1, + .hw_3dlut = 1, + .ogam_ram = 1, /**< programmable gam in output -> gamma_corr */ + .ocsc = 0, + .dgam_rom_caps = + { + .srgb = 1, + .bt2020 = 1, + .gamma2_2 = 1, + .pq = 1, + .hlg = 1, + }, + }, + .mpc = + { + .gamut_remap = 1, + .ogam_ram = 1, + .ocsc = 1, + .shared_3d_lut = 1, + .global_alpha = 1, + .top_bottom_blending = 1, + .dma_3d_lut = 1, + .yuv_linear_blend = 0, + .lut_dim_caps = + { + .dim_9 = 0, + .dim_17 = 1, + .dim_33 = 1, + }, + .lut_caps = + { + .lut_shaper_caps = + { + .dma_data = 0, + .dma_config = 0, + .non_monotonic = 0, + .data_alignment = SHAPER_LUT_DMA_DATA_ALIGNMENT, + .config_alignment = SHAPER_LUT_DMA_CONFIG_ALIGNMENT, + .config_padding = SHAPER_LUT_DMA_CONFIG_PADDING, + .data_size = SHAPER_LUT_DMA_DATA_SIZE, + .config_size = SHAPER_LUT_DMA_CONFIG_SIZE, + .data_pts_per_channel = SHAPER_LUT_DATA_POINTS_PER_CHANNEL, + }, + .lut_3dlut_caps = + { + .data_dim_9 = 0, + .data_dim_17 = 1, + .data_dim_33 = 1, + .dma_dim_9 = 0, + .dma_dim_17 = 0, + .dma_dim_33 = 1, + .alignment = LUT_3D_DMA_ALIGNMENT, + }, + .lut_3d_compound = 0, + }, + }}, + .plane_caps = + { + .per_pixel_alpha = 1, + .input_pixel_format_support = + { + .argb_packed_32b = 1, + .nv12 = 1, + .fp16 = 1, + .p010 = 1, /**< planar 4:2:0 10-bit */ + .p016 = 1, /**< planar 4:2:0 16-bit */ + .ayuv = 1, /**< packed 4:4:4 */ + .yuy2 = 1, /**< packed 4:2:2 */ + .y210 = 1, /**< packed 4:2:2 10-bit */ + .y216 = 1, /**< packed 4:2:2 16-bit */ + .p210 = 1, /**< planar 4:2:2 10-bit */ + .p216 = 1, /**< planar 4:2:2 16-bit */ + .rgb8_planar = 1, /**< planar RGB 8-bit */ + .rgb16_planar = 1, /**< planar RGB 16-bit */ + .yuv8_planar = 1, /**< planar YUV 16-bit */ + .yuv16_planar = 1, /**< planar YUV 16-bit */ + .fp16_planar = 1, /**< planar RGB 8-bit */ + .rgbe = 1, /**< shared exponent R9G9B9E5 */ + .rgb111110_fix = 0, /**< fixed R11G11B10 */ + .rgb111110_float = 0, /**< float R11G11B10 */ + }, + .output_pixel_format_support = + { + .argb_packed_32b = 1, + .nv12 = 1, + .fp16 = 1, + .p010 = 1, /**< planar 4:2:0 10-bit */ + .p016 = 1, /**< planar 4:2:0 16-bit */ + .ayuv = 1, /**< packed 4:4:4 */ + .yuy2 = 1, /**< packed 4:2:2 */ + .y210 = 1, /**< packed 4:2:2 10-bit */ + .y216 = 1, /**< packed 4:2:2 16-bit */ + .p210 = 1, /**< planar 4:2:2 10-bit */ + .p216 = 1, /**< planar 4:2:2 16-bit */ + .rgb8_planar = 1, /**< planar RGB 8-bit */ + .rgb16_planar = 1, /**< planar RGB 16-bit */ + .yuv8_planar = 1, /**< planar YUV 16-bit */ + .yuv16_planar = 1, /**< planar YUV 16-bit */ + .fp16_planar = 1, /**< planar RGB 8-bit */ + .rgbe = 0, /**< shared exponent R9G9B9E5 */ + .rgb111110_fix = 0, /**< fixed R11G11B10 */ + .rgb111110_float = 0, /**< float R11G11B10 */ + }, + .max_upscale_factor = 64000, + + // limit to 4:1 downscaling ratio: 1000/4 = 250 + .max_downscale_factor = 250, + + .pitch_alignment = 256, + .addr_alignment = 256, + .max_viewport_width = 1024, + .max_viewport_width_64bpp = 540, + }, + .isharp_caps = + { + .support = true, + .range = + { + .min = 0, + .max = 10, + .step = 1, + }, + }, + .easf_support = 1, + .input_dcc_support = 1, + .input_internal_dcc = 1, + .output_dcc_support = 0, + .output_internal_dcc = 0, + .histogram_support = 1, + .frod_support = 1, + .alpha_blending_support = 1, + .alpha_fill_caps = + { + .opaque = 1, + .bg_color = 1, + .destination = 0, + .source_stream = 0, + }, +}; + +struct cdc_fe *vpe22_cdc_fe_create(struct vpe_priv *vpe_priv, int inst) +{ + struct vpe20_cdc_fe *vpe_cdc_fe = vpe_zalloc(sizeof(struct vpe20_cdc_fe)); + + if (!vpe_cdc_fe) + return NULL; + + vpe20_construct_cdc_fe(vpe_priv, &vpe_cdc_fe->base); + + vpe_cdc_fe->base.inst = inst; + vpe_cdc_fe->regs = &cdc_fe_regs[inst]; + vpe_cdc_fe->mask = &cdc_fe_mask; + vpe_cdc_fe->shift = &cdc_fe_shift; + + return &vpe_cdc_fe->base; +} + +struct cdc_be *vpe22_cdc_be_create(struct vpe_priv *vpe_priv, int inst) +{ + struct vpe20_cdc_be *vpe_cdc_be = vpe_zalloc(sizeof(struct vpe20_cdc_be)); + + if (!vpe_cdc_be) + return NULL; + + vpe20_construct_cdc_be(vpe_priv, &vpe_cdc_be->base); + + vpe_cdc_be->base.inst = inst; + vpe_cdc_be->regs = &cdc_be_regs[inst]; + vpe_cdc_be->mask = &cdc_be_mask; + vpe_cdc_be->shift = &cdc_be_shift; + + return &vpe_cdc_be->base; +} + +struct dpp *vpe22_dpp_create(struct vpe_priv *vpe_priv, int inst) +{ + struct vpe20_dpp *vpe_dpp = vpe_zalloc(sizeof(struct vpe20_dpp)); + + if (!vpe_dpp) + return NULL; + + vpe20_construct_dpp(vpe_priv, &vpe_dpp->base); + + vpe_dpp->base.inst = inst; + vpe_dpp->regs = &dpp_regs[inst]; + vpe_dpp->mask = &dpp_mask; + vpe_dpp->shift = &dpp_shift; + + return &vpe_dpp->base; +} + +struct opp *vpe22_opp_create(struct vpe_priv *vpe_priv, int inst) +{ + struct vpe20_opp *vpe_opp = vpe_zalloc(sizeof(struct vpe20_opp)); + + if (!vpe_opp) + return NULL; + + vpe20_construct_opp(vpe_priv, &vpe_opp->base); + + vpe_opp->base.inst = inst; + vpe_opp->regs = &opp_regs[inst]; + vpe_opp->mask = &opp_mask; + vpe_opp->shift = &opp_shift; + + return &vpe_opp->base; +} + +struct mpc *vpe22_mpc_create(struct vpe_priv *vpe_priv, int inst) +{ + struct vpe20_mpc *vpe_mpc = vpe_zalloc(sizeof(struct vpe20_mpc)); + + if (!vpe_mpc) + return NULL; + + vpe20_construct_mpc(vpe_priv, &vpe_mpc->base); + + vpe_mpc->base.inst = inst; + vpe_mpc->regs = &mpc_regs[inst]; + vpe_mpc->mask = &mpc_mask; + vpe_mpc->shift = &mpc_shift; + + return &vpe_mpc->base; +} + +enum vpe_status vpe22_construct_resource(struct vpe_priv *vpe_priv, struct resource *res) +{ + struct vpe *vpe = &vpe_priv->pub; + uint32_t i; + + vpe->caps = ∩︀ + + vpe10_construct_vpec(vpe_priv, &res->vpec); + + for (i = 0; i < vpe->caps->resource_caps.num_dpp; i++) { // num pipes = num dpp = num_mpc + res->cdc_fe[i] = vpe22_cdc_fe_create(vpe_priv, i); + if (res->cdc_fe[i] == NULL) + goto err; + + res->dpp[i] = vpe22_dpp_create(vpe_priv, i); + if (res->dpp[i] == NULL) + goto err; + + res->mpc[i] = vpe22_mpc_create(vpe_priv, i); + if (res->mpc[i] == NULL) + goto err; + } + + for (i = 0; i < vpe->caps->resource_caps.num_cdc_be; i++) { + res->cdc_be[i] = vpe22_cdc_be_create(vpe_priv, i); + if (res->cdc_be[i] == NULL) + goto err; + } + + for (i = 0; i < vpe->caps->resource_caps.num_opp; i++) { // num opp = num dpp + res->opp[i] = vpe22_opp_create(vpe_priv, i); + if (res->opp[i] == NULL) + goto err; + } + + vpe20_construct_cmd_builder(vpe_priv, &res->cmd_builder); + vpe20_construct_vpe_desc_writer(&vpe_priv->vpe_desc_writer); + vpe20_construct_plane_desc_writer(&vpe_priv->plane_desc_writer); + vpe20_config_writer_init(&vpe_priv->config_writer); + + vpe_priv->num_pipe = 2; + + res->internal_hdr_normalization = 1; + + // Many of the below will need VPE20 versions. + res->check_h_mirror_support = vpe20_check_h_mirror_support; + res->calculate_segments = vpe20_calculate_segments; + res->get_max_seg_width = vpe20_get_max_seg_width; + res->set_num_segments = vpe20_set_num_segments; + res->split_bg_gap = vpe10_split_bg_gap; + res->calculate_dst_viewport_and_active = vpe20_calculate_dst_viewport_and_active; + res->get_bg_stream_idx = vpe20_get_bg_stream_idx; + res->find_bg_gaps = vpe_find_bg_gaps; + res->create_bg_segments = vpe20_create_bg_segments; + res->populate_cmd_info = vpe20_populate_cmd_info; + res->program_frontend = vpe20_program_frontend; + res->program_backend = vpe20_program_backend; + res->get_bufs_req = vpe20_get_bufs_req; + res->check_bg_color_support = vpe20_check_bg_color_support; + res->bg_color_convert = vpe20_bg_color_convert; + res->check_mirror_rotation_support = vpe20_check_mirror_rotation_support; + res->update_blnd_gamma = vpe20_update_blnd_gamma; + res->update_output_gamma = vpe20_update_output_gamma; + res->validate_cached_param = vpe20_validate_cached_param; + res->fill_alpha_through_luma_cmd_info = vpe20_fill_alpha_through_luma_cmd_info; + res->fill_non_performance_mode_cmd_info = vpe20_fill_non_performance_mode_cmd_info; + res->fill_performance_mode_cmd_info = vpe20_fill_performance_mode_cmd_info; + res->fill_blending_cmd_info = vpe20_fill_blending_cmd_info; + res->get_num_pipes_available = vpe20_get_num_pipes_available; + res->set_frod_output_viewport = vpe20_set_frod_output_viewport; + res->check_alpha_fill_support = vpe10_check_alpha_fill_support; + res->reset_pipes = vpe20_reset_pipes; + res->populate_frod_param = vpe20_populate_frod_param; + res->set_lls_pref = vpe20_set_lls_pref; + res->program_fastload = vpe20_program_3dlut_fl; + res->calculate_shaper = vpe10_calculate_shaper; + res->check_lut3d_compound = vpe20_check_lut3d_compound; + + res->set_dst_cmd_info_scaler = vpe20_set_dst_cmd_info_scaler; + res->update_opp_adjust_and_boundary = vpe20_update_opp_adjust_and_boundary; + + return VPE_STATUS_OK; + +err: + vpe20_destroy_resource(vpe_priv, res); + return VPE_STATUS_ERROR; +} + +bool vpe22_check_input_format(enum vpe_surface_pixel_format format) +{ + if (vpe_is_32bit_packed_rgb(format)) + return true; + + if (vpe_is_yuv420(format)) + return true; + + if (vpe_is_yuv422(format)) + return true; + + if (vpe_is_yuv444(format)) + return true; + + if (vpe_is_fp16(format)) + return true; + + if (vpe_is_rgb16(format)) + return true; + + if (format == VPE_SURFACE_PIXEL_FORMAT_GRPH_RGBE) + return true; + + if (format == VPE_SURFACE_PIXEL_FORMAT_PLANAR_8bpc_RGB) + return true; + + return false; +} + +const struct vpe_caps *vpe22_get_capability(void) +{ + return ∩︀ +} + +void vpe22_setup_check_funcs(struct vpe_check_support_funcs *funcs) +{ + funcs->check_input_format = vpe22_check_input_format; + funcs->check_output_format = vpe20_check_output_format; + funcs->check_input_color_space = vpe10_check_input_color_space; + funcs->check_output_color_space = vpe20_check_output_color_space; + funcs->get_dcc_compression_input_cap = vpe20_get_dcc_compression_input_cap; + funcs->get_dcc_compression_output_cap = vpe20_get_dcc_compression_output_cap; +} diff --git a/src/amd/vpelib/src/core/color.c b/src/amd/vpelib/src/core/color.c index 529d4187ac8..a07f3ccd95d 100644 --- a/src/amd/vpelib/src/core/color.c +++ b/src/amd/vpelib/src/core/color.c @@ -285,6 +285,8 @@ static bool can_bypass_degamma(const struct stream_ctx *stream_ctx) return true; if (stream_ctx->geometric_scaling) return true; + if (stream_ctx->stream.surface_info.format == VPE_SURFACE_PIXEL_FORMAT_GRPH_RGBE) + return true; return false; } @@ -1236,7 +1238,7 @@ enum vpe_status vpe_color_update_whitepoint( stream->white_point_gain = vpe_fixpt_one; } - if (is_fp16) { + if (is_fp16 || (stream->stream.surface_info.format == VPE_SURFACE_PIXEL_FORMAT_GRPH_RGBE)) { stream->white_point_gain = vpe_fixpt_div_int(stream->white_point_gain, CCCS_NORM); } diff --git a/src/amd/vpelib/src/core/resource.c b/src/amd/vpelib/src/core/resource.c index d56be8da5f8..1ffd9bee16f 100644 --- a/src/amd/vpelib/src/core/resource.c +++ b/src/amd/vpelib/src/core/resource.c @@ -34,6 +34,8 @@ #include "vpe20_resource.h" #include "multi_pipe_segmentation.h" +#include "vpe22_resource.h" + static const struct vpe_debug_options debug_defaults = { .flags = {0}, .cm_in_bypass = 0, @@ -101,6 +103,9 @@ enum vpe_ip_level vpe_resource_parse_ip_version( case VPE_VERSION(7, 0, 0): // to be removed when caller switches to new convention ip_level = VPE_IP_LEVEL_2_0; break; + case VPE_VERSION(2, 2, 0): + ip_level = VPE_IP_LEVEL_2_2; + break; default: ip_level = VPE_IP_LEVEL_UNKNOWN; break; @@ -123,6 +128,9 @@ enum vpe_status vpe_construct_resource( case VPE_IP_LEVEL_2_0: status = vpe20_construct_resource(vpe_priv, res); break; + case VPE_IP_LEVEL_2_2: + status = vpe22_construct_resource(vpe_priv, res); + break; default: status = VPE_STATUS_NOT_SUPPORTED; vpe_log("invalid ip level: %d", (int)level); @@ -149,6 +157,9 @@ void vpe_destroy_resource(struct vpe_priv *vpe_priv, struct resource *res) case VPE_IP_LEVEL_2_0: vpe20_destroy_resource(vpe_priv, res); break; + case VPE_IP_LEVEL_2_2: + vpe20_destroy_resource(vpe_priv, res); + break; default: break; } @@ -1012,6 +1023,9 @@ const struct vpe_caps *vpe_get_capability(enum vpe_ip_level ip_level) case VPE_IP_LEVEL_2_0: caps = vpe20_get_capability(); break; + case VPE_IP_LEVEL_2_2: + caps = vpe22_get_capability(); + break; default: caps = NULL; @@ -1031,6 +1045,9 @@ void vpe_setup_check_funcs(struct vpe_check_support_funcs *funcs, enum vpe_ip_le case VPE_IP_LEVEL_2_0: vpe20_setup_check_funcs(funcs); break; + case VPE_IP_LEVEL_2_2: + vpe22_setup_check_funcs(funcs); + break; default: break; }