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amd/vpelib: support vpe 2.2

Browse source 
Update vpelib to support vpe 2.2.

Signed-off-by: Peyton Lee <peytolee@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41876>
This commit is contained in:
Peyton Lee 2026-05-28 17:59:28 +08:00 • committed by Marge Bot
parent 2b2dbcc13a
commit 99c4cd205e
13 changed files with 6717 additions and 2 deletions
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1
src/amd/vpelib/inc/vpe_types.h
View file

@ -131,6 +131,7 @@ enum vpe_ip_level {
VPE_IP_LEVEL_1_0, /**< vpe 1.0 */
VPE_IP_LEVEL_1_1, /**< vpe 1.1 */
VPE_IP_LEVEL_2_0, /**< vpe 2.0 */
VPE_IP_LEVEL_2_2, /**< vpe 2.2 */
};
enum vpe_mps_mode {

4
src/amd/vpelib/meson.build
View file

@ -25,6 +25,7 @@ c_args_vpe += [
'-DVPE_BUILD_1_X',
'-DVPE_BUILD_1_1',
'-DVPE_BUILD_2_0',
'-DVPE_BUILD_2_2',
]
vpe_files = files(
@ -142,6 +143,8 @@ vpe_files = files(
'src/chip/vpe20/vpe20_plane_desc_writer.c',
'src/chip/vpe20/vpe20_resource.c',
'src/chip/vpe20/vpe20_vpe_desc_writer.c',
'src/chip/vpe22/inc/vpe22_resource.h',
'src/chip/vpe22/vpe22_resource.c',
'src/imported/SPL/dc_spl.c',
'src/imported/SPL/dc_spl.h',
'src/imported/SPL/dc_spl_filters.c',
@ -161,6 +164,7 @@ inc_amd_vpe = include_directories(
'src/chip/vpe10/inc',
'src/chip/vpe11/inc',
'src/chip/vpe20/inc',
'src/chip/vpe22/inc',
'src/imported/SPL',
'src/imported',
)

3
src/amd/vpelib/src/chip/vpe20/vpe20_cdc_fe.c
View file

@ -107,7 +107,8 @@ void vpe20_cdc_program_crossbar_config(struct cdc_fe *cdc_fe, enum vpe_surface_p
format == VPE_SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616 ||
format == VPE_SURFACE_PIXEL_FORMAT_GRPH_BGRA16161616_UNORM ||
format == VPE_SURFACE_PIXEL_FORMAT_GRPH_BGRA16161616_SNORM ||
format == VPE_SURFACE_PIXEL_FORMAT_VIDEO_AYCbCr8888) {
format == VPE_SURFACE_PIXEL_FORMAT_VIDEO_AYCbCr8888 ||
format == VPE_SURFACE_PIXEL_FORMAT_GRPH_RGBE) {
red_bar = MUX_SEL_CB_B;
blue_bar = MUX_SEL_CR_R;
}

5
src/amd/vpelib/src/chip/vpe20/vpe20_dpp.c
View file

@ -330,6 +330,10 @@ void vpe20_dpp_program_cnv(
case VPE_SURFACE_PIXEL_FORMAT_VIDEO_CrYCbA1010102: /* Y410 */
pixel_format = 115;
break;
case VPE_SURFACE_PIXEL_FORMAT_GRPH_RGBE:
pixel_format = 116;
alpha_en = 0;
break;
case VPE_SURFACE_PIXEL_FORMAT_GRPH_R8: // use crossbar
pixel_format = 120;
alpha_en = 0;
@ -343,6 +347,7 @@ void vpe20_dpp_program_cnv(
}
REG_SET(VPCNVC_SURFACE_PIXEL_FORMAT, 0, VPCNVC_SURFACE_PIXEL_FORMAT, pixel_format);
// RGBE default set VPCNVC_FORMAT_CROSSBAR_R/G/B to 0x0/0x1/0x2
REG_SET_7(VPCNVC_FORMAT_CONTROL, REG_DEFAULT(VPCNVC_FORMAT_CONTROL), FORMAT_EXPANSION_MODE,
hw_expansion_mode, FORMAT_CNV16, 0, FORMAT_CONTROL__ALPHA_EN, alpha_en, VPCNVC_BYPASS,
dpp->vpe_priv->init.debug.vpcnvc_bypass, VPCNVC_BYPASS_MSB_ALIGN, 0, CLAMP_POSITIVE, 0,

2
src/amd/vpelib/src/chip/vpe20/vpe20_resource.c
View file

@ -2538,6 +2538,8 @@ uint32_t vpe20_get_hw_surface_format(enum vpe_surface_pixel_format format)
surf_format = 298;
break;
case VPE_SURFACE_PIXEL_FORMAT_GRPH_RGBE:
surf_format = 116;
break;
default:
VPE_ASSERT("Invalid pixel format");
break;

1464
src/amd/vpelib/src/chip/vpe22/inc/asic/chip_default.h Normal file
View file

File diff suppressed because it is too large Load diff

1892
src/amd/vpelib/src/chip/vpe22/inc/asic/chip_mask.h Normal file
View file

File diff suppressed because it is too large Load diff

835
src/amd/vpelib/src/chip/vpe22/inc/asic/chip_offset.h Normal file
View file

@ -0,0 +1,835 @@
// Copyright (c) 1994 - 2025 Advanced Micro Devices, Inc. All rights reserved.
/*
* chip_offset.h
*
* Register Spec Release: <unknown>
*
*
* (c) 2021 Advanced Micro Devices, Inc. (unpublished)
*
* All rights reserved. This notice is intended as a precaution against
* inadvertent publication and does not imply publication or any waiver
* of confidentiality. The year included in the foregoing notice is the
* year of creation of the work.
*
*/
#ifndef _vpe22_chip_OFFSET_HEADER
#define _vpe22_chip_OFFSET_HEADER
// Registers from CDC block
#define mmVPEP_MGCG_CNTL 0x11E00
#define mmVPCDC_SOFT_RESET 0x11E01
#define mmVPCDC_FE0_SURFACE_CONFIG 0x11E02
#define mmVPCDC_FE0_CROSSBAR_CONFIG 0x11E03
#define mmVPCDC_FE0_VIEWPORT_START_CONFIG 0x11E04
#define mmVPCDC_FE0_VIEWPORT_DIMENSION_CONFIG 0x11E05
#define mmVPCDC_FE0_VIEWPORT_START_C_CONFIG 0x11E06
#define mmVPCDC_FE0_VIEWPORT_DIMENSION_C_CONFIG 0x11E07
#define mmVPCDC_FE1_SURFACE_CONFIG 0x11E08
#define mmVPCDC_FE1_CROSSBAR_CONFIG 0x11E09
#define mmVPCDC_FE1_VIEWPORT_START_CONFIG 0x11E0A
#define mmVPCDC_FE1_VIEWPORT_DIMENSION_CONFIG 0x11E0B
#define mmVPCDC_FE1_VIEWPORT_START_C_CONFIG 0x11E0C
#define mmVPCDC_FE1_VIEWPORT_DIMENSION_C_CONFIG 0x11E0D
#define mmVPCDC_BE0_P2B_CONFIG 0x11E0E
#define mmVPCDC_BE0_GLOBAL_SYNC_CONFIG 0x11E0F
#define mmVPCDC_BE1_P2B_CONFIG 0x11E10
#define mmVPCDC_BE1_GLOBAL_SYNC_CONFIG 0x11E11
#define mmVPCDC_BE2_P2B_CONFIG 0x11E12
#define mmVPCDC_BE2_GLOBAL_SYNC_CONFIG 0x11E13
#define mmVPCDC_BE3_P2B_CONFIG 0x11E14
#define mmVPCDC_BE3_GLOBAL_SYNC_CONFIG 0x11E15
#define mmVPCDC_GLOBAL_SYNC_TRIGGER 0x11E16
#define mmVPEP_MEM_GLOBAL_PWR_REQ_CNTL 0x11E18
#define mmVPFE0_MEM_PWR_CNTL 0x11E19
#define mmVPFE1_MEM_PWR_CNTL 0x11E1A
#define mmVPBE0_MEM_PWR_CNTL 0x11E1B
#define mmVPBE1_MEM_PWR_CNTL 0x11E1C
#define mmVPBE2_MEM_PWR_CNTL 0x11E1D
#define mmVPBE3_MEM_PWR_CNTL 0x11E1E
#define mmVPCDC_3DLUT_FL_CONFIG 0x11E26
#define mmVPCDC_CONTROL 0x11E27
// Registers from VPCNVC_CFG block
#define mmVPCNVC_CFG0_VPCNVC_SURFACE_PIXEL_FORMAT 0x11F44
#define mmVPCNVC_CFG1_VPCNVC_SURFACE_PIXEL_FORMAT 0x120E0
#define mmVPCNVC_CFG0_VPCNVC_FORMAT_CONTROL 0x11F45
#define mmVPCNVC_CFG1_VPCNVC_FORMAT_CONTROL 0x120E1
#define mmVPCNVC_CFG0_VPCNVC_FCNV_FP_BIAS_R 0x11F46
#define mmVPCNVC_CFG1_VPCNVC_FCNV_FP_BIAS_R 0x120E2
#define mmVPCNVC_CFG0_VPCNVC_FCNV_FP_BIAS_G 0x11F47
#define mmVPCNVC_CFG1_VPCNVC_FCNV_FP_BIAS_G 0x120E3
#define mmVPCNVC_CFG0_VPCNVC_FCNV_FP_BIAS_B 0x11F48
#define mmVPCNVC_CFG1_VPCNVC_FCNV_FP_BIAS_B 0x120E4
#define mmVPCNVC_CFG0_VPCNVC_FCNV_FP_SCALE_R 0x11F49
#define mmVPCNVC_CFG1_VPCNVC_FCNV_FP_SCALE_R 0x120E5
#define mmVPCNVC_CFG0_VPCNVC_FCNV_FP_SCALE_G 0x11F4A
#define mmVPCNVC_CFG1_VPCNVC_FCNV_FP_SCALE_G 0x120E6
#define mmVPCNVC_CFG0_VPCNVC_FCNV_FP_SCALE_B 0x11F4B
#define mmVPCNVC_CFG1_VPCNVC_FCNV_FP_SCALE_B 0x120E7
#define mmVPCNVC_CFG0_VPCNVC_COLOR_KEYER_CONTROL 0x11F4C
#define mmVPCNVC_CFG1_VPCNVC_COLOR_KEYER_CONTROL 0x120E8
#define mmVPCNVC_CFG0_VPCNVC_COLOR_KEYER_ALPHA 0x11F4D
#define mmVPCNVC_CFG1_VPCNVC_COLOR_KEYER_ALPHA 0x120E9
#define mmVPCNVC_CFG0_VPCNVC_COLOR_KEYER_RED 0x11F4E
#define mmVPCNVC_CFG1_VPCNVC_COLOR_KEYER_RED 0x120EA
#define mmVPCNVC_CFG0_VPCNVC_COLOR_KEYER_GREEN 0x11F4F
#define mmVPCNVC_CFG1_VPCNVC_COLOR_KEYER_GREEN 0x120EB
#define mmVPCNVC_CFG0_VPCNVC_COLOR_KEYER_BLUE 0x11F50
#define mmVPCNVC_CFG1_VPCNVC_COLOR_KEYER_BLUE 0x120EC
#define mmVPCNVC_CFG0_VPCNVC_ALPHA_2BIT_LUT01 0x11F52
#define mmVPCNVC_CFG1_VPCNVC_ALPHA_2BIT_LUT01 0x120EE
#define mmVPCNVC_CFG0_VPCNVC_ALPHA_2BIT_LUT23 0x11F53
#define mmVPCNVC_CFG1_VPCNVC_ALPHA_2BIT_LUT23 0x120EF
#define mmVPCNVC_CFG0_VPCNVC_PRE_DEALPHA 0x11F54
#define mmVPCNVC_CFG1_VPCNVC_PRE_DEALPHA 0x120F0
#define mmVPCNVC_CFG0_VPCNVC_PRE_CSC_MODE 0x11F55
#define mmVPCNVC_CFG1_VPCNVC_PRE_CSC_MODE 0x120F1
#define mmVPCNVC_CFG0_VPCNVC_PRE_CSC_C11_C12 0x11F56
#define mmVPCNVC_CFG1_VPCNVC_PRE_CSC_C11_C12 0x120F2
#define mmVPCNVC_CFG0_VPCNVC_PRE_CSC_C13_C14 0x11F57
#define mmVPCNVC_CFG1_VPCNVC_PRE_CSC_C13_C14 0x120F3
#define mmVPCNVC_CFG0_VPCNVC_PRE_CSC_C21_C22 0x11F58
#define mmVPCNVC_CFG1_VPCNVC_PRE_CSC_C21_C22 0x120F4
#define mmVPCNVC_CFG0_VPCNVC_PRE_CSC_C23_C24 0x11F59
#define mmVPCNVC_CFG1_VPCNVC_PRE_CSC_C23_C24 0x120F5
#define mmVPCNVC_CFG0_VPCNVC_PRE_CSC_C31_C32 0x11F5A
#define mmVPCNVC_CFG1_VPCNVC_PRE_CSC_C31_C32 0x120F6
#define mmVPCNVC_CFG0_VPCNVC_PRE_CSC_C33_C34 0x11F5B
#define mmVPCNVC_CFG1_VPCNVC_PRE_CSC_C33_C34 0x120F7
#define mmVPCNVC_CFG0_VPCNVC_COEF_FORMAT 0x11F5C
#define mmVPCNVC_CFG1_VPCNVC_COEF_FORMAT 0x120F8
#define mmVPCNVC_CFG0_VPCNVC_PRE_DEGAM 0x11F5D
#define mmVPCNVC_CFG1_VPCNVC_PRE_DEGAM 0x120F9
#define mmVPCNVC_CFG0_VPCNVC_PRE_REALPHA 0x11F5E
#define mmVPCNVC_CFG1_VPCNVC_PRE_REALPHA 0x120FA
// Registers from VPDSCL block
#define mmVPDSCL0_VPDSCL_COEF_RAM_TAP_SELECT 0x11F68
#define mmVPDSCL1_VPDSCL_COEF_RAM_TAP_SELECT 0x12104
#define mmVPDSCL0_VPDSCL_COEF_RAM_TAP_DATA 0x11F69
#define mmVPDSCL1_VPDSCL_COEF_RAM_TAP_DATA 0x12105
#define mmVPDSCL0_VPDSCL_MODE 0x11F6A
#define mmVPDSCL1_VPDSCL_MODE 0x12106
#define mmVPDSCL0_VPDSCL_TAP_CONTROL 0x11F6B
#define mmVPDSCL1_VPDSCL_TAP_CONTROL 0x12107
#define mmVPDSCL0_VPDSCL_CONTROL 0x11F6C
#define mmVPDSCL1_VPDSCL_CONTROL 0x12108
#define mmVPDSCL0_VPDSCL_2TAP_CONTROL 0x11F6D
#define mmVPDSCL1_VPDSCL_2TAP_CONTROL 0x12109
#define mmVPDSCL0_VPDSCL_MANUAL_REPLICATE_CONTROL 0x11F6E
#define mmVPDSCL1_VPDSCL_MANUAL_REPLICATE_CONTROL 0x1210A
#define mmVPDSCL0_VPDSCL_HORZ_FILTER_SCALE_RATIO 0x11F6F
#define mmVPDSCL1_VPDSCL_HORZ_FILTER_SCALE_RATIO 0x1210B
#define mmVPDSCL0_VPDSCL_HORZ_FILTER_INIT 0x11F70
#define mmVPDSCL1_VPDSCL_HORZ_FILTER_INIT 0x1210C
#define mmVPDSCL0_VPDSCL_HORZ_FILTER_SCALE_RATIO_C 0x11F71
#define mmVPDSCL1_VPDSCL_HORZ_FILTER_SCALE_RATIO_C 0x1210D
#define mmVPDSCL0_VPDSCL_HORZ_FILTER_INIT_C 0x11F72
#define mmVPDSCL1_VPDSCL_HORZ_FILTER_INIT_C 0x1210E
#define mmVPDSCL0_VPDSCL_VERT_FILTER_SCALE_RATIO 0x11F73
#define mmVPDSCL1_VPDSCL_VERT_FILTER_SCALE_RATIO 0x1210F
#define mmVPDSCL0_VPDSCL_VERT_FILTER_INIT 0x11F74
#define mmVPDSCL1_VPDSCL_VERT_FILTER_INIT 0x12110
#define mmVPDSCL0_VPDSCL_VERT_FILTER_INIT_BOT 0x11F75
#define mmVPDSCL1_VPDSCL_VERT_FILTER_INIT_BOT 0x12111
#define mmVPDSCL0_VPDSCL_VERT_FILTER_SCALE_RATIO_C 0x11F76
#define mmVPDSCL1_VPDSCL_VERT_FILTER_SCALE_RATIO_C 0x12112
#define mmVPDSCL0_VPDSCL_VERT_FILTER_INIT_C 0x11F77
#define mmVPDSCL1_VPDSCL_VERT_FILTER_INIT_C 0x12113
#define mmVPDSCL0_VPDSCL_VERT_FILTER_INIT_BOT_C 0x11F78
#define mmVPDSCL1_VPDSCL_VERT_FILTER_INIT_BOT_C 0x12114
#define mmVPDSCL0_VPDSCL_BLACK_COLOR 0x11F79
#define mmVPDSCL1_VPDSCL_BLACK_COLOR 0x12115
#define mmVPDSCL0_VPDSCL_UPDATE 0x11F7A
#define mmVPDSCL1_VPDSCL_UPDATE 0x12116
#define mmVPDSCL0_VPDSCL_AUTOCAL 0x11F7B
#define mmVPDSCL1_VPDSCL_AUTOCAL 0x12117
#define mmVPDSCL0_VPDSCL_EXT_OVERSCAN_LEFT_RIGHT 0x11F7C
#define mmVPDSCL1_VPDSCL_EXT_OVERSCAN_LEFT_RIGHT 0x12118
#define mmVPDSCL0_VPDSCL_EXT_OVERSCAN_TOP_BOTTOM 0x11F7D
#define mmVPDSCL1_VPDSCL_EXT_OVERSCAN_TOP_BOTTOM 0x12119
#define mmVPDSCL0_VPOTG_H_BLANK 0x11F7E
#define mmVPDSCL1_VPOTG_H_BLANK 0x1211A
#define mmVPDSCL0_VPOTG_V_BLANK 0x11F7F
#define mmVPDSCL1_VPOTG_V_BLANK 0x1211B
#define mmVPDSCL0_VPDSCL_RECOUT_START 0x11F80
#define mmVPDSCL1_VPDSCL_RECOUT_START 0x1211C
#define mmVPDSCL0_VPDSCL_RECOUT_SIZE 0x11F81
#define mmVPDSCL1_VPDSCL_RECOUT_SIZE 0x1211D
#define mmVPDSCL0_VPMPC_SIZE 0x11F82
#define mmVPDSCL1_VPMPC_SIZE 0x1211E
#define mmVPDSCL0_VPLB_DATA_FORMAT 0x11F83
#define mmVPDSCL1_VPLB_DATA_FORMAT 0x1211F
#define mmVPDSCL0_VPLB_MEMORY_CTRL 0x11F84
#define mmVPDSCL1_VPLB_MEMORY_CTRL 0x12120
#define mmVPDSCL0_VPLB_V_COUNTER 0x11F85
#define mmVPDSCL1_VPLB_V_COUNTER 0x12121
#define mmVPDSCL0_VPDSCL_MEM_PWR_CTRL 0x11F86
#define mmVPDSCL1_VPDSCL_MEM_PWR_CTRL 0x12122
#define mmVPDSCL0_VPDSCL_MEM_PWR_STATUS 0x11F87
#define mmVPDSCL1_VPDSCL_MEM_PWR_STATUS 0x12123
#define mmVPDSCL0_VPDSCL_EASF_H_MODE 0x11F88
#define mmVPDSCL1_VPDSCL_EASF_H_MODE 0x12124
#define mmVPDSCL0_VPDSCL_EASF_V_MODE 0x11F89
#define mmVPDSCL1_VPDSCL_EASF_V_MODE 0x12125
#define mmVPDSCL0_VPDSCL_SC_MODE 0x11F8A
#define mmVPDSCL1_VPDSCL_SC_MODE 0x12126
#define mmVPDSCL0_VPDSCL_SC_MATRIX_C0C1 0x11F8B
#define mmVPDSCL1_VPDSCL_SC_MATRIX_C0C1 0x12127
#define mmVPDSCL0_VPDSCL_SC_MATRIX_C2C3 0x11F8C
#define mmVPDSCL1_VPDSCL_SC_MATRIX_C2C3 0x12128
#define mmVPDSCL0_VPDSCL_EASF_H_RINGEST_EVENTAP_GAIN 0x11F8D
#define mmVPDSCL1_VPDSCL_EASF_H_RINGEST_EVENTAP_GAIN 0x12129
#define mmVPDSCL0_VPDSCL_EASF_H_RINGEST_EVENTAP_REDUCE 0x11F8E
#define mmVPDSCL1_VPDSCL_EASF_H_RINGEST_EVENTAP_REDUCE 0x1212A
#define mmVPDSCL0_VPDSCL_EASF_V_RINGEST_EVENTAP_GAIN 0x11F8F
#define mmVPDSCL1_VPDSCL_EASF_V_RINGEST_EVENTAP_GAIN 0x1212B
#define mmVPDSCL0_VPDSCL_EASF_V_RINGEST_EVENTAP_REDUCE 0x11F90
#define mmVPDSCL1_VPDSCL_EASF_V_RINGEST_EVENTAP_REDUCE 0x1212C
#define mmVPDSCL0_VPDSCL_EASF_V_RINGEST_3TAP_CNTL1 0x11F91
#define mmVPDSCL1_VPDSCL_EASF_V_RINGEST_3TAP_CNTL1 0x1212D
#define mmVPDSCL0_VPDSCL_EASF_V_RINGEST_3TAP_CNTL2 0x11F92
#define mmVPDSCL1_VPDSCL_EASF_V_RINGEST_3TAP_CNTL2 0x1212E
#define mmVPDSCL0_VPDSCL_EASF_V_RINGEST_3TAP_CNTL3 0x11F93
#define mmVPDSCL1_VPDSCL_EASF_V_RINGEST_3TAP_CNTL3 0x1212F
#define mmVPDSCL0_VPDSCL_EASF_RINGEST_FORCE 0x11F94
#define mmVPDSCL1_VPDSCL_EASF_RINGEST_FORCE 0x12130
#define mmVPDSCL0_VPDSCL_EASF_H_BF_CNTL 0x11F95
#define mmVPDSCL1_VPDSCL_EASF_H_BF_CNTL 0x12131
#define mmVPDSCL0_VPDSCL_EASF_H_BF_FINAL_MAX_MIN 0x11F96
#define mmVPDSCL1_VPDSCL_EASF_H_BF_FINAL_MAX_MIN 0x12132
#define mmVPDSCL0_VPDSCL_EASF_V_BF_CNTL 0x11F97
#define mmVPDSCL1_VPDSCL_EASF_V_BF_CNTL 0x12133
#define mmVPDSCL0_VPDSCL_EASF_V_BF_FINAL_MAX_MIN 0x11F98
#define mmVPDSCL1_VPDSCL_EASF_V_BF_FINAL_MAX_MIN 0x12134
#define mmVPDSCL0_VPDSCL_EASF_H_BF1_PWL_SEG0 0x11F99
#define mmVPDSCL1_VPDSCL_EASF_H_BF1_PWL_SEG0 0x12135
#define mmVPDSCL0_VPDSCL_EASF_H_BF1_PWL_SEG1 0x11F9A
#define mmVPDSCL1_VPDSCL_EASF_H_BF1_PWL_SEG1 0x12136
#define mmVPDSCL0_VPDSCL_EASF_H_BF1_PWL_SEG2 0x11F9B
#define mmVPDSCL1_VPDSCL_EASF_H_BF1_PWL_SEG2 0x12137
#define mmVPDSCL0_VPDSCL_EASF_H_BF1_PWL_SEG3 0x11F9C
#define mmVPDSCL1_VPDSCL_EASF_H_BF1_PWL_SEG3 0x12138
#define mmVPDSCL0_VPDSCL_EASF_H_BF1_PWL_SEG4 0x11F9D
#define mmVPDSCL1_VPDSCL_EASF_H_BF1_PWL_SEG4 0x12139
#define mmVPDSCL0_VPDSCL_EASF_H_BF1_PWL_SEG5 0x11F9E
#define mmVPDSCL1_VPDSCL_EASF_H_BF1_PWL_SEG5 0x1213A
#define mmVPDSCL0_VPDSCL_EASF_H_BF1_PWL_SEG6 0x11F9F
#define mmVPDSCL1_VPDSCL_EASF_H_BF1_PWL_SEG6 0x1213B
#define mmVPDSCL0_VPDSCL_EASF_H_BF1_PWL_SEG7 0x11FA0
#define mmVPDSCL1_VPDSCL_EASF_H_BF1_PWL_SEG7 0x1213C
#define mmVPDSCL0_VPDSCL_EASF_V_BF1_PWL_SEG0 0x11FA1
#define mmVPDSCL1_VPDSCL_EASF_V_BF1_PWL_SEG0 0x1213D
#define mmVPDSCL0_VPDSCL_EASF_V_BF1_PWL_SEG1 0x11FA2
#define mmVPDSCL1_VPDSCL_EASF_V_BF1_PWL_SEG1 0x1213E
#define mmVPDSCL0_VPDSCL_EASF_V_BF1_PWL_SEG2 0x11FA3
#define mmVPDSCL1_VPDSCL_EASF_V_BF1_PWL_SEG2 0x1213F
#define mmVPDSCL0_VPDSCL_EASF_V_BF1_PWL_SEG3 0x11FA4
#define mmVPDSCL1_VPDSCL_EASF_V_BF1_PWL_SEG3 0x12140
#define mmVPDSCL0_VPDSCL_EASF_V_BF1_PWL_SEG4 0x11FA5
#define mmVPDSCL1_VPDSCL_EASF_V_BF1_PWL_SEG4 0x12141
#define mmVPDSCL0_VPDSCL_EASF_V_BF1_PWL_SEG5 0x11FA6
#define mmVPDSCL1_VPDSCL_EASF_V_BF1_PWL_SEG5 0x12142
#define mmVPDSCL0_VPDSCL_EASF_V_BF1_PWL_SEG6 0x11FA7
#define mmVPDSCL1_VPDSCL_EASF_V_BF1_PWL_SEG6 0x12143
#define mmVPDSCL0_VPDSCL_EASF_V_BF1_PWL_SEG7 0x11FA8
#define mmVPDSCL1_VPDSCL_EASF_V_BF1_PWL_SEG7 0x12144
#define mmVPDSCL0_VPDSCL_EASF_H_BF3_PWL_SEG0 0x11FA9
#define mmVPDSCL1_VPDSCL_EASF_H_BF3_PWL_SEG0 0x12145
#define mmVPDSCL0_VPDSCL_EASF_H_BF3_PWL_SEG1 0x11FAA
#define mmVPDSCL1_VPDSCL_EASF_H_BF3_PWL_SEG1 0x12146
#define mmVPDSCL0_VPDSCL_EASF_H_BF3_PWL_SEG2 0x11FAB
#define mmVPDSCL1_VPDSCL_EASF_H_BF3_PWL_SEG2 0x12147
#define mmVPDSCL0_VPDSCL_EASF_H_BF3_PWL_SEG3 0x11FAC
#define mmVPDSCL1_VPDSCL_EASF_H_BF3_PWL_SEG3 0x12148
#define mmVPDSCL0_VPDSCL_EASF_H_BF3_PWL_SEG4 0x11FAD
#define mmVPDSCL1_VPDSCL_EASF_H_BF3_PWL_SEG4 0x12149
#define mmVPDSCL0_VPDSCL_EASF_H_BF3_PWL_SEG5 0x11FAE
#define mmVPDSCL1_VPDSCL_EASF_H_BF3_PWL_SEG5 0x1214A
#define mmVPDSCL0_VPDSCL_EASF_V_BF3_PWL_SEG0 0x11FAF
#define mmVPDSCL1_VPDSCL_EASF_V_BF3_PWL_SEG0 0x1214B
#define mmVPDSCL0_VPDSCL_EASF_V_BF3_PWL_SEG1 0x11FB0
#define mmVPDSCL1_VPDSCL_EASF_V_BF3_PWL_SEG1 0x1214C
#define mmVPDSCL0_VPDSCL_EASF_V_BF3_PWL_SEG2 0x11FB1
#define mmVPDSCL1_VPDSCL_EASF_V_BF3_PWL_SEG2 0x1214D
#define mmVPDSCL0_VPDSCL_EASF_V_BF3_PWL_SEG3 0x11FB2
#define mmVPDSCL1_VPDSCL_EASF_V_BF3_PWL_SEG3 0x1214E
#define mmVPDSCL0_VPDSCL_EASF_V_BF3_PWL_SEG4 0x11FB3
#define mmVPDSCL1_VPDSCL_EASF_V_BF3_PWL_SEG4 0x1214F
#define mmVPDSCL0_VPDSCL_EASF_V_BF3_PWL_SEG5 0x11FB4
#define mmVPDSCL1_VPDSCL_EASF_V_BF3_PWL_SEG5 0x12150
#define mmVPDSCL0_VPISHARP_MODE 0x11FB5
#define mmVPDSCL1_VPISHARP_MODE 0x12151
#define mmVPDSCL0_VPISHARP_DELTA_CTRL 0x11FB6
#define mmVPDSCL1_VPISHARP_DELTA_CTRL 0x12152
#define mmVPDSCL0_VPISHARP_DELTA_INDEX 0x11FB7
#define mmVPDSCL1_VPISHARP_DELTA_INDEX 0x12153
#define mmVPDSCL0_VPISHARP_DELTA_DATA 0x11FB8
#define mmVPDSCL1_VPISHARP_DELTA_DATA 0x12154
#define mmVPDSCL0_VPISHARP_NLDELTA_SOFT_CLIP 0x11FB9
#define mmVPDSCL1_VPISHARP_NLDELTA_SOFT_CLIP 0x12155
#define mmVPDSCL0_VPISHARP_NOISEDET_THRESHOLD 0x11FBA
#define mmVPDSCL1_VPISHARP_NOISEDET_THRESHOLD 0x12156
#define mmVPDSCL0_VPISHARP_NOISE_GAIN_PWL 0x11FBB
#define mmVPDSCL1_VPISHARP_NOISE_GAIN_PWL 0x12157
#define mmVPDSCL0_VPISHARP_LBA_PWL_SEG0 0x11FBC
#define mmVPDSCL1_VPISHARP_LBA_PWL_SEG0 0x12158
#define mmVPDSCL0_VPISHARP_LBA_PWL_SEG1 0x11FBD
#define mmVPDSCL1_VPISHARP_LBA_PWL_SEG1 0x12159
#define mmVPDSCL0_VPISHARP_LBA_PWL_SEG2 0x11FBE
#define mmVPDSCL1_VPISHARP_LBA_PWL_SEG2 0x1215A
#define mmVPDSCL0_VPISHARP_LBA_PWL_SEG3 0x11FBF
#define mmVPDSCL1_VPISHARP_LBA_PWL_SEG3 0x1215B
#define mmVPDSCL0_VPISHARP_LBA_PWL_SEG4 0x11FC0
#define mmVPDSCL1_VPISHARP_LBA_PWL_SEG4 0x1215C
#define mmVPDSCL0_VPISHARP_LBA_PWL_SEG5 0x11FC1
#define mmVPDSCL1_VPISHARP_LBA_PWL_SEG5 0x1215D
#define mmVPDSCL0_VPISHARP_DELTA_LUT_MEM_PWR_CTRL 0x11FC2
#define mmVPDSCL1_VPISHARP_DELTA_LUT_MEM_PWR_CTRL 0x1215E
// Registers from VPCM block
#define mmVPCM0_VPCM_CONTROL 0x1201C
#define mmVPCM1_VPCM_CONTROL 0x121B8
#define mmVPCM0_VPCM_POST_CSC_CONTROL 0x1201D
#define mmVPCM1_VPCM_POST_CSC_CONTROL 0x121B9
#define mmVPCM0_VPCM_POST_CSC_C11_C12 0x1201E
#define mmVPCM1_VPCM_POST_CSC_C11_C12 0x121BA
#define mmVPCM0_VPCM_POST_CSC_C13_C14 0x1201F
#define mmVPCM1_VPCM_POST_CSC_C13_C14 0x121BB
#define mmVPCM0_VPCM_POST_CSC_C21_C22 0x12020
#define mmVPCM1_VPCM_POST_CSC_C21_C22 0x121BC
#define mmVPCM0_VPCM_POST_CSC_C23_C24 0x12021
#define mmVPCM1_VPCM_POST_CSC_C23_C24 0x121BD
#define mmVPCM0_VPCM_POST_CSC_C31_C32 0x12022
#define mmVPCM1_VPCM_POST_CSC_C31_C32 0x121BE
#define mmVPCM0_VPCM_POST_CSC_C33_C34 0x12023
#define mmVPCM1_VPCM_POST_CSC_C33_C34 0x121BF
#define mmVPCM0_VPCM_BIAS_CR_R 0x12024
#define mmVPCM1_VPCM_BIAS_CR_R 0x121C0
#define mmVPCM0_VPCM_BIAS_Y_G_CB_B 0x12025
#define mmVPCM1_VPCM_BIAS_Y_G_CB_B 0x121C1
#define mmVPCM0_VPCM_GAMCOR_CONTROL 0x12026
#define mmVPCM1_VPCM_GAMCOR_CONTROL 0x121C2
#define mmVPCM0_VPCM_GAMCOR_LUT_INDEX 0x12027
#define mmVPCM1_VPCM_GAMCOR_LUT_INDEX 0x121C3
#define mmVPCM0_VPCM_GAMCOR_LUT_DATA 0x12028
#define mmVPCM1_VPCM_GAMCOR_LUT_DATA 0x121C4
#define mmVPCM0_VPCM_GAMCOR_LUT_CONTROL 0x12029
#define mmVPCM1_VPCM_GAMCOR_LUT_CONTROL 0x121C5
#define mmVPCM0_VPCM_GAMCOR_RAMA_START_CNTL_B 0x1202A
#define mmVPCM1_VPCM_GAMCOR_RAMA_START_CNTL_B 0x121C6
#define mmVPCM0_VPCM_GAMCOR_RAMA_START_CNTL_G 0x1202B
#define mmVPCM1_VPCM_GAMCOR_RAMA_START_CNTL_G 0x121C7
#define mmVPCM0_VPCM_GAMCOR_RAMA_START_CNTL_R 0x1202C
#define mmVPCM1_VPCM_GAMCOR_RAMA_START_CNTL_R 0x121C8
#define mmVPCM0_VPCM_GAMCOR_RAMA_START_SLOPE_CNTL_B 0x1202D
#define mmVPCM1_VPCM_GAMCOR_RAMA_START_SLOPE_CNTL_B 0x121C9
#define mmVPCM0_VPCM_GAMCOR_RAMA_START_SLOPE_CNTL_G 0x1202E
#define mmVPCM1_VPCM_GAMCOR_RAMA_START_SLOPE_CNTL_G 0x121CA
#define mmVPCM0_VPCM_GAMCOR_RAMA_START_SLOPE_CNTL_R 0x1202F
#define mmVPCM1_VPCM_GAMCOR_RAMA_START_SLOPE_CNTL_R 0x121CB
#define mmVPCM0_VPCM_GAMCOR_RAMA_START_BASE_CNTL_B 0x12030
#define mmVPCM1_VPCM_GAMCOR_RAMA_START_BASE_CNTL_B 0x121CC
#define mmVPCM0_VPCM_GAMCOR_RAMA_START_BASE_CNTL_G 0x12031
#define mmVPCM1_VPCM_GAMCOR_RAMA_START_BASE_CNTL_G 0x121CD
#define mmVPCM0_VPCM_GAMCOR_RAMA_START_BASE_CNTL_R 0x12032
#define mmVPCM1_VPCM_GAMCOR_RAMA_START_BASE_CNTL_R 0x121CE
#define mmVPCM0_VPCM_GAMCOR_RAMA_END_CNTL1_B 0x12033
#define mmVPCM1_VPCM_GAMCOR_RAMA_END_CNTL1_B 0x121CF
#define mmVPCM0_VPCM_GAMCOR_RAMA_END_CNTL2_B 0x12034
#define mmVPCM1_VPCM_GAMCOR_RAMA_END_CNTL2_B 0x121D0
#define mmVPCM0_VPCM_GAMCOR_RAMA_END_CNTL1_G 0x12035
#define mmVPCM1_VPCM_GAMCOR_RAMA_END_CNTL1_G 0x121D1
#define mmVPCM0_VPCM_GAMCOR_RAMA_END_CNTL2_G 0x12036
#define mmVPCM1_VPCM_GAMCOR_RAMA_END_CNTL2_G 0x121D2
#define mmVPCM0_VPCM_GAMCOR_RAMA_END_CNTL1_R 0x12037
#define mmVPCM1_VPCM_GAMCOR_RAMA_END_CNTL1_R 0x121D3
#define mmVPCM0_VPCM_GAMCOR_RAMA_END_CNTL2_R 0x12038
#define mmVPCM1_VPCM_GAMCOR_RAMA_END_CNTL2_R 0x121D4
#define mmVPCM0_VPCM_GAMCOR_RAMA_OFFSET_B 0x12039
#define mmVPCM1_VPCM_GAMCOR_RAMA_OFFSET_B 0x121D5
#define mmVPCM0_VPCM_GAMCOR_RAMA_OFFSET_G 0x1203A
#define mmVPCM1_VPCM_GAMCOR_RAMA_OFFSET_G 0x121D6
#define mmVPCM0_VPCM_GAMCOR_RAMA_OFFSET_R 0x1203B
#define mmVPCM1_VPCM_GAMCOR_RAMA_OFFSET_R 0x121D7
#define mmVPCM0_VPCM_GAMCOR_RAMA_REGION_0_1 0x1203C
#define mmVPCM1_VPCM_GAMCOR_RAMA_REGION_0_1 0x121D8
#define mmVPCM0_VPCM_GAMCOR_RAMA_REGION_2_3 0x1203D
#define mmVPCM1_VPCM_GAMCOR_RAMA_REGION_2_3 0x121D9
#define mmVPCM0_VPCM_GAMCOR_RAMA_REGION_4_5 0x1203E
#define mmVPCM1_VPCM_GAMCOR_RAMA_REGION_4_5 0x121DA
#define mmVPCM0_VPCM_GAMCOR_RAMA_REGION_6_7 0x1203F
#define mmVPCM1_VPCM_GAMCOR_RAMA_REGION_6_7 0x121DB
#define mmVPCM0_VPCM_GAMCOR_RAMA_REGION_8_9 0x12040
#define mmVPCM1_VPCM_GAMCOR_RAMA_REGION_8_9 0x121DC
#define mmVPCM0_VPCM_GAMCOR_RAMA_REGION_10_11 0x12041
#define mmVPCM1_VPCM_GAMCOR_RAMA_REGION_10_11 0x121DD
#define mmVPCM0_VPCM_GAMCOR_RAMA_REGION_12_13 0x12042
#define mmVPCM1_VPCM_GAMCOR_RAMA_REGION_12_13 0x121DE
#define mmVPCM0_VPCM_GAMCOR_RAMA_REGION_14_15 0x12043
#define mmVPCM1_VPCM_GAMCOR_RAMA_REGION_14_15 0x121DF
#define mmVPCM0_VPCM_GAMCOR_RAMA_REGION_16_17 0x12044
#define mmVPCM1_VPCM_GAMCOR_RAMA_REGION_16_17 0x121E0
#define mmVPCM0_VPCM_GAMCOR_RAMA_REGION_18_19 0x12045
#define mmVPCM1_VPCM_GAMCOR_RAMA_REGION_18_19 0x121E1
#define mmVPCM0_VPCM_GAMCOR_RAMA_REGION_20_21 0x12046
#define mmVPCM1_VPCM_GAMCOR_RAMA_REGION_20_21 0x121E2
#define mmVPCM0_VPCM_GAMCOR_RAMA_REGION_22_23 0x12047
#define mmVPCM1_VPCM_GAMCOR_RAMA_REGION_22_23 0x121E3
#define mmVPCM0_VPCM_GAMCOR_RAMA_REGION_24_25 0x12048
#define mmVPCM1_VPCM_GAMCOR_RAMA_REGION_24_25 0x121E4
#define mmVPCM0_VPCM_GAMCOR_RAMA_REGION_26_27 0x12049
#define mmVPCM1_VPCM_GAMCOR_RAMA_REGION_26_27 0x121E5
#define mmVPCM0_VPCM_GAMCOR_RAMA_REGION_28_29 0x1204A
#define mmVPCM1_VPCM_GAMCOR_RAMA_REGION_28_29 0x121E6
#define mmVPCM0_VPCM_GAMCOR_RAMA_REGION_30_31 0x1204B
#define mmVPCM1_VPCM_GAMCOR_RAMA_REGION_30_31 0x121E7
#define mmVPCM0_VPCM_GAMCOR_RAMA_REGION_32_33 0x1204C
#define mmVPCM1_VPCM_GAMCOR_RAMA_REGION_32_33 0x121E8
#define mmVPCM0_VPCM_HDR_MULT_COEF 0x1204D
#define mmVPCM1_VPCM_HDR_MULT_COEF 0x121E9
#define mmVPCM0_VPCM_MEM_PWR_CTRL 0x1204E
#define mmVPCM1_VPCM_MEM_PWR_CTRL 0x121EA
#define mmVPCM0_VPCM_MEM_PWR_STATUS 0x1204F
#define mmVPCM1_VPCM_MEM_PWR_STATUS 0x121EB
#define mmVPCM0_VPCM_DEALPHA 0x12051
#define mmVPCM1_VPCM_DEALPHA 0x121ED
#define mmVPCM0_VPCM_COEF_FORMAT 0x12052
#define mmVPCM1_VPCM_COEF_FORMAT 0x121EE
#define mmVPCM0_VPCM_HIST_CNTL 0x12055
#define mmVPCM1_VPCM_HIST_CNTL 0x121F1
#define mmVPCM0_VPCM_HIST_SCALE_SRC1 0x12056
#define mmVPCM1_VPCM_HIST_SCALE_SRC1 0x121F2
#define mmVPCM0_VPCM_HIST_COEFA_SRC2 0x12057
#define mmVPCM1_VPCM_HIST_COEFA_SRC2 0x121F3
#define mmVPCM0_VPCM_HIST_COEFB_SRC2 0x12058
#define mmVPCM1_VPCM_HIST_COEFB_SRC2 0x121F4
#define mmVPCM0_VPCM_HIST_COEFC_SRC2 0x12059
#define mmVPCM1_VPCM_HIST_COEFC_SRC2 0x121F5
#define mmVPCM0_VPCM_HIST_SCALE_SRC3 0x1205A
#define mmVPCM1_VPCM_HIST_SCALE_SRC3 0x121F6
#define mmVPCM0_VPCM_HIST_BIAS_SRC1 0x1205B
#define mmVPCM1_VPCM_HIST_BIAS_SRC1 0x121F7
#define mmVPCM0_VPCM_HIST_BIAS_SRC2 0x1205C
#define mmVPCM1_VPCM_HIST_BIAS_SRC2 0x121F8
#define mmVPCM0_VPCM_HIST_BIAS_SRC3 0x1205D
#define mmVPCM1_VPCM_HIST_BIAS_SRC3 0x121F9
// Registers from VPDPP_TOP block
#define mmVPDPP_TOP0_VPDPP_CONTROL 0x11F38
#define mmVPDPP_TOP1_VPDPP_CONTROL 0x120D4
#define mmVPDPP_TOP0_VPDPP_CRC_CTRL 0x11F3C
#define mmVPDPP_TOP1_VPDPP_CRC_CTRL 0x120D8
// Registers from VPMPC_CFG block
#define mmVPMPC_CLOCK_CONTROL 0x12768
#define mmVPMPC_SOFT_RESET 0x12769
#define mmVPMPC_CRC_CTRL 0x1276A
#define mmVPMPC_CRC_SEL_CONTROL 0x1276B
#define mmVPMPC_CRC_RESULT_AR 0x1276C
#define mmVPMPC_CRC_RESULT_GB 0x1276D
#define mmVPMPC_CRC_RESULT_C 0x1276E
#define mmVPMPC_BYPASS_BG_AR 0x12771
#define mmVPMPC_BYPASS_BG_GB 0x12772
#define mmVPMPC_HOST_READ_CONTROL 0x12773
#define mmVPMPC_PENDING_STATUS_MISC 0x12774
#define mmVPMPC_VPCDC0_3DLUT_FL_CONFIG 0x12775
#define mmVPMPC_VPCDC0_3DLUT_FL_BIAS_SCALE 0x12776
// Registers from VPMPC_OCSC block
#define mmVPMPC_OUT0_MUX 0x12789
#define mmVPMPC_OUT0_FLOAT_CONTROL 0x1278A
#define mmVPMPC_OUT0_DENORM_CONTROL 0x1278B
#define mmVPMPC_OUT0_DENORM_CLAMP_G_Y 0x1278C
#define mmVPMPC_OUT0_DENORM_CLAMP_B_CB 0x1278D
#define mmVPMPC_OUT1_MUX 0x1278E
#define mmVPMPC_OUT1_FLOAT_CONTROL 0x1278F
#define mmVPMPC_OUT1_DENORM_CONTROL 0x12790
#define mmVPMPC_OUT1_DENORM_CLAMP_G_Y 0x12791
#define mmVPMPC_OUT1_DENORM_CLAMP_B_CB 0x12792
#define mmVPMPC_OUT_CSC_COEF_FORMAT 0x1279D
#define mmVPMPC_OUT0_CSC_MODE 0x1279E
#define mmVPMPC_OUT0_CSC_C11_C12_A 0x1279F
#define mmVPMPC_OUT0_CSC_C13_C14_A 0x127A0
#define mmVPMPC_OUT0_CSC_C21_C22_A 0x127A1
#define mmVPMPC_OUT0_CSC_C23_C24_A 0x127A2
#define mmVPMPC_OUT0_CSC_C31_C32_A 0x127A3
#define mmVPMPC_OUT0_CSC_C33_C34_A 0x127A4
#define mmVPMPC_OUT1_CSC_MODE 0x127A5
#define mmVPMPC_OUT1_CSC_C11_C12_A 0x127A6
#define mmVPMPC_OUT1_CSC_C13_C14_A 0x127A7
#define mmVPMPC_OUT1_CSC_C21_C22_A 0x127A8
#define mmVPMPC_OUT1_CSC_C23_C24_A 0x127A9
#define mmVPMPC_OUT1_CSC_C31_C32_A 0x127AA
#define mmVPMPC_OUT1_CSC_C33_C34_A 0x127AB
// Registers from VPMPCC block
#define mmVPMPCC0_VPMPCC_TOP_SEL 0x125C0
#define mmVPMPCC1_VPMPCC_TOP_SEL 0x125D5
#define mmVPMPCC0_VPMPCC_BOT_SEL 0x125C1
#define mmVPMPCC1_VPMPCC_BOT_SEL 0x125D6
#define mmVPMPCC0_VPMPCC_VPOPP_ID 0x125C2
#define mmVPMPCC1_VPMPCC_VPOPP_ID 0x125D7
#define mmVPMPCC0_VPMPCC_CONTROL 0x125C3
#define mmVPMPCC1_VPMPCC_CONTROL 0x125D8
#define mmVPMPCC0_VPMPCC_CONTROL2 0x125C4
#define mmVPMPCC1_VPMPCC_CONTROL2 0x125D9
#define mmVPMPCC0_VPMPCC_TOP_GAIN 0x125C5
#define mmVPMPCC1_VPMPCC_TOP_GAIN 0x125DA
#define mmVPMPCC0_VPMPCC_BOT_GAIN_INSIDE 0x125C6
#define mmVPMPCC1_VPMPCC_BOT_GAIN_INSIDE 0x125DB
#define mmVPMPCC0_VPMPCC_BOT_GAIN_OUTSIDE 0x125C7
#define mmVPMPCC1_VPMPCC_BOT_GAIN_OUTSIDE 0x125DC
#define mmVPMPCC0_VPMPCC_MOVABLE_CM_LOCATION_CONTROL 0x125C8
#define mmVPMPCC1_VPMPCC_MOVABLE_CM_LOCATION_CONTROL 0x125DD
#define mmVPMPCC0_VPMPCC_BG_R_CR 0x125C9
#define mmVPMPCC1_VPMPCC_BG_R_CR 0x125DE
#define mmVPMPCC0_VPMPCC_BG_G_Y 0x125CA
#define mmVPMPCC1_VPMPCC_BG_G_Y 0x125DF
#define mmVPMPCC0_VPMPCC_BG_B_CB 0x125CB
#define mmVPMPCC1_VPMPCC_BG_B_CB 0x125E0
#define mmVPMPCC0_VPMPCC_MEM_PWR_CTRL 0x125CC
#define mmVPMPCC1_VPMPCC_MEM_PWR_CTRL 0x125E1
#define mmVPMPCC0_VPMPCC_STATUS 0x125CD
#define mmVPMPCC1_VPMPCC_STATUS 0x125E2
// Registers from VPMPCC_OGAM block
#define mmVPMPCC_OGAM0_VPMPCC_OGAM_CONTROL 0x12614
#define mmVPMPCC_OGAM1_VPMPCC_OGAM_CONTROL 0x1264B
#define mmVPMPCC_OGAM0_VPMPCC_OGAM_LUT_INDEX 0x12615
#define mmVPMPCC_OGAM1_VPMPCC_OGAM_LUT_INDEX 0x1264C
#define mmVPMPCC_OGAM0_VPMPCC_OGAM_LUT_DATA 0x12616
#define mmVPMPCC_OGAM1_VPMPCC_OGAM_LUT_DATA 0x1264D
#define mmVPMPCC_OGAM0_VPMPCC_OGAM_LUT_CONTROL 0x12617
#define mmVPMPCC_OGAM1_VPMPCC_OGAM_LUT_CONTROL 0x1264E
#define mmVPMPCC_OGAM0_VPMPCC_OGAM_RAMA_START_CNTL_B 0x12618
#define mmVPMPCC_OGAM1_VPMPCC_OGAM_RAMA_START_CNTL_B 0x1264F
#define mmVPMPCC_OGAM0_VPMPCC_OGAM_RAMA_START_CNTL_G 0x12619
#define mmVPMPCC_OGAM1_VPMPCC_OGAM_RAMA_START_CNTL_G 0x12650
#define mmVPMPCC_OGAM0_VPMPCC_OGAM_RAMA_START_CNTL_R 0x1261A
#define mmVPMPCC_OGAM1_VPMPCC_OGAM_RAMA_START_CNTL_R 0x12651
#define mmVPMPCC_OGAM0_VPMPCC_OGAM_RAMA_START_SLOPE_CNTL_B 0x1261B
#define mmVPMPCC_OGAM1_VPMPCC_OGAM_RAMA_START_SLOPE_CNTL_B 0x12652
#define mmVPMPCC_OGAM0_VPMPCC_OGAM_RAMA_START_SLOPE_CNTL_G 0x1261C
#define mmVPMPCC_OGAM1_VPMPCC_OGAM_RAMA_START_SLOPE_CNTL_G 0x12653
#define mmVPMPCC_OGAM0_VPMPCC_OGAM_RAMA_START_SLOPE_CNTL_R 0x1261D
#define mmVPMPCC_OGAM1_VPMPCC_OGAM_RAMA_START_SLOPE_CNTL_R 0x12654
#define mmVPMPCC_OGAM0_VPMPCC_OGAM_RAMA_START_BASE_CNTL_B 0x1261E
#define mmVPMPCC_OGAM1_VPMPCC_OGAM_RAMA_START_BASE_CNTL_B 0x12655
#define mmVPMPCC_OGAM0_VPMPCC_OGAM_RAMA_START_BASE_CNTL_G 0x1261F
#define mmVPMPCC_OGAM1_VPMPCC_OGAM_RAMA_START_BASE_CNTL_G 0x12656
#define mmVPMPCC_OGAM0_VPMPCC_OGAM_RAMA_START_BASE_CNTL_R 0x12620
#define mmVPMPCC_OGAM1_VPMPCC_OGAM_RAMA_START_BASE_CNTL_R 0x12657
#define mmVPMPCC_OGAM0_VPMPCC_OGAM_RAMA_END_CNTL1_B 0x12621
#define mmVPMPCC_OGAM1_VPMPCC_OGAM_RAMA_END_CNTL1_B 0x12658
#define mmVPMPCC_OGAM0_VPMPCC_OGAM_RAMA_END_CNTL2_B 0x12622
#define mmVPMPCC_OGAM1_VPMPCC_OGAM_RAMA_END_CNTL2_B 0x12659
#define mmVPMPCC_OGAM0_VPMPCC_OGAM_RAMA_END_CNTL1_G 0x12623
#define mmVPMPCC_OGAM1_VPMPCC_OGAM_RAMA_END_CNTL1_G 0x1265A
#define mmVPMPCC_OGAM0_VPMPCC_OGAM_RAMA_END_CNTL2_G 0x12624
#define mmVPMPCC_OGAM1_VPMPCC_OGAM_RAMA_END_CNTL2_G 0x1265B
#define mmVPMPCC_OGAM0_VPMPCC_OGAM_RAMA_END_CNTL1_R 0x12625
#define mmVPMPCC_OGAM1_VPMPCC_OGAM_RAMA_END_CNTL1_R 0x1265C
#define mmVPMPCC_OGAM0_VPMPCC_OGAM_RAMA_END_CNTL2_R 0x12626
#define mmVPMPCC_OGAM1_VPMPCC_OGAM_RAMA_END_CNTL2_R 0x1265D
#define mmVPMPCC_OGAM0_VPMPCC_OGAM_RAMA_OFFSET_B 0x12627
#define mmVPMPCC_OGAM1_VPMPCC_OGAM_RAMA_OFFSET_B 0x1265E
#define mmVPMPCC_OGAM0_VPMPCC_OGAM_RAMA_OFFSET_G 0x12628
#define mmVPMPCC_OGAM1_VPMPCC_OGAM_RAMA_OFFSET_G 0x1265F
#define mmVPMPCC_OGAM0_VPMPCC_OGAM_RAMA_OFFSET_R 0x12629
#define mmVPMPCC_OGAM1_VPMPCC_OGAM_RAMA_OFFSET_R 0x12660
#define mmVPMPCC_OGAM0_VPMPCC_OGAM_RAMA_REGION_0_1 0x1262A
#define mmVPMPCC_OGAM1_VPMPCC_OGAM_RAMA_REGION_0_1 0x12661
#define mmVPMPCC_OGAM0_VPMPCC_OGAM_RAMA_REGION_2_3 0x1262B
#define mmVPMPCC_OGAM1_VPMPCC_OGAM_RAMA_REGION_2_3 0x12662
#define mmVPMPCC_OGAM0_VPMPCC_OGAM_RAMA_REGION_4_5 0x1262C
#define mmVPMPCC_OGAM1_VPMPCC_OGAM_RAMA_REGION_4_5 0x12663
#define mmVPMPCC_OGAM0_VPMPCC_OGAM_RAMA_REGION_6_7 0x1262D
#define mmVPMPCC_OGAM1_VPMPCC_OGAM_RAMA_REGION_6_7 0x12664
#define mmVPMPCC_OGAM0_VPMPCC_OGAM_RAMA_REGION_8_9 0x1262E
#define mmVPMPCC_OGAM1_VPMPCC_OGAM_RAMA_REGION_8_9 0x12665
#define mmVPMPCC_OGAM0_VPMPCC_OGAM_RAMA_REGION_10_11 0x1262F
#define mmVPMPCC_OGAM1_VPMPCC_OGAM_RAMA_REGION_10_11 0x12666
#define mmVPMPCC_OGAM0_VPMPCC_OGAM_RAMA_REGION_12_13 0x12630
#define mmVPMPCC_OGAM1_VPMPCC_OGAM_RAMA_REGION_12_13 0x12667
#define mmVPMPCC_OGAM0_VPMPCC_OGAM_RAMA_REGION_14_15 0x12631
#define mmVPMPCC_OGAM1_VPMPCC_OGAM_RAMA_REGION_14_15 0x12668
#define mmVPMPCC_OGAM0_VPMPCC_OGAM_RAMA_REGION_16_17 0x12632
#define mmVPMPCC_OGAM1_VPMPCC_OGAM_RAMA_REGION_16_17 0x12669
#define mmVPMPCC_OGAM0_VPMPCC_OGAM_RAMA_REGION_18_19 0x12633
#define mmVPMPCC_OGAM1_VPMPCC_OGAM_RAMA_REGION_18_19 0x1266A
#define mmVPMPCC_OGAM0_VPMPCC_OGAM_RAMA_REGION_20_21 0x12634
#define mmVPMPCC_OGAM1_VPMPCC_OGAM_RAMA_REGION_20_21 0x1266B
#define mmVPMPCC_OGAM0_VPMPCC_OGAM_RAMA_REGION_22_23 0x12635
#define mmVPMPCC_OGAM1_VPMPCC_OGAM_RAMA_REGION_22_23 0x1266C
#define mmVPMPCC_OGAM0_VPMPCC_OGAM_RAMA_REGION_24_25 0x12636
#define mmVPMPCC_OGAM1_VPMPCC_OGAM_RAMA_REGION_24_25 0x1266D
#define mmVPMPCC_OGAM0_VPMPCC_OGAM_RAMA_REGION_26_27 0x12637
#define mmVPMPCC_OGAM1_VPMPCC_OGAM_RAMA_REGION_26_27 0x1266E
#define mmVPMPCC_OGAM0_VPMPCC_OGAM_RAMA_REGION_28_29 0x12638
#define mmVPMPCC_OGAM1_VPMPCC_OGAM_RAMA_REGION_28_29 0x1266F
#define mmVPMPCC_OGAM0_VPMPCC_OGAM_RAMA_REGION_30_31 0x12639
#define mmVPMPCC_OGAM1_VPMPCC_OGAM_RAMA_REGION_30_31 0x12670
#define mmVPMPCC_OGAM0_VPMPCC_OGAM_RAMA_REGION_32_33 0x1263A
#define mmVPMPCC_OGAM1_VPMPCC_OGAM_RAMA_REGION_32_33 0x12671
#define mmVPMPCC_OGAM0_VPMPCC_GAMUT_REMAP_COEF_FORMAT 0x1263B
#define mmVPMPCC_OGAM1_VPMPCC_GAMUT_REMAP_COEF_FORMAT 0x12672
#define mmVPMPCC_OGAM0_VPMPCC_GAMUT_REMAP_MODE 0x1263C
#define mmVPMPCC_OGAM1_VPMPCC_GAMUT_REMAP_MODE 0x12673
#define mmVPMPCC_OGAM0_VPMPC_GAMUT_REMAP_C11_C12_A 0x1263D
#define mmVPMPCC_OGAM1_VPMPC_GAMUT_REMAP_C11_C12_A 0x12674
#define mmVPMPCC_OGAM0_VPMPC_GAMUT_REMAP_C13_C14_A 0x1263E
#define mmVPMPCC_OGAM1_VPMPC_GAMUT_REMAP_C13_C14_A 0x12675
#define mmVPMPCC_OGAM0_VPMPC_GAMUT_REMAP_C21_C22_A 0x1263F
#define mmVPMPCC_OGAM1_VPMPC_GAMUT_REMAP_C21_C22_A 0x12676
#define mmVPMPCC_OGAM0_VPMPC_GAMUT_REMAP_C23_C24_A 0x12640
#define mmVPMPCC_OGAM1_VPMPC_GAMUT_REMAP_C23_C24_A 0x12677
#define mmVPMPCC_OGAM0_VPMPC_GAMUT_REMAP_C31_C32_A 0x12641
#define mmVPMPCC_OGAM1_VPMPC_GAMUT_REMAP_C31_C32_A 0x12678
#define mmVPMPCC_OGAM0_VPMPC_GAMUT_REMAP_C33_C34_A 0x12642
#define mmVPMPCC_OGAM1_VPMPC_GAMUT_REMAP_C33_C34_A 0x12679
// Registers from VPMPCC_MCM block
#define mmVPMPCC_MCM0_VPMPCC_MCM_1DLUT_CONTROL 0x12882
#define mmVPMPCC_MCM1_VPMPCC_MCM_1DLUT_CONTROL 0x12912
#define mmVPMPCC_MCM0_VPMPCC_MCM_1DLUT_LUT_INDEX 0x12883
#define mmVPMPCC_MCM1_VPMPCC_MCM_1DLUT_LUT_INDEX 0x12913
#define mmVPMPCC_MCM0_VPMPCC_MCM_1DLUT_LUT_DATA 0x12884
#define mmVPMPCC_MCM1_VPMPCC_MCM_1DLUT_LUT_DATA 0x12914
#define mmVPMPCC_MCM0_VPMPCC_MCM_1DLUT_LUT_CONTROL 0x12885
#define mmVPMPCC_MCM1_VPMPCC_MCM_1DLUT_LUT_CONTROL 0x12915
#define mmVPMPCC_MCM0_VPMPCC_MCM_1DLUT_RAMA_START_CNTL_B 0x12886
#define mmVPMPCC_MCM1_VPMPCC_MCM_1DLUT_RAMA_START_CNTL_B 0x12916
#define mmVPMPCC_MCM0_VPMPCC_MCM_1DLUT_RAMA_START_CNTL_G 0x12887
#define mmVPMPCC_MCM1_VPMPCC_MCM_1DLUT_RAMA_START_CNTL_G 0x12917
#define mmVPMPCC_MCM0_VPMPCC_MCM_1DLUT_RAMA_START_CNTL_R 0x12888
#define mmVPMPCC_MCM1_VPMPCC_MCM_1DLUT_RAMA_START_CNTL_R 0x12918
#define mmVPMPCC_MCM0_VPMPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_B 0x12889
#define mmVPMPCC_MCM1_VPMPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_B 0x12919
#define mmVPMPCC_MCM0_VPMPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_G 0x1288A
#define mmVPMPCC_MCM1_VPMPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_G 0x1291A
#define mmVPMPCC_MCM0_VPMPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_R 0x1288B
#define mmVPMPCC_MCM1_VPMPCC_MCM_1DLUT_RAMA_START_SLOPE_CNTL_R 0x1291B
#define mmVPMPCC_MCM0_VPMPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_B 0x1288C
#define mmVPMPCC_MCM1_VPMPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_B 0x1291C
#define mmVPMPCC_MCM0_VPMPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_G 0x1288D
#define mmVPMPCC_MCM1_VPMPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_G 0x1291D
#define mmVPMPCC_MCM0_VPMPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_R 0x1288E
#define mmVPMPCC_MCM1_VPMPCC_MCM_1DLUT_RAMA_START_BASE_CNTL_R 0x1291E
#define mmVPMPCC_MCM0_VPMPCC_MCM_1DLUT_RAMA_END_CNTL1_B 0x1288F
#define mmVPMPCC_MCM1_VPMPCC_MCM_1DLUT_RAMA_END_CNTL1_B 0x1291F
#define mmVPMPCC_MCM0_VPMPCC_MCM_1DLUT_RAMA_END_CNTL2_B 0x12890
#define mmVPMPCC_MCM1_VPMPCC_MCM_1DLUT_RAMA_END_CNTL2_B 0x12920
#define mmVPMPCC_MCM0_VPMPCC_MCM_1DLUT_RAMA_END_CNTL1_G 0x12891
#define mmVPMPCC_MCM1_VPMPCC_MCM_1DLUT_RAMA_END_CNTL1_G 0x12921
#define mmVPMPCC_MCM0_VPMPCC_MCM_1DLUT_RAMA_END_CNTL2_G 0x12892
#define mmVPMPCC_MCM1_VPMPCC_MCM_1DLUT_RAMA_END_CNTL2_G 0x12922
#define mmVPMPCC_MCM0_VPMPCC_MCM_1DLUT_RAMA_END_CNTL1_R 0x12893
#define mmVPMPCC_MCM1_VPMPCC_MCM_1DLUT_RAMA_END_CNTL1_R 0x12923
#define mmVPMPCC_MCM0_VPMPCC_MCM_1DLUT_RAMA_END_CNTL2_R 0x12894
#define mmVPMPCC_MCM1_VPMPCC_MCM_1DLUT_RAMA_END_CNTL2_R 0x12924
#define mmVPMPCC_MCM0_VPMPCC_MCM_1DLUT_RAMA_OFFSET_B 0x12895
#define mmVPMPCC_MCM1_VPMPCC_MCM_1DLUT_RAMA_OFFSET_B 0x12925
#define mmVPMPCC_MCM0_VPMPCC_MCM_1DLUT_RAMA_OFFSET_G 0x12896
#define mmVPMPCC_MCM1_VPMPCC_MCM_1DLUT_RAMA_OFFSET_G 0x12926
#define mmVPMPCC_MCM0_VPMPCC_MCM_1DLUT_RAMA_OFFSET_R 0x12897
#define mmVPMPCC_MCM1_VPMPCC_MCM_1DLUT_RAMA_OFFSET_R 0x12927
#define mmVPMPCC_MCM0_VPMPCC_MCM_1DLUT_RAMA_REGION_0_1 0x12898
#define mmVPMPCC_MCM1_VPMPCC_MCM_1DLUT_RAMA_REGION_0_1 0x12928
#define mmVPMPCC_MCM0_VPMPCC_MCM_1DLUT_RAMA_REGION_2_3 0x12899
#define mmVPMPCC_MCM1_VPMPCC_MCM_1DLUT_RAMA_REGION_2_3 0x12929
#define mmVPMPCC_MCM0_VPMPCC_MCM_1DLUT_RAMA_REGION_4_5 0x1289A
#define mmVPMPCC_MCM1_VPMPCC_MCM_1DLUT_RAMA_REGION_4_5 0x1292A
#define mmVPMPCC_MCM0_VPMPCC_MCM_1DLUT_RAMA_REGION_6_7 0x1289B
#define mmVPMPCC_MCM1_VPMPCC_MCM_1DLUT_RAMA_REGION_6_7 0x1292B
#define mmVPMPCC_MCM0_VPMPCC_MCM_1DLUT_RAMA_REGION_8_9 0x1289C
#define mmVPMPCC_MCM1_VPMPCC_MCM_1DLUT_RAMA_REGION_8_9 0x1292C
#define mmVPMPCC_MCM0_VPMPCC_MCM_1DLUT_RAMA_REGION_10_11 0x1289D
#define mmVPMPCC_MCM1_VPMPCC_MCM_1DLUT_RAMA_REGION_10_11 0x1292D
#define mmVPMPCC_MCM0_VPMPCC_MCM_1DLUT_RAMA_REGION_12_13 0x1289E
#define mmVPMPCC_MCM1_VPMPCC_MCM_1DLUT_RAMA_REGION_12_13 0x1292E
#define mmVPMPCC_MCM0_VPMPCC_MCM_1DLUT_RAMA_REGION_14_15 0x1289F
#define mmVPMPCC_MCM1_VPMPCC_MCM_1DLUT_RAMA_REGION_14_15 0x1292F
#define mmVPMPCC_MCM0_VPMPCC_MCM_1DLUT_RAMA_REGION_16_17 0x128A0
#define mmVPMPCC_MCM1_VPMPCC_MCM_1DLUT_RAMA_REGION_16_17 0x12930
#define mmVPMPCC_MCM0_VPMPCC_MCM_1DLUT_RAMA_REGION_18_19 0x128A1
#define mmVPMPCC_MCM1_VPMPCC_MCM_1DLUT_RAMA_REGION_18_19 0x12931
#define mmVPMPCC_MCM0_VPMPCC_MCM_1DLUT_RAMA_REGION_20_21 0x128A2
#define mmVPMPCC_MCM1_VPMPCC_MCM_1DLUT_RAMA_REGION_20_21 0x12932
#define mmVPMPCC_MCM0_VPMPCC_MCM_1DLUT_RAMA_REGION_22_23 0x128A3
#define mmVPMPCC_MCM1_VPMPCC_MCM_1DLUT_RAMA_REGION_22_23 0x12933
#define mmVPMPCC_MCM0_VPMPCC_MCM_1DLUT_RAMA_REGION_24_25 0x128A4
#define mmVPMPCC_MCM1_VPMPCC_MCM_1DLUT_RAMA_REGION_24_25 0x12934
#define mmVPMPCC_MCM0_VPMPCC_MCM_1DLUT_RAMA_REGION_26_27 0x128A5
#define mmVPMPCC_MCM1_VPMPCC_MCM_1DLUT_RAMA_REGION_26_27 0x12935
#define mmVPMPCC_MCM0_VPMPCC_MCM_1DLUT_RAMA_REGION_28_29 0x128A6
#define mmVPMPCC_MCM1_VPMPCC_MCM_1DLUT_RAMA_REGION_28_29 0x12936
#define mmVPMPCC_MCM0_VPMPCC_MCM_1DLUT_RAMA_REGION_30_31 0x128A7
#define mmVPMPCC_MCM1_VPMPCC_MCM_1DLUT_RAMA_REGION_30_31 0x12937
#define mmVPMPCC_MCM0_VPMPCC_MCM_1DLUT_RAMA_REGION_32_33 0x128A8
#define mmVPMPCC_MCM1_VPMPCC_MCM_1DLUT_RAMA_REGION_32_33 0x12938
#define mmVPMPCC_MCM0_VPMPCC_MCM_FIRST_GAMUT_REMAP_COEF_FORMAT 0x128A9
#define mmVPMPCC_MCM1_VPMPCC_MCM_FIRST_GAMUT_REMAP_COEF_FORMAT 0x12939
#define mmVPMPCC_MCM0_VPMPCC_MCM_FIRST_GAMUT_REMAP_MODE 0x128AA
#define mmVPMPCC_MCM1_VPMPCC_MCM_FIRST_GAMUT_REMAP_MODE 0x1293A
#define mmVPMPCC_MCM0_VPMPC_MCM_FIRST_GAMUT_REMAP_C11_C12_SETA 0x128AB
#define mmVPMPCC_MCM1_VPMPC_MCM_FIRST_GAMUT_REMAP_C11_C12_SETA 0x1293B
#define mmVPMPCC_MCM0_VPMPC_MCM_FIRST_GAMUT_REMAP_C13_C14_SETA 0x128AC
#define mmVPMPCC_MCM1_VPMPC_MCM_FIRST_GAMUT_REMAP_C13_C14_SETA 0x1293C
#define mmVPMPCC_MCM0_VPMPC_MCM_FIRST_GAMUT_REMAP_C21_C22_SETA 0x128AD
#define mmVPMPCC_MCM1_VPMPC_MCM_FIRST_GAMUT_REMAP_C21_C22_SETA 0x1293D
#define mmVPMPCC_MCM0_VPMPC_MCM_FIRST_GAMUT_REMAP_C23_C24_SETA 0x128AE
#define mmVPMPCC_MCM1_VPMPC_MCM_FIRST_GAMUT_REMAP_C23_C24_SETA 0x1293E
#define mmVPMPCC_MCM0_VPMPC_MCM_FIRST_GAMUT_REMAP_C31_C32_SETA 0x128AF
#define mmVPMPCC_MCM1_VPMPC_MCM_FIRST_GAMUT_REMAP_C31_C32_SETA 0x1293F
#define mmVPMPCC_MCM0_VPMPC_MCM_FIRST_GAMUT_REMAP_C33_C34_SETA 0x128B0
#define mmVPMPCC_MCM1_VPMPC_MCM_FIRST_GAMUT_REMAP_C33_C34_SETA 0x12940
#define mmVPMPCC_MCM0_VPMPCC_MCM_SECOND_GAMUT_REMAP_COEF_FORMAT 0x128B1
#define mmVPMPCC_MCM1_VPMPCC_MCM_SECOND_GAMUT_REMAP_COEF_FORMAT 0x12941
#define mmVPMPCC_MCM0_VPMPCC_MCM_SECOND_GAMUT_REMAP_MODE 0x128B2
#define mmVPMPCC_MCM1_VPMPCC_MCM_SECOND_GAMUT_REMAP_MODE 0x12942
#define mmVPMPCC_MCM0_VPMPC_MCM_SECOND_GAMUT_REMAP_C11_C12_SETA 0x128B3
#define mmVPMPCC_MCM1_VPMPC_MCM_SECOND_GAMUT_REMAP_C11_C12_SETA 0x12943
#define mmVPMPCC_MCM0_VPMPC_MCM_SECOND_GAMUT_REMAP_C13_C14_SETA 0x128B4
#define mmVPMPCC_MCM1_VPMPC_MCM_SECOND_GAMUT_REMAP_C13_C14_SETA 0x12944
#define mmVPMPCC_MCM0_VPMPC_MCM_SECOND_GAMUT_REMAP_C21_C22_SETA 0x128B5
#define mmVPMPCC_MCM1_VPMPC_MCM_SECOND_GAMUT_REMAP_C21_C22_SETA 0x12945
#define mmVPMPCC_MCM0_VPMPC_MCM_SECOND_GAMUT_REMAP_C23_C24_SETA 0x128B6
#define mmVPMPCC_MCM1_VPMPC_MCM_SECOND_GAMUT_REMAP_C23_C24_SETA 0x12946
#define mmVPMPCC_MCM0_VPMPC_MCM_SECOND_GAMUT_REMAP_C31_C32_SETA 0x128B7
#define mmVPMPCC_MCM1_VPMPC_MCM_SECOND_GAMUT_REMAP_C31_C32_SETA 0x12947
#define mmVPMPCC_MCM0_VPMPC_MCM_SECOND_GAMUT_REMAP_C33_C34_SETA 0x128B8
#define mmVPMPCC_MCM1_VPMPC_MCM_SECOND_GAMUT_REMAP_C33_C34_SETA 0x12948
#define mmVPMPCC_MCM0_VPMPCC_MCM_MEM_PWR_CTRL 0x128B9
#define mmVPMPCC_MCM1_VPMPCC_MCM_MEM_PWR_CTRL 0x12949
// Registers from VPMPC_RMCM block
#define mmVPMPC_RMCM_SHAPER_CONTROL 0x126F0
#define mmVPMPC_RMCM_SHAPER_OFFSET_R 0x126F1
#define mmVPMPC_RMCM_SHAPER_OFFSET_G 0x126F2
#define mmVPMPC_RMCM_SHAPER_OFFSET_B 0x126F3
#define mmVPMPC_RMCM_SHAPER_SCALE_R 0x126F4
#define mmVPMPC_RMCM_SHAPER_SCALE_G_B 0x126F5
#define mmVPMPC_RMCM_SHAPER_LUT_INDEX 0x126F6
#define mmVPMPC_RMCM_SHAPER_LUT_DATA 0x126F7
#define mmVPMPC_RMCM_SHAPER_LUT_WRITE_EN_MASK 0x126F8
#define mmVPMPC_RMCM_SHAPER_RAMA_START_CNTL_B 0x126F9
#define mmVPMPC_RMCM_SHAPER_RAMA_START_CNTL_G 0x126FA
#define mmVPMPC_RMCM_SHAPER_RAMA_START_CNTL_R 0x126FB
#define mmVPMPC_RMCM_SHAPER_RAMA_END_CNTL_B 0x126FC
#define mmVPMPC_RMCM_SHAPER_RAMA_END_CNTL_G 0x126FD
#define mmVPMPC_RMCM_SHAPER_RAMA_END_CNTL_R 0x126FE
#define mmVPMPC_RMCM_SHAPER_RAMA_REGION_0_1 0x126FF
#define mmVPMPC_RMCM_SHAPER_RAMA_REGION_2_3 0x12700
#define mmVPMPC_RMCM_SHAPER_RAMA_REGION_4_5 0x12701
#define mmVPMPC_RMCM_SHAPER_RAMA_REGION_6_7 0x12702
#define mmVPMPC_RMCM_SHAPER_RAMA_REGION_8_9 0x12703
#define mmVPMPC_RMCM_SHAPER_RAMA_REGION_10_11 0x12704
#define mmVPMPC_RMCM_SHAPER_RAMA_REGION_12_13 0x12705
#define mmVPMPC_RMCM_SHAPER_RAMA_REGION_14_15 0x12706
#define mmVPMPC_RMCM_SHAPER_RAMA_REGION_16_17 0x12707
#define mmVPMPC_RMCM_SHAPER_RAMA_REGION_18_19 0x12708
#define mmVPMPC_RMCM_SHAPER_RAMA_REGION_20_21 0x12709
#define mmVPMPC_RMCM_SHAPER_RAMA_REGION_22_23 0x1270A
#define mmVPMPC_RMCM_SHAPER_RAMA_REGION_24_25 0x1270B
#define mmVPMPC_RMCM_SHAPER_RAMA_REGION_26_27 0x1270C
#define mmVPMPC_RMCM_SHAPER_RAMA_REGION_28_29 0x1270D
#define mmVPMPC_RMCM_SHAPER_RAMA_REGION_30_31 0x1270E
#define mmVPMPC_RMCM_SHAPER_RAMA_REGION_32_33 0x1270F
#define mmVPMPC_RMCM_3DLUT_MODE 0x12710
#define mmVPMPC_RMCM_3DLUT_INDEX 0x12711
#define mmVPMPC_RMCM_3DLUT_DATA 0x12712
#define mmVPMPC_RMCM_3DLUT_DATA_30BIT 0x12713
#define mmVPMPC_RMCM_3DLUT_READ_WRITE_CONTROL 0x12714
#define mmVPMPC_RMCM_3DLUT_OUT_NORM_FACTOR 0x12715
#define mmVPMPC_RMCM_3DLUT_OUT_OFFSET_R 0x12716
#define mmVPMPC_RMCM_3DLUT_OUT_OFFSET_G 0x12717
#define mmVPMPC_RMCM_3DLUT_OUT_OFFSET_B 0x12718
#define mmVPMPC_RMCM_GAMUT_REMAP_COEF_FORMAT 0x12719
#define mmVPMPC_RMCM_GAMUT_REMAP_MODE 0x1271A
#define mmVPMPC_RMCM_GAMUT_REMAP_C11_C12_SETA 0x1271B
#define mmVPMPC_RMCM_GAMUT_REMAP_C13_C14_SETA 0x1271C
#define mmVPMPC_RMCM_GAMUT_REMAP_C21_C22_SETA 0x1271D
#define mmVPMPC_RMCM_GAMUT_REMAP_C23_C24_SETA 0x1271E
#define mmVPMPC_RMCM_GAMUT_REMAP_C31_C32_SETA 0x1271F
#define mmVPMPC_RMCM_GAMUT_REMAP_C33_C34_SETA 0x12720
#define mmVPMPC_RMCM_MEM_PWR_CTRL 0x12721
#define mmVPMPC_RMCM_3DLUT_FAST_LOAD_SELECT 0x12722
#define mmVPMPC_RMCM_CNTL 0x12724
// Registers from VPFMT block
#define mmVPFMT0_VPFMT_CLAMP_COMPONENT_R 0x12AB0
#define mmVPFMT1_VPFMT_CLAMP_COMPONENT_R 0x12AF3
#define mmVPFMT0_VPFMT_CLAMP_COMPONENT_G 0x12AB1
#define mmVPFMT1_VPFMT_CLAMP_COMPONENT_G 0x12AF4
#define mmVPFMT0_VPFMT_CLAMP_COMPONENT_B 0x12AB2
#define mmVPFMT1_VPFMT_CLAMP_COMPONENT_B 0x12AF5
#define mmVPFMT0_VPFMT_DYNAMIC_EXP_CNTL 0x12AB3
#define mmVPFMT1_VPFMT_DYNAMIC_EXP_CNTL 0x12AF6
#define mmVPFMT0_VPFMT_CONTROL 0x12AB4
#define mmVPFMT1_VPFMT_CONTROL 0x12AF7
#define mmVPFMT0_VPFMT_BIT_DEPTH_CONTROL 0x12AB5
#define mmVPFMT1_VPFMT_BIT_DEPTH_CONTROL 0x12AF8
#define mmVPFMT0_VPFMT_DITHER_RAND_R_SEED 0x12AB6
#define mmVPFMT1_VPFMT_DITHER_RAND_R_SEED 0x12AF9
#define mmVPFMT0_VPFMT_DITHER_RAND_G_SEED 0x12AB7
#define mmVPFMT1_VPFMT_DITHER_RAND_G_SEED 0x12AFA
#define mmVPFMT0_VPFMT_DITHER_RAND_B_SEED 0x12AB8
#define mmVPFMT1_VPFMT_DITHER_RAND_B_SEED 0x12AFB
#define mmVPFMT0_VPFMT_CLAMP_CNTL 0x12AB9
#define mmVPFMT1_VPFMT_CLAMP_CNTL 0x12AFC
#define mmVPFMT0_VPFMT_SUBSAMPLER_MEMORY_CONTROL 0x12ABA
#define mmVPFMT1_VPFMT_SUBSAMPLER_MEMORY_CONTROL 0x12AFD
// Registers from VPOPP_PIPE block
#define mmVPOPP_PIPE0_VPOPP_PIPE_CONTROL 0x12AD8
#define mmVPOPP_PIPE1_VPOPP_PIPE_CONTROL 0x12B1B
#define mmVPOPP_PIPE0_VPOPP_PIPE_OUTBG_EXT1 0x12AD9
#define mmVPOPP_PIPE1_VPOPP_PIPE_OUTBG_EXT1 0x12B1C
#define mmVPOPP_PIPE0_VPOPP_PIPE_OUTBG_EXT2 0x12ADA
#define mmVPOPP_PIPE1_VPOPP_PIPE_OUTBG_EXT2 0x12B1D
#define mmVPOPP_PIPE0_VPOPP_PIPE_OUTBG_COL1 0x12ADB
#define mmVPOPP_PIPE1_VPOPP_PIPE_OUTBG_COL1 0x12B1E
#define mmVPOPP_PIPE0_VPOPP_PIPE_OUTBG_COL2 0x12ADC
#define mmVPOPP_PIPE1_VPOPP_PIPE_OUTBG_COL2 0x12B1F
// Registers from VPOPP_TOP block
#define mmVPOPP_TOP_CLK_CONTROL 0x12BC2
#define mmVPOPP_CRC_CONTROL 0x12BC4
#define mmVPOPP_CRC_RESULT_RG 0x12BC5
#define mmVPOPP_CRC_RESULT_BC 0x12BC6
#define mmVPOPP_FROD_CONTROL 0x12BC7
#define mmVPOPP_FROD_MEM_PWR_CONTROL 0x12BC8
#endif

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/* Copyright 2025 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors: AMD
*
*/
#pragma once
#include "resource.h"
#ifdef __cplusplus
extern "C" {
#endif
enum vpe_status vpe22_construct_resource(struct vpe_priv *vpe_priv, struct resource *res);
const struct vpe_caps *vpe22_get_capability(void);
struct cdc_fe *vpe22_cdc_fe_create(struct vpe_priv *vpe_priv, int inst);
struct cdc_be *vpe22_cdc_be_create(struct vpe_priv *vpe_priv, int inst);
struct dpp *vpe22_dpp_create(struct vpe_priv *vpe_priv, int inst);
struct opp *vpe22_opp_create(struct vpe_priv *vpe_priv, int inst);
struct mpc *vpe22_mpc_create(struct vpe_priv *vpe_priv, int inst);
void vpe22_setup_check_funcs(struct vpe_check_support_funcs *funcs);
bool vpe22_check_input_format(enum vpe_surface_pixel_format format);
#ifdef __cplusplus
}
#endif

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/* Copyright 2025 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors: AMD
*
*/
#include <string.h>
#include "vpe_priv.h"
#include "common.h"
#include "vpe20_cmd_builder.h"
#include "vpe20_vpe_desc_writer.h"
#include "vpe20_plane_desc_writer.h"
#include "vpe20_config_writer.h"
#include "vpe20_resource.h"
#include "vpe22_resource.h"
#include "vpe10_resource.h"
#include "vpe10_vpec.h"
#include "vpe10_cdc_fe.h"
#include "vpe10_cdc_be.h"
#include "vpe20_cdc_fe.h"
#include "vpe20_cdc_be.h"
#include "vpe10_dpp.h"
#include "vpe20_dpp.h"
#include "vpe10_mpc.h"
#include "vpe20_mpc.h"
#include "vpe10_opp.h"
#include "vpe20_opp.h"
#include "vpe10_background.h"
#include "vpe22/inc/asic/chip_offset.h"
#include "vpe22/inc/asic/chip_mask.h"
#include "vpe22/inc/asic/chip_shift.h"
#include "vpe22/inc/asic/chip_default.h"
#include "custom_fp16.h"
#include "custom_float.h"
#include "background.h"
#include "vpe_visual_confirm.h"
#include "vpe_spl_translation.h"
#include "SPL/dc_spl.h"
#define LUT_NUM_ENTRIES (17 * 17 * 17)
#define LUT_ENTRY_SIZE (2)
#define LUT_NUM_COMPONENT (3)
#define LUT_BUFFER_SIZE (LUT_NUM_ENTRIES * LUT_ENTRY_SIZE * LUT_NUM_COMPONENT)
#define LUT_FL_SIZE_17X17X17 (4916)
#define LUT_FL_SIZE_33X33X33 (35940)
#define BYTES_PER_ENTRY (4)
#define SHAPER_LUT_CHANNELS (3)
#define SHAPER_LUT_DATA_POINTS_PER_CHANNEL (256)
#define SHAPER_LUT_CONFIG_ENTRIES (28)
#define SHAPER_LUT_DMA_DATA_SIZE \
(SHAPER_LUT_DATA_POINTS_PER_CHANNEL * SHAPER_LUT_CHANNELS * BYTES_PER_ENTRY)
#define SHAPER_LUT_DMA_CONFIG_SIZE \
(SHAPER_LUT_CONFIG_ENTRIES * (BYTES_PER_ENTRY + SHAPER_LUT_DMA_CONFIG_PADDING))
#define SHAPER_LUT_DMA_DATA_ALIGNMENT (64)
#define SHAPER_LUT_DMA_CONFIG_ALIGNMENT (64)
#define SHAPER_LUT_DMA_CONFIG_PADDING (60)
#define LUT_3D_DMA_ALIGNMENT (256)
#define VPE_DESTINATION_AS_INPUT_STREAM_INDEX 0xff
// set field/register/bitfield name
#define SFRB(field_name, reg_name, post_fix) .field_name = reg_name##__##field_name##post_fix
// #ifdef SOC_BRINGUP
#define SRIDFVL(reg_name, block, id) \
.reg_name = {mm##block##id##_##reg_name, mm##block##id##_##reg_name##_##DEFAULT, \
mm##block##id##_##reg_name##_##DEFAULT, false}
#define SRIDFVL1(reg_name) \
.reg_name = {mm##reg_name, mm##reg_name##_##DEFAULT, mm##reg_name##_##DEFAULT, false}
#define SRIDFVL2(reg_name, block, id) \
.block##_##reg_name = {mm##block##id##_##reg_name, mm##block##id##_##reg_name##_##DEFAULT, \
mm##block##id##_##reg_name##_##DEFAULT, false}
#define SRIDFVL3(reg_name, block, id) \
.block##_##reg_name = {mm##block##_##reg_name, mm##block##_##reg_name##_##DEFAULT, \
mm##block##_##reg_name##_##DEFAULT, false}
#define SRIDFVL_CDC(reg_name, block, id) \
.block##0##_##reg_name = {mm##block##id##_##reg_name, mm##block##id##_##reg_name##_##DEFAULT, \
mm##block##id##_##reg_name##_##DEFAULT, false}
/***************** CDC FE registers ****************/
#define cdc_fe_regs(id) [id] = {CDC_FE_REG_LIST_VPE20(id)}
static struct vpe20_cdc_fe_registers cdc_fe_regs[] = {cdc_fe_regs(0), cdc_fe_regs(1)};
static const struct vpe20_cdc_fe_shift cdc_fe_shift = {CDC_FE_FIELD_LIST_VPE20(__SHIFT)};
static const struct vpe20_cdc_fe_mask cdc_fe_mask = {CDC_FE_FIELD_LIST_VPE20(_MASK)};
/***************** CDC BE registers ****************/
#define cdc_be_regs(id) [id] = {CDC_BE_REG_LIST_VPE20(id)}
static struct vpe20_cdc_be_registers cdc_be_regs[] = {
cdc_be_regs(0), cdc_be_regs(1), cdc_be_regs(2), cdc_be_regs(3)};
static const struct vpe20_cdc_be_shift cdc_be_shift = {CDC_BE_FIELD_LIST_VPE20(__SHIFT)};
static const struct vpe20_cdc_be_mask cdc_be_mask = {CDC_BE_FIELD_LIST_VPE20(_MASK)};
/***************** DPP registers ****************/
#define dpp_regs(id) [id] = {DPP_REG_LIST_VPE20(id)}
static struct vpe20_dpp_registers dpp_regs[] = {dpp_regs(0), dpp_regs(1)};
static const struct vpe20_dpp_shift dpp_shift = {DPP_FIELD_LIST_VPE20(__SHIFT)};
static const struct vpe20_dpp_mask dpp_mask = {DPP_FIELD_LIST_VPE20(_MASK)};
/***************** OPP registers ****************/
#define opp_regs(id) [id] = {OPP_REG_LIST_VPE20(id)}
static struct vpe20_opp_registers opp_regs[] = {opp_regs(0), opp_regs(1)};
static const struct vpe20_opp_shift opp_shift = {OPP_FIELD_LIST_VPE20(__SHIFT)};
static const struct vpe20_opp_mask opp_mask = {OPP_FIELD_LIST_VPE20(_MASK)};
/***************** MPC registers ****************/
#define mpc_regs(id) [id] = {MPC_REG_LIST_VPE20(id)}
static struct vpe20_mpc_registers mpc_regs[] = {mpc_regs(0), mpc_regs(1)};
static const struct vpe20_mpc_shift mpc_shift = {MPC_FIELD_LIST_VPE20(__SHIFT)};
static const struct vpe20_mpc_mask mpc_mask = {MPC_FIELD_LIST_VPE20(_MASK)};
static struct vpe_caps
caps =
{
.max_input_size =
{
.width = 16384,
.height = 16384,
},
.max_output_size =
{
.width = 16384,
.height = 16384,
},
.min_input_size =
{
.width = 1,
.height = 1,
},
.min_output_size =
{
.width = 1,
.height = 1,
},
.lut_size = LUT_BUFFER_SIZE,
.rotation_support = 1,
.h_mirror_support = 1,
.v_mirror_support = 1,
.is_apu = 1,
.bg_color_check_support = 0,
.prefer_external_scaler_coef = 0,
.resource_caps =
{
.num_dpp = 2,
.num_opp = 2,
.num_mpc_3dlut = 1,
.num_queue = 8,
.num_cdc_be = 4,
},
.color_caps = {.dpp =
{
.pre_csc = 1,
.luma_key = 1,
.color_key = 1,
.dgam_ram = 0,
.post_csc = 1,
.gamma_corr = 1,
.hw_3dlut = 1,
.ogam_ram = 1, /**< programmable gam in output -> gamma_corr */
.ocsc = 0,
.dgam_rom_caps =
{
.srgb = 1,
.bt2020 = 1,
.gamma2_2 = 1,
.pq = 1,
.hlg = 1,
},
},
.mpc =
{
.gamut_remap = 1,
.ogam_ram = 1,
.ocsc = 1,
.shared_3d_lut = 1,
.global_alpha = 1,
.top_bottom_blending = 1,
.dma_3d_lut = 1,
.yuv_linear_blend = 0,
.lut_dim_caps =
{
.dim_9 = 0,
.dim_17 = 1,
.dim_33 = 1,
},
.lut_caps =
{
.lut_shaper_caps =
{
.dma_data = 0,
.dma_config = 0,
.non_monotonic = 0,
.data_alignment = SHAPER_LUT_DMA_DATA_ALIGNMENT,
.config_alignment = SHAPER_LUT_DMA_CONFIG_ALIGNMENT,
.config_padding = SHAPER_LUT_DMA_CONFIG_PADDING,
.data_size = SHAPER_LUT_DMA_DATA_SIZE,
.config_size = SHAPER_LUT_DMA_CONFIG_SIZE,
.data_pts_per_channel = SHAPER_LUT_DATA_POINTS_PER_CHANNEL,
},
.lut_3dlut_caps =
{
.data_dim_9 = 0,
.data_dim_17 = 1,
.data_dim_33 = 1,
.dma_dim_9 = 0,
.dma_dim_17 = 0,
.dma_dim_33 = 1,
.alignment = LUT_3D_DMA_ALIGNMENT,
},
.lut_3d_compound = 0,
},
}},
.plane_caps =
{
.per_pixel_alpha = 1,
.input_pixel_format_support =
{
.argb_packed_32b = 1,
.nv12 = 1,
.fp16 = 1,
.p010 = 1, /**< planar 4:2:0 10-bit */
.p016 = 1, /**< planar 4:2:0 16-bit */
.ayuv = 1, /**< packed 4:4:4 */
.yuy2 = 1, /**< packed 4:2:2 */
.y210 = 1, /**< packed 4:2:2 10-bit */
.y216 = 1, /**< packed 4:2:2 16-bit */
.p210 = 1, /**< planar 4:2:2 10-bit */
.p216 = 1, /**< planar 4:2:2 16-bit */
.rgb8_planar = 1, /**< planar RGB 8-bit */
.rgb16_planar = 1, /**< planar RGB 16-bit */
.yuv8_planar = 1, /**< planar YUV 16-bit */
.yuv16_planar = 1, /**< planar YUV 16-bit */
.fp16_planar = 1, /**< planar RGB 8-bit */
.rgbe = 1, /**< shared exponent R9G9B9E5 */
.rgb111110_fix = 0, /**< fixed R11G11B10 */
.rgb111110_float = 0, /**< float R11G11B10 */
},
.output_pixel_format_support =
{
.argb_packed_32b = 1,
.nv12 = 1,
.fp16 = 1,
.p010 = 1, /**< planar 4:2:0 10-bit */
.p016 = 1, /**< planar 4:2:0 16-bit */
.ayuv = 1, /**< packed 4:4:4 */
.yuy2 = 1, /**< packed 4:2:2 */
.y210 = 1, /**< packed 4:2:2 10-bit */
.y216 = 1, /**< packed 4:2:2 16-bit */
.p210 = 1, /**< planar 4:2:2 10-bit */
.p216 = 1, /**< planar 4:2:2 16-bit */
.rgb8_planar = 1, /**< planar RGB 8-bit */
.rgb16_planar = 1, /**< planar RGB 16-bit */
.yuv8_planar = 1, /**< planar YUV 16-bit */
.yuv16_planar = 1, /**< planar YUV 16-bit */
.fp16_planar = 1, /**< planar RGB 8-bit */
.rgbe = 0, /**< shared exponent R9G9B9E5 */
.rgb111110_fix = 0, /**< fixed R11G11B10 */
.rgb111110_float = 0, /**< float R11G11B10 */
},
.max_upscale_factor = 64000,
// limit to 4:1 downscaling ratio: 1000/4 = 250
.max_downscale_factor = 250,
.pitch_alignment = 256,
.addr_alignment = 256,
.max_viewport_width = 1024,
.max_viewport_width_64bpp = 540,
},
.isharp_caps =
{
.support = true,
.range =
{
.min = 0,
.max = 10,
.step = 1,
},
},
.easf_support = 1,
.input_dcc_support = 1,
.input_internal_dcc = 1,
.output_dcc_support = 0,
.output_internal_dcc = 0,
.histogram_support = 1,
.frod_support = 1,
.alpha_blending_support = 1,
.alpha_fill_caps =
{
.opaque = 1,
.bg_color = 1,
.destination = 0,
.source_stream = 0,
},
};
struct cdc_fe *vpe22_cdc_fe_create(struct vpe_priv *vpe_priv, int inst)
{
struct vpe20_cdc_fe *vpe_cdc_fe = vpe_zalloc(sizeof(struct vpe20_cdc_fe));
if (!vpe_cdc_fe)
return NULL;
vpe20_construct_cdc_fe(vpe_priv, &vpe_cdc_fe->base);
vpe_cdc_fe->base.inst = inst;
vpe_cdc_fe->regs = &cdc_fe_regs[inst];
vpe_cdc_fe->mask = &cdc_fe_mask;
vpe_cdc_fe->shift = &cdc_fe_shift;
return &vpe_cdc_fe->base;
}
struct cdc_be *vpe22_cdc_be_create(struct vpe_priv *vpe_priv, int inst)
{
struct vpe20_cdc_be *vpe_cdc_be = vpe_zalloc(sizeof(struct vpe20_cdc_be));
if (!vpe_cdc_be)
return NULL;
vpe20_construct_cdc_be(vpe_priv, &vpe_cdc_be->base);
vpe_cdc_be->base.inst = inst;
vpe_cdc_be->regs = &cdc_be_regs[inst];
vpe_cdc_be->mask = &cdc_be_mask;
vpe_cdc_be->shift = &cdc_be_shift;
return &vpe_cdc_be->base;
}
struct dpp *vpe22_dpp_create(struct vpe_priv *vpe_priv, int inst)
{
struct vpe20_dpp *vpe_dpp = vpe_zalloc(sizeof(struct vpe20_dpp));
if (!vpe_dpp)
return NULL;
vpe20_construct_dpp(vpe_priv, &vpe_dpp->base);
vpe_dpp->base.inst = inst;
vpe_dpp->regs = &dpp_regs[inst];
vpe_dpp->mask = &dpp_mask;
vpe_dpp->shift = &dpp_shift;
return &vpe_dpp->base;
}
struct opp *vpe22_opp_create(struct vpe_priv *vpe_priv, int inst)
{
struct vpe20_opp *vpe_opp = vpe_zalloc(sizeof(struct vpe20_opp));
if (!vpe_opp)
return NULL;
vpe20_construct_opp(vpe_priv, &vpe_opp->base);
vpe_opp->base.inst = inst;
vpe_opp->regs = &opp_regs[inst];
vpe_opp->mask = &opp_mask;
vpe_opp->shift = &opp_shift;
return &vpe_opp->base;
}
struct mpc *vpe22_mpc_create(struct vpe_priv *vpe_priv, int inst)
{
struct vpe20_mpc *vpe_mpc = vpe_zalloc(sizeof(struct vpe20_mpc));
if (!vpe_mpc)
return NULL;
vpe20_construct_mpc(vpe_priv, &vpe_mpc->base);
vpe_mpc->base.inst = inst;
vpe_mpc->regs = &mpc_regs[inst];
vpe_mpc->mask = &mpc_mask;
vpe_mpc->shift = &mpc_shift;
return &vpe_mpc->base;
}
enum vpe_status vpe22_construct_resource(struct vpe_priv *vpe_priv, struct resource *res)
{
struct vpe *vpe = &vpe_priv->pub;
uint32_t i;
vpe->caps = &caps;
vpe10_construct_vpec(vpe_priv, &res->vpec);
for (i = 0; i < vpe->caps->resource_caps.num_dpp; i++) { // num pipes = num dpp = num_mpc
res->cdc_fe[i] = vpe22_cdc_fe_create(vpe_priv, i);
if (res->cdc_fe[i] == NULL)
goto err;
res->dpp[i] = vpe22_dpp_create(vpe_priv, i);
if (res->dpp[i] == NULL)
goto err;
res->mpc[i] = vpe22_mpc_create(vpe_priv, i);
if (res->mpc[i] == NULL)
goto err;
}
for (i = 0; i < vpe->caps->resource_caps.num_cdc_be; i++) {
res->cdc_be[i] = vpe22_cdc_be_create(vpe_priv, i);
if (res->cdc_be[i] == NULL)
goto err;
}
for (i = 0; i < vpe->caps->resource_caps.num_opp; i++) { // num opp = num dpp
res->opp[i] = vpe22_opp_create(vpe_priv, i);
if (res->opp[i] == NULL)
goto err;
}
vpe20_construct_cmd_builder(vpe_priv, &res->cmd_builder);
vpe20_construct_vpe_desc_writer(&vpe_priv->vpe_desc_writer);
vpe20_construct_plane_desc_writer(&vpe_priv->plane_desc_writer);
vpe20_config_writer_init(&vpe_priv->config_writer);
vpe_priv->num_pipe = 2;
res->internal_hdr_normalization = 1;
// Many of the below will need VPE20 versions.
res->check_h_mirror_support = vpe20_check_h_mirror_support;
res->calculate_segments = vpe20_calculate_segments;
res->get_max_seg_width = vpe20_get_max_seg_width;
res->set_num_segments = vpe20_set_num_segments;
res->split_bg_gap = vpe10_split_bg_gap;
res->calculate_dst_viewport_and_active = vpe20_calculate_dst_viewport_and_active;
res->get_bg_stream_idx = vpe20_get_bg_stream_idx;
res->find_bg_gaps = vpe_find_bg_gaps;
res->create_bg_segments = vpe20_create_bg_segments;
res->populate_cmd_info = vpe20_populate_cmd_info;
res->program_frontend = vpe20_program_frontend;
res->program_backend = vpe20_program_backend;
res->get_bufs_req = vpe20_get_bufs_req;
res->check_bg_color_support = vpe20_check_bg_color_support;
res->bg_color_convert = vpe20_bg_color_convert;
res->check_mirror_rotation_support = vpe20_check_mirror_rotation_support;
res->update_blnd_gamma = vpe20_update_blnd_gamma;
res->update_output_gamma = vpe20_update_output_gamma;
res->validate_cached_param = vpe20_validate_cached_param;
res->fill_alpha_through_luma_cmd_info = vpe20_fill_alpha_through_luma_cmd_info;
res->fill_non_performance_mode_cmd_info = vpe20_fill_non_performance_mode_cmd_info;
res->fill_performance_mode_cmd_info = vpe20_fill_performance_mode_cmd_info;
res->fill_blending_cmd_info = vpe20_fill_blending_cmd_info;
res->get_num_pipes_available = vpe20_get_num_pipes_available;
res->set_frod_output_viewport = vpe20_set_frod_output_viewport;
res->check_alpha_fill_support = vpe10_check_alpha_fill_support;
res->reset_pipes = vpe20_reset_pipes;
res->populate_frod_param = vpe20_populate_frod_param;
res->set_lls_pref = vpe20_set_lls_pref;
res->program_fastload = vpe20_program_3dlut_fl;
res->calculate_shaper = vpe10_calculate_shaper;
res->check_lut3d_compound = vpe20_check_lut3d_compound;
res->set_dst_cmd_info_scaler = vpe20_set_dst_cmd_info_scaler;
res->update_opp_adjust_and_boundary = vpe20_update_opp_adjust_and_boundary;
return VPE_STATUS_OK;
err:
vpe20_destroy_resource(vpe_priv, res);
return VPE_STATUS_ERROR;
}
bool vpe22_check_input_format(enum vpe_surface_pixel_format format)
{
if (vpe_is_32bit_packed_rgb(format))
return true;
if (vpe_is_yuv420(format))
return true;
if (vpe_is_yuv422(format))
return true;
if (vpe_is_yuv444(format))
return true;
if (vpe_is_fp16(format))
return true;
if (vpe_is_rgb16(format))
return true;
if (format == VPE_SURFACE_PIXEL_FORMAT_GRPH_RGBE)
return true;
if (format == VPE_SURFACE_PIXEL_FORMAT_PLANAR_8bpc_RGB)
return true;
return false;
}
const struct vpe_caps *vpe22_get_capability(void)
{
return &caps;
}
void vpe22_setup_check_funcs(struct vpe_check_support_funcs *funcs)
{
funcs->check_input_format = vpe22_check_input_format;
funcs->check_output_format = vpe20_check_output_format;
funcs->check_input_color_space = vpe10_check_input_color_space;
funcs->check_output_color_space = vpe20_check_output_color_space;
funcs->get_dcc_compression_input_cap = vpe20_get_dcc_compression_input_cap;
funcs->get_dcc_compression_output_cap = vpe20_get_dcc_compression_output_cap;
}

4
src/amd/vpelib/src/core/color.c
View file

@ -285,6 +285,8 @@ static bool can_bypass_degamma(const struct stream_ctx *stream_ctx)
return true;
if (stream_ctx->geometric_scaling)
return true;
if (stream_ctx->stream.surface_info.format == VPE_SURFACE_PIXEL_FORMAT_GRPH_RGBE)
return true;
return false;
}
@ -1236,7 +1238,7 @@ enum vpe_status vpe_color_update_whitepoint(
stream->white_point_gain = vpe_fixpt_one;
}
if (is_fp16) {
if (is_fp16 || (stream->stream.surface_info.format == VPE_SURFACE_PIXEL_FORMAT_GRPH_RGBE)) {
stream->white_point_gain = vpe_fixpt_div_int(stream->white_point_gain, CCCS_NORM);
}

17
src/amd/vpelib/src/core/resource.c
View file

@ -34,6 +34,8 @@
#include "vpe20_resource.h"
#include "multi_pipe_segmentation.h"
#include "vpe22_resource.h"
static const struct vpe_debug_options debug_defaults = {
.flags = {0},
.cm_in_bypass = 0,
@ -101,6 +103,9 @@ enum vpe_ip_level vpe_resource_parse_ip_version(
case VPE_VERSION(7, 0, 0): // to be removed when caller switches to new convention
ip_level = VPE_IP_LEVEL_2_0;
break;
case VPE_VERSION(2, 2, 0):
ip_level = VPE_IP_LEVEL_2_2;
break;
default:
ip_level = VPE_IP_LEVEL_UNKNOWN;
break;
@ -123,6 +128,9 @@ enum vpe_status vpe_construct_resource(
case VPE_IP_LEVEL_2_0:
status = vpe20_construct_resource(vpe_priv, res);
break;
case VPE_IP_LEVEL_2_2:
status = vpe22_construct_resource(vpe_priv, res);
break;
default:
status = VPE_STATUS_NOT_SUPPORTED;
vpe_log("invalid ip level: %d", (int)level);
@ -149,6 +157,9 @@ void vpe_destroy_resource(struct vpe_priv *vpe_priv, struct resource *res)
case VPE_IP_LEVEL_2_0:
vpe20_destroy_resource(vpe_priv, res);
break;
case VPE_IP_LEVEL_2_2:
vpe20_destroy_resource(vpe_priv, res);
break;
default:
break;
}
@ -1012,6 +1023,9 @@ const struct vpe_caps *vpe_get_capability(enum vpe_ip_level ip_level)
case VPE_IP_LEVEL_2_0:
caps = vpe20_get_capability();
break;
case VPE_IP_LEVEL_2_2:
caps = vpe22_get_capability();
break;
default:
caps = NULL;
@ -1031,6 +1045,9 @@ void vpe_setup_check_funcs(struct vpe_check_support_funcs *funcs, enum vpe_ip_le
case VPE_IP_LEVEL_2_0:
vpe20_setup_check_funcs(funcs);
break;
case VPE_IP_LEVEL_2_2:
vpe22_setup_check_funcs(funcs);
break;
default:
break;
}