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ir3: Drop ir3_nir_lower_64b_intrinsics
Our 64-bit memory load/stores are already split to 32 bits by nir_lower_mem_access_bit_sizes. Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38688>
This commit is contained in:
Emma Anholt
Marge Bot
parent
f8901bddac
commit
997c500cc4
3 changed files with 0 additions and 160 deletions
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@ -1225,7 +1225,6 @@ ir3_nir_lower_variant(struct ir3_shader_variant *so,
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progress |= OPT(s, ir3_nir_lower_64b_global);
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progress |= OPT(s, ir3_nir_lower_64b_undef);
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progress |= OPT(s, nir_lower_int64);
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progress |= OPT(s, ir3_nir_lower_64b_intrinsics);
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progress |= OPT(s, nir_lower_64bit_phis);
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progress |= OPT(s, ir3_nir_opt_subgroups, so);
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@ -51,7 +51,6 @@ uint8_t ir3_nir_vectorize_filter(const nir_instr *instr, const void *data);
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/*
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* 64b related lowering:
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*/
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bool ir3_nir_lower_64b_intrinsics(nir_shader *shader);
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bool ir3_nir_lower_64b_undef(nir_shader *shader);
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bool ir3_nir_lower_64b_global(nir_shader *shader);
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bool ir3_nir_lower_64b_regs(nir_shader *shader);
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@ -9,164 +9,6 @@
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#include "nir_builder_opcodes.h"
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#include "nir_intrinsics.h"
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/*
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* Lowering for 64b intrinsics generated with OpenCL or with
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* VK_KHR_buffer_device_address. All our intrinsics from a hw
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* standpoint are 32b, so we just need to combine in zero for
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* the upper 32bits and let the other nir passes clean up the mess.
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*/
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static bool
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lower_64b_intrinsics_filter(const nir_instr *instr, const void *unused)
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{
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(void)unused;
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if (instr->type != nir_instr_type_intrinsic)
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return false;
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nir_intrinsic_instr *intr = nir_instr_as_intrinsic(instr);
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if (intr->intrinsic == nir_intrinsic_load_deref ||
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intr->intrinsic == nir_intrinsic_store_deref)
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return false;
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if (is_intrinsic_store(intr->intrinsic))
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return nir_src_bit_size(intr->src[0]) == 64;
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/* skip over ssbo atomics, we'll lower them later */
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if (intr->intrinsic == nir_intrinsic_ssbo_atomic ||
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intr->intrinsic == nir_intrinsic_ssbo_atomic_swap ||
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intr->intrinsic == nir_intrinsic_global_atomic ||
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intr->intrinsic == nir_intrinsic_global_atomic_swap)
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return false;
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if (nir_intrinsic_dest_components(intr) == 0)
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return false;
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return intr->def.bit_size == 64;
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}
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static nir_def *
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lower_64b_intrinsics(nir_builder *b, nir_instr *instr, void *unused)
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{
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(void)unused;
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nir_intrinsic_instr *intr = nir_instr_as_intrinsic(instr);
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/* We could be *slightly* more clever and, for ex, turn a 64b vec4
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* load into two 32b vec4 loads, rather than 4 32b vec2 loads.
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*/
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if (is_intrinsic_store(intr->intrinsic)) {
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unsigned offset_src_idx;
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switch (intr->intrinsic) {
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case nir_intrinsic_store_ssbo:
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case nir_intrinsic_store_global_ir3:
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case nir_intrinsic_store_per_view_output:
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offset_src_idx = 2;
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break;
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default:
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offset_src_idx = 1;
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}
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unsigned num_comp = nir_intrinsic_src_components(intr, 0);
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unsigned wrmask = nir_intrinsic_has_write_mask(intr) ?
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nir_intrinsic_write_mask(intr) : BITSET_MASK(num_comp);
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nir_def *val = intr->src[0].ssa;
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nir_def *off = intr->src[offset_src_idx].ssa;
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for (unsigned i = 0; i < num_comp; i++) {
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if (!(wrmask & BITFIELD_BIT(i)))
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continue;
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nir_def *c64 = nir_channel(b, val, i);
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nir_def *c32 = nir_unpack_64_2x32(b, c64);
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nir_intrinsic_instr *store =
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nir_instr_as_intrinsic(nir_instr_clone(b->shader, &intr->instr));
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store->num_components = 2;
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store->src[0] = nir_src_for_ssa(c32);
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store->src[offset_src_idx] = nir_src_for_ssa(off);
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if (nir_intrinsic_has_write_mask(intr))
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nir_intrinsic_set_write_mask(store, 0x3);
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nir_builder_instr_insert(b, &store->instr);
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off = nir_iadd_imm(b, off, 8);
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}
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return NIR_LOWER_INSTR_PROGRESS_REPLACE;
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}
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unsigned num_comp = nir_intrinsic_dest_components(intr);
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nir_def *def = &intr->def;
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def->bit_size = 32;
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/* load_kernel_input is handled specially, lowering to two 32b inputs:
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*/
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if (intr->intrinsic == nir_intrinsic_load_kernel_input) {
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assert(num_comp == 1);
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nir_def *offset = nir_iadd_imm(b,
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intr->src[0].ssa, 4);
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nir_def *upper = nir_load_kernel_input(b, 1, 32, offset);
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return nir_pack_64_2x32_split(b, def, upper);
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}
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nir_def *components[num_comp];
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if (is_intrinsic_load(intr->intrinsic)) {
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unsigned offset_src_idx;
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switch(intr->intrinsic) {
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case nir_intrinsic_load_ssbo:
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case nir_intrinsic_load_ubo:
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case nir_intrinsic_load_global_ir3:
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case nir_intrinsic_load_per_view_output:
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offset_src_idx = 1;
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break;
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default:
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offset_src_idx = 0;
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}
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nir_def *off = intr->src[offset_src_idx].ssa;
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for (unsigned i = 0; i < num_comp; i++) {
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nir_intrinsic_instr *load =
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nir_instr_as_intrinsic(nir_instr_clone(b->shader, &intr->instr));
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load->num_components = 2;
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load->src[offset_src_idx] = nir_src_for_ssa(off);
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nir_def_init(&load->instr, &load->def, 2, 32);
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nir_builder_instr_insert(b, &load->instr);
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components[i] = nir_pack_64_2x32(b, &load->def);
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off = nir_iadd_imm(b, off, 8);
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}
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} else {
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/* The remaining (non load/store) intrinsics just get zero-
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* extended from 32b to 64b:
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*/
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for (unsigned i = 0; i < num_comp; i++) {
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nir_def *c = nir_channel(b, def, i);
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components[i] = nir_pack_64_2x32_split(b, c, nir_imm_zero(b, 1, 32));
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}
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}
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return nir_build_alu_src_arr(b, nir_op_vec(num_comp), components);
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}
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bool
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ir3_nir_lower_64b_intrinsics(nir_shader *shader)
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{
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return nir_shader_lower_instructions(
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shader, lower_64b_intrinsics_filter,
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lower_64b_intrinsics, NULL);
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}
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/*
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* Lowering for 64b undef instructions, splitting into a two 32b undefs
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*/
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