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radeonsi: (User) SGPR related cleanups.

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Use the same user SGPRs for the same purpose in vertex and pixel shaders.

Better calculation of the number of SGPRs to reserve.
This commit is contained in:
Michel Dänzer 2012-04-19 11:41:48 +02:00 • committed by Michel Dänzer
parent de12c6cb54
commit 9918fbd026
3 changed files with 33 additions and 16 deletions
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30
src/gallium/drivers/radeonsi/evergreen_state.c
View file

@ -1927,6 +1927,7 @@ void si_pipe_shader_ps(struct pipe_context *ctx, struct si_pipe_shader *shader)
struct r600_pipe_state *rstate = &shader->rstate;
struct r600_shader *rshader = &shader->shader;
unsigned i, exports_ps, num_cout, spi_ps_in_control, db_shader_control;
unsigned num_sgprs, num_user_sgprs;
int pos_index = -1, face_index = -1;
int ninterp = 0;
boolean have_linear = FALSE, have_centroid = FALSE, have_perspective = FALSE;
@ -2028,16 +2029,22 @@ void si_pipe_shader_ps(struct pipe_context *ctx, struct si_pipe_shader *shader)
va >> 40,
shader->bo, RADEON_USAGE_READ);
num_user_sgprs = 6;
num_sgprs = shader->num_sgprs;
if (num_user_sgprs > num_sgprs)
num_sgprs = num_user_sgprs;
/* Last 2 reserved SGPRs are used for VCC */
/* XXX: Hard-coding 2 SGPRs for constant buffer */
num_sgprs += 2;
assert(num_sgprs <= 104);
r600_pipe_state_add_reg(rstate,
R_00B028_SPI_SHADER_PGM_RSRC1_PS,
S_00B028_VGPRS(shader->num_vgprs / 4) |
S_00B028_SGPRS((shader->num_sgprs + 2 + 2 + 1) / 8),
S_00B028_VGPRS((shader->num_vgprs - 1) / 4) |
S_00B028_SGPRS((num_sgprs - 1) / 8),
NULL, 0);
r600_pipe_state_add_reg(rstate,
R_00B02C_SPI_SHADER_PGM_RSRC2_PS,
S_00B02C_USER_SGPR(6),
S_00B02C_USER_SGPR(num_user_sgprs),
NULL, 0);
r600_pipe_state_add_reg(rstate, R_02880C_DB_SHADER_CONTROL,
@ -2052,6 +2059,7 @@ void si_pipe_shader_vs(struct pipe_context *ctx, struct si_pipe_shader *shader)
struct r600_context *rctx = (struct r600_context *)ctx;
struct r600_pipe_state *rstate = &shader->rstate;
struct r600_shader *rshader = &shader->shader;
unsigned num_sgprs, num_user_sgprs;
unsigned nparams, i;
uint64_t va;
@ -2095,16 +2103,22 @@ void si_pipe_shader_vs(struct pipe_context *ctx, struct si_pipe_shader *shader)
va >> 40,
shader->bo, RADEON_USAGE_READ);
num_user_sgprs = 8;
num_sgprs = shader->num_sgprs;
if (num_user_sgprs > num_sgprs)
num_sgprs = num_user_sgprs;
/* Last 2 reserved SGPRs are used for VCC */
/* XXX: Hard-coding 2 SGPRs for constant buffer */
num_sgprs += 2;
assert(num_sgprs <= 104);
r600_pipe_state_add_reg(rstate,
R_00B128_SPI_SHADER_PGM_RSRC1_VS,
S_00B128_VGPRS(shader->num_vgprs / 4) |
S_00B128_SGPRS((shader->num_sgprs + 2 + 2 + 2) / 8),
S_00B128_VGPRS((shader->num_vgprs - 1) / 4) |
S_00B128_SGPRS((num_sgprs - 1) / 8),
NULL, 0);
r600_pipe_state_add_reg(rstate,
R_00B12C_SPI_SHADER_PGM_RSRC2_VS,
S_00B12C_USER_SGPR(2 + 2),
S_00B12C_USER_SGPR(num_user_sgprs),
NULL, 0);
}

8
src/gallium/drivers/radeonsi/r600_state_common.c
View file

@ -452,10 +452,10 @@ void r600_set_constant_buffer(struct pipe_context *ctx, uint shader, uint index,
rstate = &rctx->vs_const_buffer;
rstate->nregs = 0;
r600_pipe_state_add_reg(rstate,
R_00B138_SPI_SHADER_USER_DATA_VS_2,
R_00B130_SPI_SHADER_USER_DATA_VS_0,
va_offset, rbuffer, RADEON_USAGE_READ);
r600_pipe_state_add_reg(rstate,
R_00B13C_SPI_SHADER_USER_DATA_VS_3,
R_00B134_SPI_SHADER_USER_DATA_VS_1,
va_offset >> 32, NULL, 0);
break;
case PIPE_SHADER_FRAGMENT:
@ -638,10 +638,10 @@ static void r600_vertex_buffer_update(struct r600_context *rctx)
va = r600_resource_va(ctx->screen, (void*)t_list_buffer);
r600_pipe_state_add_reg(rstate,
R_00B130_SPI_SHADER_USER_DATA_VS_0,
R_00B148_SPI_SHADER_USER_DATA_VS_6,
va, t_list_buffer, RADEON_USAGE_READ);
r600_pipe_state_add_reg(rstate,
R_00B134_SPI_SHADER_USER_DATA_VS_1,
R_00B14C_SPI_SHADER_USER_DATA_VS_7,
va >> 32,
NULL, 0);

11
src/gallium/drivers/radeonsi/radeonsi_shader.c
View file

@ -138,9 +138,9 @@ static void declare_input_vs(
unsigned chan;
/* XXX: Communicate with the rest of the driver about which SGPR the T#
* list pointer is going to be stored in. Hard code to SGPR[0-1] for
* list pointer is going to be stored in. Hard code to SGPR[6:7] for
* now */
t_list_ptr = use_sgpr(base->gallivm, SGPR_I64, 0);
t_list_ptr = use_sgpr(base->gallivm, SGPR_I64, 3);
t_offset = lp_build_const_int32(base->gallivm,
4 * velem->vertex_buffer_index);
@ -188,6 +188,9 @@ static void declare_input_fs(
* [32:16] ParamOffset
*
*/
/* XXX: This register number must be identical to the S_00B02C_USER_SGPR
* register field value
*/
LLVMValueRef params = use_sgpr(base->gallivm, SGPR_I32, 6);
@ -256,8 +259,8 @@ static LLVMValueRef fetch_constant(
LLVMValueRef offset;
/* XXX: Assume the pointer to the constant buffer is being stored in
* SGPR[2:3] */
const_ptr = use_sgpr(base->gallivm, SGPR_I64, 1);
* SGPR[0:1] */
const_ptr = use_sgpr(base->gallivm, SGPR_I64, 0);
/* XXX: This assumes that the constant buffer is not packed, so
* CONST[0].x will have an offset of 0 and CONST[1].x will have an