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i965: drop brw->is_g4x in favor of devinfo->is_g4x

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Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
This commit is contained in:
Lionel Landwerlin 2017-08-30 09:09:13 +01:00
parent 46213f676e
commit 990c24ad85
8 changed files with 10 additions and 12 deletions
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2
src/mesa/drivers/dri/i965/brw_blorp.c
View file

@ -74,7 +74,7 @@ brw_blorp_init(struct brw_context *brw)
switch (devinfo->gen) {
case 4:
if (brw->is_g4x) {
if (devinfo->is_g4x) {
brw->blorp.exec = gen45_blorp_exec;
} else {
brw->blorp.exec = gen4_blorp_exec;

3
src/mesa/drivers/dri/i965/brw_context.c
View file

@ -528,7 +528,7 @@ brw_initialize_context_constants(struct brw_context *brw)
ctx->Const.MaxPointSizeAA = 255.0;
ctx->Const.PointSizeGranularity = 1.0;
if (devinfo->gen >= 5 || brw->is_g4x)
if (devinfo->gen >= 5 || devinfo->is_g4x)
ctx->Const.MaxClipPlanes = 8;
ctx->Const.GLSLTessLevelsAsInputs = true;
@ -858,7 +858,6 @@ brwCreateContext(gl_api api,
brw->screen = screen;
brw->bufmgr = screen->bufmgr;
brw->is_g4x = devinfo->is_g4x;
brw->is_baytrail = devinfo->is_baytrail;
brw->is_haswell = devinfo->is_haswell;
brw->is_cherryview = devinfo->is_cherryview;

1
src/mesa/drivers/dri/i965/brw_context.h
View file

@ -746,7 +746,6 @@ struct brw_context
uint64_t max_gtt_map_object_size;
bool is_g4x;
bool is_baytrail;
bool is_haswell;
bool is_cherryview;

2
src/mesa/drivers/dri/i965/brw_curbe.c
View file

@ -324,7 +324,7 @@ emit:
*
* BRW_NEW_FRAGMENT_PROGRAM
*/
if (devinfo->gen == 4 && !brw->is_g4x &&
if (devinfo->gen == 4 && !devinfo->is_g4x &&
(brw->fragment_program->info.inputs_read & (1 << VARYING_SLOT_POS))) {
BEGIN_BATCH(2);
OUT_BATCH(_3DSTATE_GLOBAL_DEPTH_OFFSET_CLAMP << 16 | (2 - 2));

8
src/mesa/drivers/dri/i965/brw_misc_state.c
View file

@ -375,7 +375,7 @@ brw_emit_depth_stencil_hiz(struct brw_context *brw,
assert(!separate_stencil);
const struct gen_device_info *devinfo = &brw->screen->devinfo;
const unsigned len = (brw->is_g4x || devinfo->gen == 5) ? 6 : 5;
const unsigned len = (devinfo->is_g4x || devinfo->gen == 5) ? 6 : 5;
BEGIN_BATCH(len);
OUT_BATCH(_3DSTATE_DEPTH_BUFFER << 16 | (len - 2));
@ -395,7 +395,7 @@ brw_emit_depth_stencil_hiz(struct brw_context *brw,
((height + tile_y - 1) << 19));
OUT_BATCH(0);
if (brw->is_g4x || devinfo->gen >= 5)
if (devinfo->is_g4x || devinfo->gen >= 5)
OUT_BATCH(tile_x | (tile_y << 16));
else
assert(tile_x == 0 && tile_y == 0);
@ -419,7 +419,7 @@ void
brw_emit_select_pipeline(struct brw_context *brw, enum brw_pipeline pipeline)
{
const struct gen_device_info *devinfo = &brw->screen->devinfo;
const bool is_965 = devinfo->gen == 4 && !brw->is_g4x;
const bool is_965 = devinfo->gen == 4 && !devinfo->is_g4x;
const uint32_t _3DSTATE_PIPELINE_SELECT =
is_965 ? CMD_PIPELINE_SELECT_965 : CMD_PIPELINE_SELECT_GM45;
@ -524,7 +524,7 @@ void
brw_upload_invariant_state(struct brw_context *brw)
{
const struct gen_device_info *devinfo = &brw->screen->devinfo;
const bool is_965 = devinfo->gen == 4 && !brw->is_g4x;
const bool is_965 = devinfo->gen == 4 && !devinfo->is_g4x;
brw_emit_select_pipeline(brw, BRW_RENDER_PIPELINE);
brw->last_pipeline = BRW_RENDER_PIPELINE;

2
src/mesa/drivers/dri/i965/brw_state_upload.c
View file

@ -188,7 +188,7 @@ void brw_init_state( struct brw_context *brw )
gen6_init_atoms(brw);
else if (devinfo->gen >= 5)
gen5_init_atoms(brw);
else if (brw->is_g4x)
else if (devinfo->is_g4x)
gen45_init_atoms(brw);
else
gen4_init_atoms(brw);

2
src/mesa/drivers/dri/i965/brw_urb.c
View file

@ -157,7 +157,7 @@ brw_calculate_urb_fence(struct brw_context *brw, unsigned csize,
brw->urb.nr_vs_entries = limits[VS].preferred_nr_entries;
brw->urb.nr_sf_entries = limits[SF].preferred_nr_entries;
}
} else if (brw->is_g4x) {
} else if (devinfo->is_g4x) {
brw->urb.nr_vs_entries = 64;
if (check_urb_layout(brw)) {
goto done;

2
src/mesa/drivers/dri/i965/intel_extensions.c
View file

@ -151,7 +151,7 @@ intelInitExtensions(struct gl_context *ctx)
ctx->Extensions.EXT_shader_integer_mix = ctx->Const.GLSLVersion >= 130;
ctx->Extensions.MESA_shader_integer_functions = ctx->Const.GLSLVersion >= 130;
if (brw->is_g4x || devinfo->gen >= 5) {
if (devinfo->is_g4x || devinfo->gen >= 5) {
ctx->Extensions.MESA_shader_framebuffer_fetch_non_coherent = true;
ctx->Extensions.KHR_blend_equation_advanced = true;
}