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intel/fs: add plumbing for embedded samplers

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We can address samplers from 3 different locations :
   - binding table
   - dynamic state base address
   - bindless sampler base address (only Gfx11+)

Here we allow samplers to be address from the dynamic state base
address with the embedded sampler flag.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Ivan Briano <ivan.briano@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22151>
This commit is contained in:
Lionel Landwerlin 2023-03-21 14:16:16 +02:00 • committed by Marge Bot
parent 3f25b2826f
commit 99047451c9
2 changed files with 31 additions and 7 deletions
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5
src/intel/compiler/brw_compiler.h
View file

@ -467,6 +467,8 @@ enum brw_param_builtin {
#define BRW_PARAM_BUILTIN_CLIP_PLANE_COMP(param) \ #define BRW_PARAM_BUILTIN_CLIP_PLANE_COMP(param) \
(((param) - BRW_PARAM_BUILTIN_CLIP_PLANE_0_X) & 0x3) (((param) - BRW_PARAM_BUILTIN_CLIP_PLANE_0_X) & 0x3)
#define BRW_MAX_EMBEDDED_SAMPLERS (4096)
enum brw_shader_reloc_id { enum brw_shader_reloc_id {
BRW_SHADER_RELOC_CONST_DATA_ADDR_LOW, BRW_SHADER_RELOC_CONST_DATA_ADDR_LOW,
BRW_SHADER_RELOC_CONST_DATA_ADDR_HIGH, BRW_SHADER_RELOC_CONST_DATA_ADDR_HIGH,
@ -474,6 +476,9 @@ enum brw_shader_reloc_id {
BRW_SHADER_RELOC_RESUME_SBT_ADDR_LOW, BRW_SHADER_RELOC_RESUME_SBT_ADDR_LOW,
BRW_SHADER_RELOC_RESUME_SBT_ADDR_HIGH, BRW_SHADER_RELOC_RESUME_SBT_ADDR_HIGH,
BRW_SHADER_RELOC_DESCRIPTORS_ADDR_HIGH, BRW_SHADER_RELOC_DESCRIPTORS_ADDR_HIGH,
BRW_SHADER_RELOC_EMBEDDED_SAMPLER_HANDLE,
BRW_SHADER_RELOC_LAST_EMBEDDED_SAMPLER_HANDLE =
BRW_SHADER_RELOC_EMBEDDED_SAMPLER_HANDLE + BRW_MAX_EMBEDDED_SAMPLERS - 1,
}; };
enum brw_shader_reloc_type { enum brw_shader_reloc_type {

23
src/intel/compiler/brw_fs_nir.cpp
View file

@ -4643,14 +4643,26 @@ try_rebuild_resource(nir_to_brw_state &ntb, const brw::fs_builder &bld, nir_def
} else { } else {
assert(def->parent_instr->type == nir_instr_type_intrinsic && assert(def->parent_instr->type == nir_instr_type_intrinsic &&
(nir_instr_as_intrinsic(def->parent_instr)->intrinsic == (nir_instr_as_intrinsic(def->parent_instr)->intrinsic ==
nir_intrinsic_load_uniform)); nir_intrinsic_load_uniform ||
nir_instr_as_intrinsic(def->parent_instr)->intrinsic ==
nir_intrinsic_load_reloc_const_intel));
nir_intrinsic_instr *intrin = nir_instr_as_intrinsic(def->parent_instr); nir_intrinsic_instr *intrin = nir_instr_as_intrinsic(def->parent_instr);
switch (intrin->intrinsic) {
case nir_intrinsic_load_uniform: {
unsigned base_offset = nir_intrinsic_base(intrin); unsigned base_offset = nir_intrinsic_base(intrin);
unsigned load_offset = nir_src_as_uint(intrin->src[0]); unsigned load_offset = nir_src_as_uint(intrin->src[0]);
fs_reg src(UNIFORM, base_offset / 4, BRW_REGISTER_TYPE_UD); fs_reg src(UNIFORM, base_offset / 4, BRW_REGISTER_TYPE_UD);
src.offset = load_offset + base_offset % 4; src.offset = load_offset + base_offset % 4;
return src; return src;
} }
default:
/* Execute the code below, since we have to generate new
* instructions.
*/
break;
}
}
} }
for (unsigned i = 0; i < resources.array.size(); i++) { for (unsigned i = 0; i < resources.array.size(); i++) {
@ -4759,6 +4771,14 @@ try_rebuild_resource(nir_to_brw_state &ntb, const brw::fs_builder &bld, nir_def
break; break;
} }
case nir_intrinsic_load_reloc_const_intel: {
uint32_t id = nir_intrinsic_param_idx(intrin);
fs_reg dst = ubld8.vgrf(BRW_REGISTER_TYPE_UD);
ntb.resource_insts[def->index] =
ubld8.emit(SHADER_OPCODE_MOV_RELOC_IMM, dst,
brw_imm_ud(id), brw_imm_ud(0));
}
default: default:
break; break;
} }
@ -8520,4 +8540,3 @@ nir_to_brw(fs_visitor *s)
ralloc_free(ntb.mem_ctx); ralloc_free(ntb.mem_ctx);
} }