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radv/meta: use BDA for copying VRS rates to HTILE
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33493>
This commit is contained in:
Samuel Pitoiset
Marge Bot
parent
e3cd101c17
commit
990244f7e2
3 changed files with 35 additions and 52 deletions
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@ -220,7 +220,7 @@ void radv_retile_dcc(struct radv_cmd_buffer *cmd_buffer, struct radv_image *imag
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void radv_expand_fmask_image_inplace(struct radv_cmd_buffer *cmd_buffer, struct radv_image *image,
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const VkImageSubresourceRange *subresourceRange);
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void radv_copy_vrs_htile(struct radv_cmd_buffer *cmd_buffer, struct radv_image_view *vrs_iview, const VkRect2D *rect,
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struct radv_image *dst_image, struct radv_buffer *htile_buffer, bool read_htile_value);
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struct radv_image *dst_image, uint64_t htile_va, bool read_htile_value);
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bool radv_can_use_fmask_copy(struct radv_cmd_buffer *cmd_buffer, const struct radv_image *src_image,
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const struct radv_image *dst_image, const struct radv_meta_blit2d_rect *rect);
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@ -22,20 +22,23 @@ build_copy_vrs_htile_shader(struct radv_device *device, struct radeon_surf *surf
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/* Get coordinates. */
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nir_def *global_id = get_global_ids(&b, 2);
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nir_def *offset = nir_load_push_constant(&b, 2, 32, nir_imm_int(&b, 0), .range = 8);
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nir_def *addr = nir_load_push_constant(&b, 2, 32, nir_imm_int(&b, 0), .range = 8);
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nir_def *htile_va = nir_pack_64_2x32(&b, nir_channels(&b, addr, 0x3));
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nir_def *offset = nir_load_push_constant(&b, 2, 32, nir_imm_int(&b, 8), .range = 16);
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/* Multiply the coordinates by the HTILE block size. */
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nir_def *coord = nir_iadd(&b, nir_imul_imm(&b, global_id, 8), offset);
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/* Load constants. */
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nir_def *constants = nir_load_push_constant(&b, 3, 32, nir_imm_int(&b, 8), .range = 20);
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nir_def *constants = nir_load_push_constant(&b, 3, 32, nir_imm_int(&b, 16), .range = 28);
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nir_def *htile_pitch = nir_channel(&b, constants, 0);
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nir_def *htile_slice_size = nir_channel(&b, constants, 1);
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nir_def *read_htile_value = nir_channel(&b, constants, 2);
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/* Get the HTILE addr from coordinates. */
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nir_def *zero = nir_imm_int(&b, 0);
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nir_def *htile_addr =
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nir_def *htile_offset =
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ac_nir_htile_addr_from_coord(&b, &pdev->info, &surf->u.gfx9.zs.htile_equation, htile_pitch, htile_slice_size,
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nir_channel(&b, coord, 0), nir_channel(&b, coord, 1), zero, zero);
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@ -63,16 +66,13 @@ build_copy_vrs_htile_shader(struct radv_device *device, struct radeon_surf *surf
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/* Compute the final VRS rate. */
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nir_def *vrs_rates = nir_ior(&b, nir_ishl_imm(&b, y_rate, 10), nir_ishl_imm(&b, x_rate, 6));
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/* Load the HTILE buffer descriptor. */
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nir_def *htile_buf = radv_meta_load_descriptor(&b, 0, 1);
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/* Load the HTILE value if requested, otherwise use the default value. */
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nir_variable *htile_value = nir_local_variable_create(b.impl, glsl_int_type(), "htile_value");
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nir_push_if(&b, nir_ieq_imm(&b, read_htile_value, 1));
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{
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/* Load the existing HTILE 32-bit value for this 8x8 pixels area. */
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nir_def *input_value = nir_load_ssbo(&b, 1, 32, htile_buf, htile_addr);
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nir_def *input_value = nir_build_load_global(&b, 1, 32, nir_iadd(&b, htile_va, nir_u2u64(&b, htile_offset)));
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/* Clear the 4-bit VRS rates. */
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nir_store_var(&b, htile_value, nir_iand_imm(&b, input_value, 0xfffff33f), 0x1);
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@ -87,7 +87,8 @@ build_copy_vrs_htile_shader(struct radv_device *device, struct radeon_surf *surf
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nir_def *output_value = nir_ior(&b, nir_load_var(&b, htile_value), vrs_rates);
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/* Store the updated HTILE 32-bit which contains the VRS rates. */
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nir_store_ssbo(&b, output_value, htile_buf, htile_addr, .access = ACCESS_NON_READABLE);
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nir_build_store_global(&b, output_value, nir_iadd(&b, htile_va, nir_u2u64(&b, htile_offset)),
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.access = ACCESS_NON_READABLE);
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return b.shader;
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}
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@ -106,24 +107,18 @@ get_pipeline(struct radv_device *device, struct radv_image *image, VkPipeline *p
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.descriptorCount = 1,
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.stageFlags = VK_SHADER_STAGE_COMPUTE_BIT,
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},
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{
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.binding = 1,
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.descriptorType = VK_DESCRIPTOR_TYPE_STORAGE_BUFFER,
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.descriptorCount = 1,
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.stageFlags = VK_SHADER_STAGE_COMPUTE_BIT,
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},
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};
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const VkDescriptorSetLayoutCreateInfo desc_info = {
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.sType = VK_STRUCTURE_TYPE_DESCRIPTOR_SET_LAYOUT_CREATE_INFO,
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.flags = VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT,
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.bindingCount = 2,
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.bindingCount = 1,
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.pBindings = bindings,
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};
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const VkPushConstantRange pc_range = {
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.stageFlags = VK_SHADER_STAGE_COMPUTE_BIT,
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.size = 20,
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.size = 28,
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};
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result = vk_meta_get_pipeline_layout(&device->vk, &device->meta_state.device, &desc_info, &pc_range, &key,
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@ -163,7 +158,7 @@ get_pipeline(struct radv_device *device, struct radv_image *image, VkPipeline *p
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void
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radv_copy_vrs_htile(struct radv_cmd_buffer *cmd_buffer, struct radv_image_view *vrs_iview, const VkRect2D *rect,
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struct radv_image *dst_image, struct radv_buffer *htile_buffer, bool read_htile_value)
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struct radv_image *dst_image, uint64_t htile_va, bool read_htile_value)
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{
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struct radv_device *device = radv_cmd_buffer_device(cmd_buffer);
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struct radv_meta_saved_state saved_state;
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@ -190,31 +185,23 @@ radv_copy_vrs_htile(struct radv_cmd_buffer *cmd_buffer, struct radv_image_view *
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radv_CmdBindPipeline(radv_cmd_buffer_to_handle(cmd_buffer), VK_PIPELINE_BIND_POINT_COMPUTE, pipeline);
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radv_meta_push_descriptor_set(
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cmd_buffer, VK_PIPELINE_BIND_POINT_COMPUTE, layout, 0, 2,
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(VkWriteDescriptorSet[]){{.sType = VK_STRUCTURE_TYPE_WRITE_DESCRIPTOR_SET,
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.dstBinding = 0,
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.dstArrayElement = 0,
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.descriptorCount = 1,
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.descriptorType = VK_DESCRIPTOR_TYPE_SAMPLED_IMAGE,
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.pImageInfo =
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(VkDescriptorImageInfo[]){
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{
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.sampler = VK_NULL_HANDLE,
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.imageView = radv_image_view_to_handle(vrs_iview),
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.imageLayout = VK_IMAGE_LAYOUT_GENERAL,
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},
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}},
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{.sType = VK_STRUCTURE_TYPE_WRITE_DESCRIPTOR_SET,
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.dstBinding = 1,
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.dstArrayElement = 0,
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.descriptorCount = 1,
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.descriptorType = VK_DESCRIPTOR_TYPE_STORAGE_BUFFER,
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.pBufferInfo = &(VkDescriptorBufferInfo){.buffer = radv_buffer_to_handle(htile_buffer),
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.offset = 0,
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.range = htile_buffer->vk.size}}});
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radv_meta_push_descriptor_set(cmd_buffer, VK_PIPELINE_BIND_POINT_COMPUTE, layout, 0, 1,
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(VkWriteDescriptorSet[]){{.sType = VK_STRUCTURE_TYPE_WRITE_DESCRIPTOR_SET,
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.dstBinding = 0,
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.dstArrayElement = 0,
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.descriptorCount = 1,
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.descriptorType = VK_DESCRIPTOR_TYPE_SAMPLED_IMAGE,
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.pImageInfo = (VkDescriptorImageInfo[]){
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{
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.sampler = VK_NULL_HANDLE,
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.imageView = radv_image_view_to_handle(vrs_iview),
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.imageLayout = VK_IMAGE_LAYOUT_GENERAL,
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},
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}}});
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const unsigned constants[5] = {
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const unsigned constants[7] = {
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htile_va,
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htile_va >> 32,
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rect->offset.x,
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rect->offset.y,
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dst_image->planes[0].surface.meta_pitch,
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@ -222,8 +209,8 @@ radv_copy_vrs_htile(struct radv_cmd_buffer *cmd_buffer, struct radv_image_view *
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read_htile_value,
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};
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vk_common_CmdPushConstants(radv_cmd_buffer_to_handle(cmd_buffer), layout, VK_SHADER_STAGE_COMPUTE_BIT, 0, 20,
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constants);
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vk_common_CmdPushConstants(radv_cmd_buffer_to_handle(cmd_buffer), layout, VK_SHADER_STAGE_COMPUTE_BIT, 0,
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sizeof(constants), constants);
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uint32_t width = DIV_ROUND_UP(rect->extent.width, 8);
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uint32_t height = DIV_ROUND_UP(rect->extent.height, 8);
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@ -9325,18 +9325,13 @@ radv_CmdBeginRendering(VkCommandBuffer commandBuffer, const VkRenderingInfo *pRe
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/* HTILE buffer */
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uint64_t htile_offset = ds_image->bindings[0].offset + ds_image->planes[0].surface.meta_offset +
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ds_image->planes[0].surface.u.gfx9.meta_levels[level].offset;
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uint64_t htile_size = ds_image->planes[0].surface.u.gfx9.meta_levels[level].size;
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struct radv_buffer htile_buffer;
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radv_buffer_init(&htile_buffer, device, ds_image->bindings[0].bo, htile_size, htile_offset);
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const uint64_t htile_va = radv_buffer_get_va(ds_image->bindings[0].bo) + htile_offset;
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assert(render->area.offset.x + render->area.extent.width <= ds_image->vk.extent.width &&
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render->area.offset.x + render->area.extent.height <= ds_image->vk.extent.height);
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/* Copy the VRS rates to the HTILE buffer. */
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radv_copy_vrs_htile(cmd_buffer, render->vrs_att.iview, &render->area, ds_image, &htile_buffer, true);
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radv_buffer_finish(&htile_buffer);
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radv_copy_vrs_htile(cmd_buffer, render->vrs_att.iview, &render->area, ds_image, htile_va, true);
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} else {
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/* When a subpass uses a VRS attachment without binding a depth/stencil attachment, or when
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* HTILE isn't enabled, we use a fallback that copies the VRS rates to our internal HTILE buffer.
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@ -9347,13 +9342,14 @@ radv_CmdBeginRendering(VkCommandBuffer commandBuffer, const VkRenderingInfo *pRe
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render->area.offset.y < ds_image->vk.extent.height) {
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/* HTILE buffer */
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struct radv_buffer *htile_buffer = device->vrs.buffer;
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const uint64_t htile_va = htile_buffer->addr;
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VkRect2D area = render->area;
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area.extent.width = MIN2(area.extent.width, ds_image->vk.extent.width - area.offset.x);
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area.extent.height = MIN2(area.extent.height, ds_image->vk.extent.height - area.offset.y);
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/* Copy the VRS rates to the HTILE buffer. */
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radv_copy_vrs_htile(cmd_buffer, render->vrs_att.iview, &area, ds_image, htile_buffer, false);
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radv_copy_vrs_htile(cmd_buffer, render->vrs_att.iview, &area, ds_image, htile_va, false);
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}
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}
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}
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