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radeon/llvm: Remove unused AMDIL TableGen definitons
This commit is contained in:
Tom Stellard
parent
34ff22b75f
commit
984ad0788c
18 changed files with 26 additions and 6140 deletions
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@ -56,7 +56,7 @@ namespace AMDGPUISD
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enum
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{
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AMDGPU_FIRST = AMDILISD::LAST_NON_MEMORY_OPCODE,
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AMDGPU_FIRST = AMDILISD::LAST_ISD_NUMBER,
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FRACT,
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FMAX,
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SMAX,
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@ -46,7 +46,6 @@ bool AMDGPU::isTransOp(unsigned opcode)
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case AMDIL::COS_r600:
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case AMDIL::COS_eg:
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case AMDIL::RSQ_f32:
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case AMDIL::MULLIT:
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case AMDIL::MUL_LIT_r600:
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case AMDIL::MUL_LIT_eg:
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@ -23,26 +23,10 @@ def RetCC_AMDIL32 : CallingConv<[
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// Integer and FP scalar values get put on the stack at 16-byte alignment
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// but with a size of 4 bytes
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CCIfType<[i1, i8, i16, i32, f32, f64, i64], CCAssignToReg<
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CCIfType<[i32, f32], CCAssignToReg<
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[
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R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, R13, R14, R15, R16, R17, R18, R19, R20, R21, R22, R23, R24, R25, R26, R27, R28, R29, R30, R31, R32, R33, R34, R35, R36, R37, R38, R39, R40, R41, R42, R43, R44, R45, R46, R47, R48, R49, R50, R51, R52, R53, R54, R55, R56, R57, R58, R59, R60, R61, R62, R63, R64, R65, R66, R67, R68, R69, R70, R71, R72, R73, R74, R75, R76, R77, R78, R79, R80, R81, R82, R83, R84, R85, R86, R87, R88, R89, R90, R91, R92, R93, R94, R95, R96, R97, R98, R99, R100, R101, R102, R103, R104, R105, R106, R107, R108, R109, R110, R111, R112, R113, R114, R115, R116, R117, R118, R119, R120, R121, R122, R123, R124, R125, R126, R127, R128, R129, R130, R131, R132, R133, R134, R135, R136, R137, R138, R139, R140, R141, R142, R143, R144, R145, R146, R147, R148, R149, R150, R151, R152, R153, R154, R155, R156, R157, R158, R159, R160, R161, R162, R163, R164, R165, R166, R167, R168, R169, R170, R171, R172, R173, R174, R175, R176, R177, R178, R179, R180, R181, R182, R183, R184, R185, R186, R187, R188, R189, R190, R191, R192, R193, R194, R195, R196, R197, R198, R199, R200, R201, R202, R203, R204, R205, R206, R207, R208, R209, R210, R211, R212, R213, R214, R215, R216, R217, R218, R219, R220, R221, R222, R223, R224, R225, R226, R227, R228, R229, R230, R231, R232, R233, R234, R235, R236, R237, R238, R239, R240, R241, R242, R243, R244, R245, R246, R247, R248, R249, R250, R251, R252, R253, R254, R255, R256, R257, R258, R259, R260, R261, R262, R263, R264, R265, R266, R267, R268, R269, R270, R271, R272, R273, R274, R275, R276, R277, R278, R279, R280, R281, R282, R283, R284, R285, R286, R287, R288, R289, R290, R291, R292, R293, R294, R295, R296, R297, R298, R299, R300, R301, R302, R303, R304, R305, R306, R307, R308, R309, R310, R311, R312, R313, R314, R315, R316, R317, R318, R319, R320, R321, R322, R323, R324, R325, R326, R327, R328, R329, R330, R331, R332, R333, R334, R335, R336, R337, R338, R339, R340, R341, R342, R343, R344, R345, R346, R347, R348, R349, R350, R351, R352, R353, R354, R355, R356, R357, R358, R359, R360, R361, R362, R363, R364, R365, R366, R367, R368, R369, R370, R371, R372, R373, R374, R375, R376, R377, R378, R379, R380, R381, R382, R383, R384, R385, R386, R387, R388, R389, R390, R391, R392, R393, R394, R395, R396, R397, R398, R399, R400, R401, R402, R403, R404, R405, R406, R407, R408, R409, R410, R411, R412, R413, R414, R415, R416, R417, R418, R419, R420, R421, R422, R423, R424, R425, R426, R427, R428, R429, R430, R431, R432, R433, R434, R435, R436, R437, R438, R439, R440, R441, R442, R443, R444, R445, R446, R447, R448, R449, R450, R451, R452, R453, R454, R455, R456, R457, R458, R459, R460, R461, R462, R463, R464, R465, R466, R467, R468, R469, R470, R471, R472, R473, R474, R475, R476, R477, R478, R479, R480, R481, R482, R483, R484, R485, R486, R487, R488, R489, R490, R491, R492, R493, R494, R495, R496, R497, R498, R499, R500, R501, R502, R503, R504, R505, R506, R507, R508, R509, R510, R511, R512, R513, R514, R515, R516, R517, R518, R519, R520, R521, R522, R523, R524, R525, R526, R527, R528, R529, R530, R531, R532, R533, R534, R535, R536, R537, R538, R539, R540, R541, R542, R543, R544, R545, R546, R547, R548, R549, R550, R551, R552, R553, R554, R555, R556, R557, R558, R559, R560, R561, R562, R563, R564, R565, R566, R567, R568, R569, R570, R571, R572, R573, R574, R575, R576, R577, R578, R579, R580, R581, R582, R583, R584, R585, R586, R587, R588, R589, R590, R591, R592, R593, R594, R595, R596, R597, R598, R599, R600, R601, R602, R603, R604, R605, R606, R607, R608, R609, R610, R611, R612, R613, R614, R615, R616, R617, R618, R619, R620, R621, R622, R623, R624, R625, R626, R627, R628, R629, R630, R631, R632, R633, R634, R635, R636, R637, R638, R639, R640, R641, R642, R643, R644, R645, R646, R647, R648, R649, R650, R651, R652, R653, R654, R655, R656, R657, R658, R659, R660, R661, R662, R663, R664, R665, R666, R667, R668, R669, R670, R671, R672, R673, R674, R675, R676, R677, R678, R679, R680, R681, R682, R683, R684, R685, R686, R687, R688, R689, R690, R691, R692, R693, R694, R695, R696, R697, R698, R699, R700, R701, R702, R703, R704, R705, R706, R707, R708, R709, R710, R711, R712, R713, R714, R715, R716, R717, R718, R719, R720, R721, R722, R723, R724, R725, R726, R727, R728, R729, R730, R731, R732, R733, R734, R735, R736, R737, R738, R739, R740, R741, R742, R743, R744, R745, R746, R747, R748, R749, R750, R751, R752, R753, R754, R755, R756, R757, R758, R759, R760, R761, R762, R763, R764, R765, R766, R767
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]> >,
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// 2-element Short vector types get 16 byte alignment and size of 8 bytes
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CCIfType<[v2i32, v2f32, v2i8, v4i8, v2i16, v4i16], CCAssignToReg<
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[R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, R13, R14, R15, R16, R17, R18, R19, R20, R21, R22, R23, R24, R25, R26, R27, R28, R29, R30, R31, R32, R33, R34, R35, R36, R37, R38, R39, R40, R41, R42, R43, R44, R45, R46, R47, R48, R49, R50, R51, R52, R53, R54, R55, R56, R57, R58, R59, R60, R61, R62, R63, R64, R65, R66, R67, R68, R69, R70, R71, R72, R73, R74, R75, R76, R77, R78, R79, R80, R81, R82, R83, R84, R85, R86, R87, R88, R89, R90, R91, R92, R93, R94, R95, R96, R97, R98, R99, R100, R101, R102, R103, R104, R105, R106, R107, R108, R109, R110, R111, R112, R113, R114, R115, R116, R117, R118, R119, R120, R121, R122, R123, R124, R125, R126, R127, R128, R129, R130, R131, R132, R133, R134, R135, R136, R137, R138, R139, R140, R141, R142, R143, R144, R145, R146, R147, R148, R149, R150, R151, R152, R153, R154, R155, R156, R157, R158, R159, R160, R161, R162, R163, R164, R165, R166, R167, R168, R169, R170, R171, R172, R173, R174, R175, R176, R177, R178, R179, R180, R181, R182, R183, R184, R185, R186, R187, R188, R189, R190, R191, R192, R193, R194, R195, R196, R197, R198, R199, R200, R201, R202, R203, R204, R205, R206, R207, R208, R209, R210, R211, R212, R213, R214, R215, R216, R217, R218, R219, R220, R221, R222, R223, R224, R225, R226, R227, R228, R229, R230, R231, R232, R233, R234, R235, R236, R237, R238, R239, R240, R241, R242, R243, R244, R245, R246, R247, R248, R249, R250, R251, R252, R253, R254, R255, R256, R257, R258, R259, R260, R261, R262, R263, R264, R265, R266, R267, R268, R269, R270, R271, R272, R273, R274, R275, R276, R277, R278, R279, R280, R281, R282, R283, R284, R285, R286, R287, R288, R289, R290, R291, R292, R293, R294, R295, R296, R297, R298, R299, R300, R301, R302, R303, R304, R305, R306, R307, R308, R309, R310, R311, R312, R313, R314, R315, R316, R317, R318, R319, R320, R321, R322, R323, R324, R325, R326, R327, R328, R329, R330, R331, R332, R333, R334, R335, R336, R337, R338, R339, R340, R341, R342, R343, R344, R345, R346, R347, R348, R349, R350, R351, R352, R353, R354, R355, R356, R357, R358, R359, R360, R361, R362, R363, R364, R365, R366, R367, R368, R369, R370, R371, R372, R373, R374, R375, R376, R377, R378, R379, R380, R381, R382, R383, R384, R385, R386, R387, R388, R389, R390, R391, R392, R393, R394, R395, R396, R397, R398, R399, R400, R401, R402, R403, R404, R405, R406, R407, R408, R409, R410, R411, R412, R413, R414, R415, R416, R417, R418, R419, R420, R421, R422, R423, R424, R425, R426, R427, R428, R429, R430, R431, R432, R433, R434, R435, R436, R437, R438, R439, R440, R441, R442, R443, R444, R445, R446, R447, R448, R449, R450, R451, R452, R453, R454, R455, R456, R457, R458, R459, R460, R461, R462, R463, R464, R465, R466, R467, R468, R469, R470, R471, R472, R473, R474, R475, R476, R477, R478, R479, R480, R481, R482, R483, R484, R485, R486, R487, R488, R489, R490, R491, R492, R493, R494, R495, R496, R497, R498, R499, R500, R501, R502, R503, R504, R505, R506, R507, R508, R509, R510, R511, R512, R513, R514, R515, R516, R517, R518, R519, R520, R521, R522, R523, R524, R525, R526, R527, R528, R529, R530, R531, R532, R533, R534, R535, R536, R537, R538, R539, R540, R541, R542, R543, R544, R545, R546, R547, R548, R549, R550, R551, R552, R553, R554, R555, R556, R557, R558, R559, R560, R561, R562, R563, R564, R565, R566, R567, R568, R569, R570, R571, R572, R573, R574, R575, R576, R577, R578, R579, R580, R581, R582, R583, R584, R585, R586, R587, R588, R589, R590, R591, R592, R593, R594, R595, R596, R597, R598, R599, R600, R601, R602, R603, R604, R605, R606, R607, R608, R609, R610, R611, R612, R613, R614, R615, R616, R617, R618, R619, R620, R621, R622, R623, R624, R625, R626, R627, R628, R629, R630, R631, R632, R633, R634, R635, R636, R637, R638, R639, R640, R641, R642, R643, R644, R645, R646, R647, R648, R649, R650, R651, R652, R653, R654, R655, R656, R657, R658, R659, R660, R661, R662, R663, R664, R665, R666, R667, R668, R669, R670, R671, R672, R673, R674, R675, R676, R677, R678, R679, R680, R681, R682, R683, R684, R685, R686, R687, R688, R689, R690, R691, R692, R693, R694, R695, R696, R697, R698, R699, R700, R701, R702, R703, R704, R705, R706, R707, R708, R709, R710, R711, R712, R713, R714, R715, R716, R717, R718, R719, R720, R721, R722, R723, R724, R725, R726, R727, R728, R729, R730, R731, R732, R733, R734, R735, R736, R737, R738, R739, R740, R741, R742, R743, R744, R745, R746, R747, R748, R749, R750, R751, R752, R753, R754, R755, R756, R757, R758, R759, R760, R761, R762, R763, R764, R765, R766, R767
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]> >,
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// 4-element Short vector types get 16 byte alignment and size of 16 bytes
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CCIfType<[v4i32, v4f32], CCAssignToReg<
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[R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, R13, R14, R15, R16, R17, R18, R19, R20, R21, R22, R23, R24, R25, R26, R27, R28, R29, R30, R31, R32, R33, R34, R35, R36, R37, R38, R39, R40, R41, R42, R43, R44, R45, R46, R47, R48, R49, R50, R51, R52, R53, R54, R55, R56, R57, R58, R59, R60, R61, R62, R63, R64, R65, R66, R67, R68, R69, R70, R71, R72, R73, R74, R75, R76, R77, R78, R79, R80, R81, R82, R83, R84, R85, R86, R87, R88, R89, R90, R91, R92, R93, R94, R95, R96, R97, R98, R99, R100, R101, R102, R103, R104, R105, R106, R107, R108, R109, R110, R111, R112, R113, R114, R115, R116, R117, R118, R119, R120, R121, R122, R123, R124, R125, R126, R127, R128, R129, R130, R131, R132, R133, R134, R135, R136, R137, R138, R139, R140, R141, R142, R143, R144, R145, R146, R147, R148, R149, R150, R151, R152, R153, R154, R155, R156, R157, R158, R159, R160, R161, R162, R163, R164, R165, R166, R167, R168, R169, R170, R171, R172, R173, R174, R175, R176, R177, R178, R179, R180, R181, R182, R183, R184, R185, R186, R187, R188, R189, R190, R191, R192, R193, R194, R195, R196, R197, R198, R199, R200, R201, R202, R203, R204, R205, R206, R207, R208, R209, R210, R211, R212, R213, R214, R215, R216, R217, R218, R219, R220, R221, R222, R223, R224, R225, R226, R227, R228, R229, R230, R231, R232, R233, R234, R235, R236, R237, R238, R239, R240, R241, R242, R243, R244, R245, R246, R247, R248, R249, R250, R251, R252, R253, R254, R255, R256, R257, R258, R259, R260, R261, R262, R263, R264, R265, R266, R267, R268, R269, R270, R271, R272, R273, R274, R275, R276, R277, R278, R279, R280, R281, R282, R283, R284, R285, R286, R287, R288, R289, R290, R291, R292, R293, R294, R295, R296, R297, R298, R299, R300, R301, R302, R303, R304, R305, R306, R307, R308, R309, R310, R311, R312, R313, R314, R315, R316, R317, R318, R319, R320, R321, R322, R323, R324, R325, R326, R327, R328, R329, R330, R331, R332, R333, R334, R335, R336, R337, R338, R339, R340, R341, R342, R343, R344, R345, R346, R347, R348, R349, R350, R351, R352, R353, R354, R355, R356, R357, R358, R359, R360, R361, R362, R363, R364, R365, R366, R367, R368, R369, R370, R371, R372, R373, R374, R375, R376, R377, R378, R379, R380, R381, R382, R383, R384, R385, R386, R387, R388, R389, R390, R391, R392, R393, R394, R395, R396, R397, R398, R399, R400, R401, R402, R403, R404, R405, R406, R407, R408, R409, R410, R411, R412, R413, R414, R415, R416, R417, R418, R419, R420, R421, R422, R423, R424, R425, R426, R427, R428, R429, R430, R431, R432, R433, R434, R435, R436, R437, R438, R439, R440, R441, R442, R443, R444, R445, R446, R447, R448, R449, R450, R451, R452, R453, R454, R455, R456, R457, R458, R459, R460, R461, R462, R463, R464, R465, R466, R467, R468, R469, R470, R471, R472, R473, R474, R475, R476, R477, R478, R479, R480, R481, R482, R483, R484, R485, R486, R487, R488, R489, R490, R491, R492, R493, R494, R495, R496, R497, R498, R499, R500, R501, R502, R503, R504, R505, R506, R507, R508, R509, R510, R511, R512, R513, R514, R515, R516, R517, R518, R519, R520, R521, R522, R523, R524, R525, R526, R527, R528, R529, R530, R531, R532, R533, R534, R535, R536, R537, R538, R539, R540, R541, R542, R543, R544, R545, R546, R547, R548, R549, R550, R551, R552, R553, R554, R555, R556, R557, R558, R559, R560, R561, R562, R563, R564, R565, R566, R567, R568, R569, R570, R571, R572, R573, R574, R575, R576, R577, R578, R579, R580, R581, R582, R583, R584, R585, R586, R587, R588, R589, R590, R591, R592, R593, R594, R595, R596, R597, R598, R599, R600, R601, R602, R603, R604, R605, R606, R607, R608, R609, R610, R611, R612, R613, R614, R615, R616, R617, R618, R619, R620, R621, R622, R623, R624, R625, R626, R627, R628, R629, R630, R631, R632, R633, R634, R635, R636, R637, R638, R639, R640, R641, R642, R643, R644, R645, R646, R647, R648, R649, R650, R651, R652, R653, R654, R655, R656, R657, R658, R659, R660, R661, R662, R663, R664, R665, R666, R667, R668, R669, R670, R671, R672, R673, R674, R675, R676, R677, R678, R679, R680, R681, R682, R683, R684, R685, R686, R687, R688, R689, R690, R691, R692, R693, R694, R695, R696, R697, R698, R699, R700, R701, R702, R703, R704, R705, R706, R707, R708, R709, R710, R711, R712, R713, R714, R715, R716, R717, R718, R719, R720, R721, R722, R723, R724, R725, R726, R727, R728, R729, R730, R731, R732, R733, R734, R735, R736, R737, R738, R739, R740, R741, R742, R743, R744, R745, R746, R747, R748, R749, R750, R751, R752, R753, R754, R755, R756, R757, R758, R759, R760, R761, R762, R763, R764, R765, R766, R767
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]> >,
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// 2-element 64-bit vector types get aligned to 16 bytes with a size of 16 bytes
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CCIfType<[v2f64, v2i64], CCAssignToReg<
|
||||
[R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, R13, R14, R15, R16, R17, R18, R19, R20, R21, R22, R23, R24, R25, R26, R27, R28, R29, R30, R31, R32, R33, R34, R35, R36, R37, R38, R39, R40, R41, R42, R43, R44, R45, R46, R47, R48, R49, R50, R51, R52, R53, R54, R55, R56, R57, R58, R59, R60, R61, R62, R63, R64, R65, R66, R67, R68, R69, R70, R71, R72, R73, R74, R75, R76, R77, R78, R79, R80, R81, R82, R83, R84, R85, R86, R87, R88, R89, R90, R91, R92, R93, R94, R95, R96, R97, R98, R99, R100, R101, R102, R103, R104, R105, R106, R107, R108, R109, R110, R111, R112, R113, R114, R115, R116, R117, R118, R119, R120, R121, R122, R123, R124, R125, R126, R127, R128, R129, R130, R131, R132, R133, R134, R135, R136, R137, R138, R139, R140, R141, R142, R143, R144, R145, R146, R147, R148, R149, R150, R151, R152, R153, R154, R155, R156, R157, R158, R159, R160, R161, R162, R163, R164, R165, R166, R167, R168, R169, R170, R171, R172, R173, R174, R175, R176, R177, R178, R179, R180, R181, R182, R183, R184, R185, R186, R187, R188, R189, R190, R191, R192, R193, R194, R195, R196, R197, R198, R199, R200, R201, R202, R203, R204, R205, R206, R207, R208, R209, R210, R211, R212, R213, R214, R215, R216, R217, R218, R219, R220, R221, R222, R223, R224, R225, R226, R227, R228, R229, R230, R231, R232, R233, R234, R235, R236, R237, R238, R239, R240, R241, R242, R243, R244, R245, R246, R247, R248, R249, R250, R251, R252, R253, R254, R255, R256, R257, R258, R259, R260, R261, R262, R263, R264, R265, R266, R267, R268, R269, R270, R271, R272, R273, R274, R275, R276, R277, R278, R279, R280, R281, R282, R283, R284, R285, R286, R287, R288, R289, R290, R291, R292, R293, R294, R295, R296, R297, R298, R299, R300, R301, R302, R303, R304, R305, R306, R307, R308, R309, R310, R311, R312, R313, R314, R315, R316, R317, R318, R319, R320, R321, R322, R323, R324, R325, R326, R327, R328, R329, R330, R331, R332, R333, R334, R335, R336, R337, R338, R339, R340, R341, R342, R343, R344, R345, R346, R347, R348, R349, R350, R351, R352, R353, R354, R355, R356, R357, R358, R359, R360, R361, R362, R363, R364, R365, R366, R367, R368, R369, R370, R371, R372, R373, R374, R375, R376, R377, R378, R379, R380, R381, R382, R383, R384, R385, R386, R387, R388, R389, R390, R391, R392, R393, R394, R395, R396, R397, R398, R399, R400, R401, R402, R403, R404, R405, R406, R407, R408, R409, R410, R411, R412, R413, R414, R415, R416, R417, R418, R419, R420, R421, R422, R423, R424, R425, R426, R427, R428, R429, R430, R431, R432, R433, R434, R435, R436, R437, R438, R439, R440, R441, R442, R443, R444, R445, R446, R447, R448, R449, R450, R451, R452, R453, R454, R455, R456, R457, R458, R459, R460, R461, R462, R463, R464, R465, R466, R467, R468, R469, R470, R471, R472, R473, R474, R475, R476, R477, R478, R479, R480, R481, R482, R483, R484, R485, R486, R487, R488, R489, R490, R491, R492, R493, R494, R495, R496, R497, R498, R499, R500, R501, R502, R503, R504, R505, R506, R507, R508, R509, R510, R511, R512, R513, R514, R515, R516, R517, R518, R519, R520, R521, R522, R523, R524, R525, R526, R527, R528, R529, R530, R531, R532, R533, R534, R535, R536, R537, R538, R539, R540, R541, R542, R543, R544, R545, R546, R547, R548, R549, R550, R551, R552, R553, R554, R555, R556, R557, R558, R559, R560, R561, R562, R563, R564, R565, R566, R567, R568, R569, R570, R571, R572, R573, R574, R575, R576, R577, R578, R579, R580, R581, R582, R583, R584, R585, R586, R587, R588, R589, R590, R591, R592, R593, R594, R595, R596, R597, R598, R599, R600, R601, R602, R603, R604, R605, R606, R607, R608, R609, R610, R611, R612, R613, R614, R615, R616, R617, R618, R619, R620, R621, R622, R623, R624, R625, R626, R627, R628, R629, R630, R631, R632, R633, R634, R635, R636, R637, R638, R639, R640, R641, R642, R643, R644, R645, R646, R647, R648, R649, R650, R651, R652, R653, R654, R655, R656, R657, R658, R659, R660, R661, R662, R663, R664, R665, R666, R667, R668, R669, R670, R671, R672, R673, R674, R675, R676, R677, R678, R679, R680, R681, R682, R683, R684, R685, R686, R687, R688, R689, R690, R691, R692, R693, R694, R695, R696, R697, R698, R699, R700, R701, R702, R703, R704, R705, R706, R707, R708, R709, R710, R711, R712, R713, R714, R715, R716, R717, R718, R719, R720, R721, R722, R723, R724, R725, R726, R727, R728, R729, R730, R731, R732, R733, R734, R735, R736, R737, R738, R739, R740, R741, R742, R743, R744, R745, R746, R747, R748, R749, R750, R751, R752, R753, R754, R755, R756, R757, R758, R759, R760, R761, R762, R763, R764, R765, R766, R767
|
||||
]> >, CCAssignToStack<16, 16>
|
||||
]>;
|
||||
R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, R13, R14, R15, R16, R17, R18, R19, R20
|
||||
]> >, CCAssignToStack<16, 16>]>;
|
||||
|
||||
// AMDIL 32-bit C Calling convention.
|
||||
def CC_AMDIL32 : CallingConv<[
|
||||
|
|
@ -53,23 +37,6 @@ def CC_AMDIL32 : CallingConv<[
|
|||
// but with a size of 4 bytes
|
||||
// Integer and FP scalar values get put on the stack at 16-byte alignment
|
||||
// but with a size of 4 bytes
|
||||
CCIfType<[i1, i8, i16, i32, f32, f64, i64], CCAssignToReg<
|
||||
[R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, R13, R14, R15, R16, R17, R18, R19, R20, R21, R22, R23, R24, R25, R26, R27, R28, R29, R30, R31, R32, R33, R34, R35, R36, R37, R38, R39, R40, R41, R42, R43, R44, R45, R46, R47, R48, R49, R50, R51, R52, R53, R54, R55, R56, R57, R58, R59, R60, R61, R62, R63, R64, R65, R66, R67, R68, R69, R70, R71, R72, R73, R74, R75, R76, R77, R78, R79, R80, R81, R82, R83, R84, R85, R86, R87, R88, R89, R90, R91, R92, R93, R94, R95, R96, R97, R98, R99, R100, R101, R102, R103, R104, R105, R106, R107, R108, R109, R110, R111, R112, R113, R114, R115, R116, R117, R118, R119, R120, R121, R122, R123, R124, R125, R126, R127, R128, R129, R130, R131, R132, R133, R134, R135, R136, R137, R138, R139, R140, R141, R142, R143, R144, R145, R146, R147, R148, R149, R150, R151, R152, R153, R154, R155, R156, R157, R158, R159, R160, R161, R162, R163, R164, R165, R166, R167, R168, R169, R170, R171, R172, R173, R174, R175, R176, R177, R178, R179, R180, R181, R182, R183, R184, R185, R186, R187, R188, R189, R190, R191, R192, R193, R194, R195, R196, R197, R198, R199, R200, R201, R202, R203, R204, R205, R206, R207, R208, R209, R210, R211, R212, R213, R214, R215, R216, R217, R218, R219, R220, R221, R222, R223, R224, R225, R226, R227, R228, R229, R230, R231, R232, R233, R234, R235, R236, R237, R238, R239, R240, R241, R242, R243, R244, R245, R246, R247, R248, R249, R250, R251, R252, R253, R254, R255, R256, R257, R258, R259, R260, R261, R262, R263, R264, R265, R266, R267, R268, R269, R270, R271, R272, R273, R274, R275, R276, R277, R278, R279, R280, R281, R282, R283, R284, R285, R286, R287, R288, R289, R290, R291, R292, R293, R294, R295, R296, R297, R298, R299, R300, R301, R302, R303, R304, R305, R306, R307, R308, R309, R310, R311, R312, R313, R314, R315, R316, R317, R318, R319, R320, R321, R322, R323, R324, R325, R326, R327, R328, R329, R330, R331, R332, R333, R334, R335, R336, R337, R338, R339, R340, R341, R342, R343, R344, R345, R346, R347, R348, R349, R350, R351, R352, R353, R354, R355, R356, R357, R358, R359, R360, R361, R362, R363, R364, R365, R366, R367, R368, R369, R370, R371, R372, R373, R374, R375, R376, R377, R378, R379, R380, R381, R382, R383, R384, R385, R386, R387, R388, R389, R390, R391, R392, R393, R394, R395, R396, R397, R398, R399, R400, R401, R402, R403, R404, R405, R406, R407, R408, R409, R410, R411, R412, R413, R414, R415, R416, R417, R418, R419, R420, R421, R422, R423, R424, R425, R426, R427, R428, R429, R430, R431, R432, R433, R434, R435, R436, R437, R438, R439, R440, R441, R442, R443, R444, R445, R446, R447, R448, R449, R450, R451, R452, R453, R454, R455, R456, R457, R458, R459, R460, R461, R462, R463, R464, R465, R466, R467, R468, R469, R470, R471, R472, R473, R474, R475, R476, R477, R478, R479, R480, R481, R482, R483, R484, R485, R486, R487, R488, R489, R490, R491, R492, R493, R494, R495, R496, R497, R498, R499, R500, R501, R502, R503, R504, R505, R506, R507, R508, R509, R510, R511, R512, R513, R514, R515, R516, R517, R518, R519, R520, R521, R522, R523, R524, R525, R526, R527, R528, R529, R530, R531, R532, R533, R534, R535, R536, R537, R538, R539, R540, R541, R542, R543, R544, R545, R546, R547, R548, R549, R550, R551, R552, R553, R554, R555, R556, R557, R558, R559, R560, R561, R562, R563, R564, R565, R566, R567, R568, R569, R570, R571, R572, R573, R574, R575, R576, R577, R578, R579, R580, R581, R582, R583, R584, R585, R586, R587, R588, R589, R590, R591, R592, R593, R594, R595, R596, R597, R598, R599, R600, R601, R602, R603, R604, R605, R606, R607, R608, R609, R610, R611, R612, R613, R614, R615, R616, R617, R618, R619, R620, R621, R622, R623, R624, R625, R626, R627, R628, R629, R630, R631, R632, R633, R634, R635, R636, R637, R638, R639, R640, R641, R642, R643, R644, R645, R646, R647, R648, R649, R650, R651, R652, R653, R654, R655, R656, R657, R658, R659, R660, R661, R662, R663, R664, R665, R666, R667, R668, R669, R670, R671, R672, R673, R674, R675, R676, R677, R678, R679, R680, R681, R682, R683, R684, R685, R686, R687, R688, R689, R690, R691, R692, R693, R694, R695, R696, R697, R698, R699, R700, R701, R702, R703, R704, R705, R706, R707, R708, R709, R710, R711, R712, R713, R714, R715, R716, R717, R718, R719, R720, R721, R722, R723, R724, R725, R726, R727, R728, R729, R730, R731, R732, R733, R734, R735, R736, R737, R738, R739, R740, R741, R742, R743, R744, R745, R746, R747, R748, R749, R750, R751, R752, R753, R754, R755, R756, R757, R758, R759, R760, R761, R762, R763, R764, R765, R766, R767
|
||||
]> >,
|
||||
|
||||
// 2-element Short vector types get 16 byte alignment and size of 8 bytes
|
||||
CCIfType<[v2i32, v2f32, v2i8, v4i8, v2i16, v4i16], CCAssignToReg<
|
||||
[R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, R13, R14, R15, R16, R17, R18, R19, R20, R21, R22, R23, R24, R25, R26, R27, R28, R29, R30, R31, R32, R33, R34, R35, R36, R37, R38, R39, R40, R41, R42, R43, R44, R45, R46, R47, R48, R49, R50, R51, R52, R53, R54, R55, R56, R57, R58, R59, R60, R61, R62, R63, R64, R65, R66, R67, R68, R69, R70, R71, R72, R73, R74, R75, R76, R77, R78, R79, R80, R81, R82, R83, R84, R85, R86, R87, R88, R89, R90, R91, R92, R93, R94, R95, R96, R97, R98, R99, R100, R101, R102, R103, R104, R105, R106, R107, R108, R109, R110, R111, R112, R113, R114, R115, R116, R117, R118, R119, R120, R121, R122, R123, R124, R125, R126, R127, R128, R129, R130, R131, R132, R133, R134, R135, R136, R137, R138, R139, R140, R141, R142, R143, R144, R145, R146, R147, R148, R149, R150, R151, R152, R153, R154, R155, R156, R157, R158, R159, R160, R161, R162, R163, R164, R165, R166, R167, R168, R169, R170, R171, R172, R173, R174, R175, R176, R177, R178, R179, R180, R181, R182, R183, R184, R185, R186, R187, R188, R189, R190, R191, R192, R193, R194, R195, R196, R197, R198, R199, R200, R201, R202, R203, R204, R205, R206, R207, R208, R209, R210, R211, R212, R213, R214, R215, R216, R217, R218, R219, R220, R221, R222, R223, R224, R225, R226, R227, R228, R229, R230, R231, R232, R233, R234, R235, R236, R237, R238, R239, R240, R241, R242, R243, R244, R245, R246, R247, R248, R249, R250, R251, R252, R253, R254, R255, R256, R257, R258, R259, R260, R261, R262, R263, R264, R265, R266, R267, R268, R269, R270, R271, R272, R273, R274, R275, R276, R277, R278, R279, R280, R281, R282, R283, R284, R285, R286, R287, R288, R289, R290, R291, R292, R293, R294, R295, R296, R297, R298, R299, R300, R301, R302, R303, R304, R305, R306, R307, R308, R309, R310, R311, R312, R313, R314, R315, R316, R317, R318, R319, R320, R321, R322, R323, R324, R325, R326, R327, R328, R329, R330, R331, R332, R333, R334, R335, R336, R337, R338, R339, R340, R341, R342, R343, R344, R345, R346, R347, R348, R349, R350, R351, R352, R353, R354, R355, R356, R357, R358, R359, R360, R361, R362, R363, R364, R365, R366, R367, R368, R369, R370, R371, R372, R373, R374, R375, R376, R377, R378, R379, R380, R381, R382, R383, R384, R385, R386, R387, R388, R389, R390, R391, R392, R393, R394, R395, R396, R397, R398, R399, R400, R401, R402, R403, R404, R405, R406, R407, R408, R409, R410, R411, R412, R413, R414, R415, R416, R417, R418, R419, R420, R421, R422, R423, R424, R425, R426, R427, R428, R429, R430, R431, R432, R433, R434, R435, R436, R437, R438, R439, R440, R441, R442, R443, R444, R445, R446, R447, R448, R449, R450, R451, R452, R453, R454, R455, R456, R457, R458, R459, R460, R461, R462, R463, R464, R465, R466, R467, R468, R469, R470, R471, R472, R473, R474, R475, R476, R477, R478, R479, R480, R481, R482, R483, R484, R485, R486, R487, R488, R489, R490, R491, R492, R493, R494, R495, R496, R497, R498, R499, R500, R501, R502, R503, R504, R505, R506, R507, R508, R509, R510, R511, R512, R513, R514, R515, R516, R517, R518, R519, R520, R521, R522, R523, R524, R525, R526, R527, R528, R529, R530, R531, R532, R533, R534, R535, R536, R537, R538, R539, R540, R541, R542, R543, R544, R545, R546, R547, R548, R549, R550, R551, R552, R553, R554, R555, R556, R557, R558, R559, R560, R561, R562, R563, R564, R565, R566, R567, R568, R569, R570, R571, R572, R573, R574, R575, R576, R577, R578, R579, R580, R581, R582, R583, R584, R585, R586, R587, R588, R589, R590, R591, R592, R593, R594, R595, R596, R597, R598, R599, R600, R601, R602, R603, R604, R605, R606, R607, R608, R609, R610, R611, R612, R613, R614, R615, R616, R617, R618, R619, R620, R621, R622, R623, R624, R625, R626, R627, R628, R629, R630, R631, R632, R633, R634, R635, R636, R637, R638, R639, R640, R641, R642, R643, R644, R645, R646, R647, R648, R649, R650, R651, R652, R653, R654, R655, R656, R657, R658, R659, R660, R661, R662, R663, R664, R665, R666, R667, R668, R669, R670, R671, R672, R673, R674, R675, R676, R677, R678, R679, R680, R681, R682, R683, R684, R685, R686, R687, R688, R689, R690, R691, R692, R693, R694, R695, R696, R697, R698, R699, R700, R701, R702, R703, R704, R705, R706, R707, R708, R709, R710, R711, R712, R713, R714, R715, R716, R717, R718, R719, R720, R721, R722, R723, R724, R725, R726, R727, R728, R729, R730, R731, R732, R733, R734, R735, R736, R737, R738, R739, R740, R741, R742, R743, R744, R745, R746, R747, R748, R749, R750, R751, R752, R753, R754, R755, R756, R757, R758, R759, R760, R761, R762, R763, R764, R765, R766, R767
|
||||
]> >,
|
||||
|
||||
// 4-element Short vector types get 16 byte alignment and size of 16 bytes
|
||||
CCIfType<[v4i32, v4f32], CCAssignToReg<
|
||||
[R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, R13, R14, R15, R16, R17, R18, R19, R20, R21, R22, R23, R24, R25, R26, R27, R28, R29, R30, R31, R32, R33, R34, R35, R36, R37, R38, R39, R40, R41, R42, R43, R44, R45, R46, R47, R48, R49, R50, R51, R52, R53, R54, R55, R56, R57, R58, R59, R60, R61, R62, R63, R64, R65, R66, R67, R68, R69, R70, R71, R72, R73, R74, R75, R76, R77, R78, R79, R80, R81, R82, R83, R84, R85, R86, R87, R88, R89, R90, R91, R92, R93, R94, R95, R96, R97, R98, R99, R100, R101, R102, R103, R104, R105, R106, R107, R108, R109, R110, R111, R112, R113, R114, R115, R116, R117, R118, R119, R120, R121, R122, R123, R124, R125, R126, R127, R128, R129, R130, R131, R132, R133, R134, R135, R136, R137, R138, R139, R140, R141, R142, R143, R144, R145, R146, R147, R148, R149, R150, R151, R152, R153, R154, R155, R156, R157, R158, R159, R160, R161, R162, R163, R164, R165, R166, R167, R168, R169, R170, R171, R172, R173, R174, R175, R176, R177, R178, R179, R180, R181, R182, R183, R184, R185, R186, R187, R188, R189, R190, R191, R192, R193, R194, R195, R196, R197, R198, R199, R200, R201, R202, R203, R204, R205, R206, R207, R208, R209, R210, R211, R212, R213, R214, R215, R216, R217, R218, R219, R220, R221, R222, R223, R224, R225, R226, R227, R228, R229, R230, R231, R232, R233, R234, R235, R236, R237, R238, R239, R240, R241, R242, R243, R244, R245, R246, R247, R248, R249, R250, R251, R252, R253, R254, R255, R256, R257, R258, R259, R260, R261, R262, R263, R264, R265, R266, R267, R268, R269, R270, R271, R272, R273, R274, R275, R276, R277, R278, R279, R280, R281, R282, R283, R284, R285, R286, R287, R288, R289, R290, R291, R292, R293, R294, R295, R296, R297, R298, R299, R300, R301, R302, R303, R304, R305, R306, R307, R308, R309, R310, R311, R312, R313, R314, R315, R316, R317, R318, R319, R320, R321, R322, R323, R324, R325, R326, R327, R328, R329, R330, R331, R332, R333, R334, R335, R336, R337, R338, R339, R340, R341, R342, R343, R344, R345, R346, R347, R348, R349, R350, R351, R352, R353, R354, R355, R356, R357, R358, R359, R360, R361, R362, R363, R364, R365, R366, R367, R368, R369, R370, R371, R372, R373, R374, R375, R376, R377, R378, R379, R380, R381, R382, R383, R384, R385, R386, R387, R388, R389, R390, R391, R392, R393, R394, R395, R396, R397, R398, R399, R400, R401, R402, R403, R404, R405, R406, R407, R408, R409, R410, R411, R412, R413, R414, R415, R416, R417, R418, R419, R420, R421, R422, R423, R424, R425, R426, R427, R428, R429, R430, R431, R432, R433, R434, R435, R436, R437, R438, R439, R440, R441, R442, R443, R444, R445, R446, R447, R448, R449, R450, R451, R452, R453, R454, R455, R456, R457, R458, R459, R460, R461, R462, R463, R464, R465, R466, R467, R468, R469, R470, R471, R472, R473, R474, R475, R476, R477, R478, R479, R480, R481, R482, R483, R484, R485, R486, R487, R488, R489, R490, R491, R492, R493, R494, R495, R496, R497, R498, R499, R500, R501, R502, R503, R504, R505, R506, R507, R508, R509, R510, R511, R512, R513, R514, R515, R516, R517, R518, R519, R520, R521, R522, R523, R524, R525, R526, R527, R528, R529, R530, R531, R532, R533, R534, R535, R536, R537, R538, R539, R540, R541, R542, R543, R544, R545, R546, R547, R548, R549, R550, R551, R552, R553, R554, R555, R556, R557, R558, R559, R560, R561, R562, R563, R564, R565, R566, R567, R568, R569, R570, R571, R572, R573, R574, R575, R576, R577, R578, R579, R580, R581, R582, R583, R584, R585, R586, R587, R588, R589, R590, R591, R592, R593, R594, R595, R596, R597, R598, R599, R600, R601, R602, R603, R604, R605, R606, R607, R608, R609, R610, R611, R612, R613, R614, R615, R616, R617, R618, R619, R620, R621, R622, R623, R624, R625, R626, R627, R628, R629, R630, R631, R632, R633, R634, R635, R636, R637, R638, R639, R640, R641, R642, R643, R644, R645, R646, R647, R648, R649, R650, R651, R652, R653, R654, R655, R656, R657, R658, R659, R660, R661, R662, R663, R664, R665, R666, R667, R668, R669, R670, R671, R672, R673, R674, R675, R676, R677, R678, R679, R680, R681, R682, R683, R684, R685, R686, R687, R688, R689, R690, R691, R692, R693, R694, R695, R696, R697, R698, R699, R700, R701, R702, R703, R704, R705, R706, R707, R708, R709, R710, R711, R712, R713, R714, R715, R716, R717, R718, R719, R720, R721, R722, R723, R724, R725, R726, R727, R728, R729, R730, R731, R732, R733, R734, R735, R736, R737, R738, R739, R740, R741, R742, R743, R744, R745, R746, R747, R748, R749, R750, R751, R752, R753, R754, R755, R756, R757, R758, R759, R760, R761, R762, R763, R764, R765, R766, R767
|
||||
]> >,
|
||||
|
||||
// 2-element 64-bit vector types get aligned to 16 bytes with a size of 16 bytes
|
||||
CCIfType<[v2f64, v2i64], CCAssignToReg<
|
||||
[R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, R13, R14, R15, R16, R17, R18, R19, R20, R21, R22, R23, R24, R25, R26, R27, R28, R29, R30, R31, R32, R33, R34, R35, R36, R37, R38, R39, R40, R41, R42, R43, R44, R45, R46, R47, R48, R49, R50, R51, R52, R53, R54, R55, R56, R57, R58, R59, R60, R61, R62, R63, R64, R65, R66, R67, R68, R69, R70, R71, R72, R73, R74, R75, R76, R77, R78, R79, R80, R81, R82, R83, R84, R85, R86, R87, R88, R89, R90, R91, R92, R93, R94, R95, R96, R97, R98, R99, R100, R101, R102, R103, R104, R105, R106, R107, R108, R109, R110, R111, R112, R113, R114, R115, R116, R117, R118, R119, R120, R121, R122, R123, R124, R125, R126, R127, R128, R129, R130, R131, R132, R133, R134, R135, R136, R137, R138, R139, R140, R141, R142, R143, R144, R145, R146, R147, R148, R149, R150, R151, R152, R153, R154, R155, R156, R157, R158, R159, R160, R161, R162, R163, R164, R165, R166, R167, R168, R169, R170, R171, R172, R173, R174, R175, R176, R177, R178, R179, R180, R181, R182, R183, R184, R185, R186, R187, R188, R189, R190, R191, R192, R193, R194, R195, R196, R197, R198, R199, R200, R201, R202, R203, R204, R205, R206, R207, R208, R209, R210, R211, R212, R213, R214, R215, R216, R217, R218, R219, R220, R221, R222, R223, R224, R225, R226, R227, R228, R229, R230, R231, R232, R233, R234, R235, R236, R237, R238, R239, R240, R241, R242, R243, R244, R245, R246, R247, R248, R249, R250, R251, R252, R253, R254, R255, R256, R257, R258, R259, R260, R261, R262, R263, R264, R265, R266, R267, R268, R269, R270, R271, R272, R273, R274, R275, R276, R277, R278, R279, R280, R281, R282, R283, R284, R285, R286, R287, R288, R289, R290, R291, R292, R293, R294, R295, R296, R297, R298, R299, R300, R301, R302, R303, R304, R305, R306, R307, R308, R309, R310, R311, R312, R313, R314, R315, R316, R317, R318, R319, R320, R321, R322, R323, R324, R325, R326, R327, R328, R329, R330, R331, R332, R333, R334, R335, R336, R337, R338, R339, R340, R341, R342, R343, R344, R345, R346, R347, R348, R349, R350, R351, R352, R353, R354, R355, R356, R357, R358, R359, R360, R361, R362, R363, R364, R365, R366, R367, R368, R369, R370, R371, R372, R373, R374, R375, R376, R377, R378, R379, R380, R381, R382, R383, R384, R385, R386, R387, R388, R389, R390, R391, R392, R393, R394, R395, R396, R397, R398, R399, R400, R401, R402, R403, R404, R405, R406, R407, R408, R409, R410, R411, R412, R413, R414, R415, R416, R417, R418, R419, R420, R421, R422, R423, R424, R425, R426, R427, R428, R429, R430, R431, R432, R433, R434, R435, R436, R437, R438, R439, R440, R441, R442, R443, R444, R445, R446, R447, R448, R449, R450, R451, R452, R453, R454, R455, R456, R457, R458, R459, R460, R461, R462, R463, R464, R465, R466, R467, R468, R469, R470, R471, R472, R473, R474, R475, R476, R477, R478, R479, R480, R481, R482, R483, R484, R485, R486, R487, R488, R489, R490, R491, R492, R493, R494, R495, R496, R497, R498, R499, R500, R501, R502, R503, R504, R505, R506, R507, R508, R509, R510, R511, R512, R513, R514, R515, R516, R517, R518, R519, R520, R521, R522, R523, R524, R525, R526, R527, R528, R529, R530, R531, R532, R533, R534, R535, R536, R537, R538, R539, R540, R541, R542, R543, R544, R545, R546, R547, R548, R549, R550, R551, R552, R553, R554, R555, R556, R557, R558, R559, R560, R561, R562, R563, R564, R565, R566, R567, R568, R569, R570, R571, R572, R573, R574, R575, R576, R577, R578, R579, R580, R581, R582, R583, R584, R585, R586, R587, R588, R589, R590, R591, R592, R593, R594, R595, R596, R597, R598, R599, R600, R601, R602, R603, R604, R605, R606, R607, R608, R609, R610, R611, R612, R613, R614, R615, R616, R617, R618, R619, R620, R621, R622, R623, R624, R625, R626, R627, R628, R629, R630, R631, R632, R633, R634, R635, R636, R637, R638, R639, R640, R641, R642, R643, R644, R645, R646, R647, R648, R649, R650, R651, R652, R653, R654, R655, R656, R657, R658, R659, R660, R661, R662, R663, R664, R665, R666, R667, R668, R669, R670, R671, R672, R673, R674, R675, R676, R677, R678, R679, R680, R681, R682, R683, R684, R685, R686, R687, R688, R689, R690, R691, R692, R693, R694, R695, R696, R697, R698, R699, R700, R701, R702, R703, R704, R705, R706, R707, R708, R709, R710, R711, R712, R713, R714, R715, R716, R717, R718, R719, R720, R721, R722, R723, R724, R725, R726, R727, R728, R729, R730, R731, R732, R733, R734, R735, R736, R737, R738, R739, R740, R741, R742, R743, R744, R745, R746, R747, R748, R749, R750, R751, R752, R753, R754, R755, R756, R757, R758, R759, R760, R761, R762, R763, R764, R765, R766, R767
|
||||
]> >, CCAssignToStack<16, 16>
|
||||
]>;
|
||||
|
||||
CCIfType<[i32, f32], CCAssignToReg<
|
||||
[R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, R13, R14, R15, R16, R17, R18, R19, R20
|
||||
]> >, CCAssignToStack<16, 16>]>;
|
||||
|
|
|
|||
|
|
@ -29,40 +29,6 @@ class ILFormat<ILOpCode op, dag outs, dag ins, string asmstr, list<dag> pattern>
|
|||
bit hasZeroOpFlag = 0;
|
||||
}
|
||||
|
||||
//===--------------------------------------------------------------------===//
|
||||
// The base class for vector insert instructions. It is a single dest, quad
|
||||
// source instruction where the last two source operands must be 32bit
|
||||
// immediate values that are encoding the swizzle of the source register
|
||||
// The src2 and src3 instructions must also be inversion of each other such
|
||||
// that if src2 is 0x1000300(x0z0), src3 must be 0x20004(0y0w). The values
|
||||
// are encoded as 32bit integer with each 8 char representing a swizzle value.
|
||||
// The encoding is as follows for 32bit register types:
|
||||
// 0x00 -> '_'
|
||||
// 0x01 -> 'x'
|
||||
// 0x02 -> 'y'
|
||||
// 0x03 -> 'z'
|
||||
// 0x04 -> 'w'
|
||||
// 0x05 -> 'x'
|
||||
// 0x06 -> 'y'
|
||||
// 0x07 -> 'z'
|
||||
// 0x08 -> 'w'
|
||||
// 0x09 -> '0'
|
||||
// The encoding is as follows for 64bit register types:
|
||||
// 0x00 -> "__"
|
||||
// 0x01 -> "xy"
|
||||
// 0x02 -> "zw"
|
||||
// 0x03 -> "xy"
|
||||
// 0x04 -> "zw"
|
||||
// 0x05 -> "00"
|
||||
//===--------------------------------------------------------------------===//
|
||||
class InsertVectorClass<ILOpCode op, RegisterClass DReg, RegisterClass SReg,
|
||||
SDNode OpNode, string asmstr> :
|
||||
ILFormat<op, (outs DReg:$dst),
|
||||
(ins DReg:$src0, SReg:$src1, i32imm:$src2, i32imm:$src3),
|
||||
!strconcat(asmstr, " $dst, $src0, $src1"),
|
||||
[(set DReg:$dst, (OpNode DReg:$src0, SReg:$src1,
|
||||
timm:$src2, timm:$src3))]>;
|
||||
|
||||
//===--------------------------------------------------------------------===//
|
||||
// Class that has one input parameters and one output parameter.
|
||||
// The basic pattern for this class is "Opcode Dst, Src0" and
|
||||
|
|
@ -86,18 +52,6 @@ class OneInOneOut<ILOpCode op, dag outs, dag ins,
|
|||
ILSrcMod src0_reg_rel_mod;
|
||||
}
|
||||
|
||||
//===--------------------------------------------------------------------===//
|
||||
// A simplified version of OneInOneOut class where the pattern is standard
|
||||
// and does not need special cases. This requires that the pattern has
|
||||
// a SDNode and takes a source and destination register that is of type
|
||||
// RegisterClass. This is the standard unary op class.
|
||||
//===--------------------------------------------------------------------===//
|
||||
class UnaryOp<ILOpCode op, SDNode OpNode,
|
||||
RegisterClass dRegs, RegisterClass sRegs>
|
||||
: OneInOneOut<op, (outs dRegs:$dst), (ins sRegs:$src),
|
||||
!strconcat(op.Text, " $dst, $src"),
|
||||
[(set dRegs:$dst, (OpNode sRegs:$src))]>;
|
||||
|
||||
//===--------------------------------------------------------------------===//
|
||||
// This class is similiar to the UnaryOp class, however, there is no
|
||||
// result value to assign.
|
||||
|
|
@ -130,39 +84,6 @@ class TwoInOneOut<ILOpCode op, dag outs, dag ins,
|
|||
ILSrc src1_reg_rel;
|
||||
ILSrcMod src1_reg_rel_mod;
|
||||
}
|
||||
//===--------------------------------------------------------------------===//
|
||||
// A simplification of the TwoInOneOut pattern for Binary Operations.
|
||||
// This class is a helper class that assumes the simple pattern of
|
||||
// $dst = op $src0 $src1.
|
||||
// Other type of matching patterns need to use the TwoInOneOut class.
|
||||
//===--------------------------------------------------------------------===//
|
||||
class BinaryOp<ILOpCode op, SDNode OpNode, RegisterClass dReg,
|
||||
RegisterClass sReg0, RegisterClass sReg1>
|
||||
: TwoInOneOut<op, (outs dReg:$dst), (ins sReg0:$src0, sReg1:$src1),
|
||||
!strconcat(op.Text, " $dst, $src0, $src1"),
|
||||
[(set dReg:$dst, (OpNode sReg0:$src0, sReg1:$src1))]>;
|
||||
|
||||
//===--------------------------------------------------------------------===//
|
||||
// The base class for vector extract instructions. The vector extract
|
||||
// instructions take as an input value a source register and a 32bit integer
|
||||
// with the same encoding as specified in InsertVectorClass and produces
|
||||
// a result with only the swizzled component in the destination register.
|
||||
//===--------------------------------------------------------------------===//
|
||||
class ExtractVectorClass<RegisterClass DReg, RegisterClass SReg, SDNode OpNode>
|
||||
: TwoInOneOut<IL_OP_MOV, (outs DReg:$dst), (ins SReg:$src0, i32imm:$src1),
|
||||
"mov $dst, $src0",
|
||||
[(set DReg:$dst, (OpNode SReg:$src0, timm:$src1))]>;
|
||||
|
||||
//===--------------------------------------------------------------------===//
|
||||
// The base class for vector concatenation. This class creates either a vec2
|
||||
// or a vec4 of 32bit data types or a vec2 of 64bit data types. This is done
|
||||
// by swizzling either the 'x' or 'xy' components of the source operands
|
||||
// into the destination register.
|
||||
//===--------------------------------------------------------------------===//
|
||||
class VectorConcatClass<RegisterClass Dst, RegisterClass Src, SDNode OpNode>
|
||||
: TwoInOneOut<IL_OP_I_ADD, (outs Dst:$dst), (ins Src:$src0, Src:$src1),
|
||||
"iadd $dst, $src0, $src1",
|
||||
[(set Dst:$dst, (OpNode Src:$src0, Src:$src1))]>;
|
||||
|
||||
//===--------------------------------------------------------------------===//
|
||||
// Similiar to the UnaryOpNoRet class, but takes as arguments two input
|
||||
|
|
@ -197,203 +118,6 @@ class ThreeInOneOut<ILOpCode op, dag outs, dag ins,
|
|||
ILSrcMod src2_reg_rel_mod;
|
||||
}
|
||||
|
||||
//===--------------------------------------------------------------------===//
|
||||
// The g version of the Three Input pattern uses a standard pattern but
|
||||
// but allows specification of the register to further generalize the class
|
||||
// This class is mainly used in the generic multiclasses in AMDILMultiClass.td
|
||||
//===--------------------------------------------------------------------===//
|
||||
class TernaryOp<ILOpCode op, SDNode OpNode,
|
||||
RegisterClass dReg,
|
||||
RegisterClass sReg0,
|
||||
RegisterClass sReg1,
|
||||
RegisterClass sReg2>
|
||||
: ThreeInOneOut<op, (outs dReg:$dst),
|
||||
(ins sReg0:$src0, sReg1:$src1, sReg2:$src2),
|
||||
!strconcat(op.Text, " $dst, $src0, $src1, $src2"),
|
||||
[(set dReg:$dst,
|
||||
(OpNode sReg0:$src0, sReg1:$src1, sReg2:$src2))]>;
|
||||
|
||||
//===--------------------------------------------------------------------===//
|
||||
// Set of classes that have three input parameters and one output parameter.
|
||||
// The basic pattern for this class is "Opcode Dst, Src0, Src1, Src2" and
|
||||
// handles the mad and conditional mov instruction.
|
||||
// It sets the binary token ILSrc, ILSrcMod, ILRelAddr and ILSrc and ILSrcMod
|
||||
// if the addressing is register relative.
|
||||
// This class is the parent class of TernaryOp
|
||||
//===--------------------------------------------------------------------===//
|
||||
class FourInOneOut<ILOpCode op, dag outs, dag ins,
|
||||
string asmstr, list<dag> pattern>
|
||||
: ThreeInOneOut<op, outs, ins, asmstr, pattern> {
|
||||
ILSrc src3_reg;
|
||||
ILSrcMod src3_mod;
|
||||
ILRelAddr src3_rel;
|
||||
ILSrc src3_reg_rel;
|
||||
ILSrcMod src3_reg_rel_mod;
|
||||
}
|
||||
|
||||
|
||||
//===--------------------------------------------------------------------===//
|
||||
// The macro class that is an extension of OneInOneOut but is tailored for
|
||||
// macros only where all the register types are the same
|
||||
//===--------------------------------------------------------------------===//
|
||||
class UnaryMacro<RegisterClass Dst, RegisterClass Src0, SDNode OpNode>
|
||||
: OneInOneOut<IL_OP_MACRO, (outs Dst:$dst),
|
||||
(ins Src0:$src0),
|
||||
"($dst),($src0)",
|
||||
[(set Dst:$dst, (OpNode Src0:$src0))]>;
|
||||
|
||||
//===--------------------------------------------------------------------===//
|
||||
// The macro class is an extension of TwoInOneOut but is tailored for
|
||||
// macros only where all the register types are the same
|
||||
//===--------------------------------------------------------------------===//
|
||||
class BinaryMacro<RegisterClass Dst,
|
||||
RegisterClass Src0,
|
||||
RegisterClass Src1,
|
||||
SDNode OpNode>
|
||||
: TwoInOneOut<IL_OP_MACRO, (outs Dst:$dst),
|
||||
(ins Src0: $src0, Src1:$src1),
|
||||
"($dst),($src0, $src1)",
|
||||
[(set Dst:$dst, (OpNode Src0:$src0, Src1:$src1))]>;
|
||||
|
||||
//===--------------------------------------------------------------------===//
|
||||
// Classes for dealing with atomic instructions w/ 32bit pointers
|
||||
//===--------------------------------------------------------------------===//
|
||||
class Append<ILOpCode op, string idType, SDNode intr>
|
||||
: ILFormat<op, (outs GPRI32:$dst),
|
||||
(ins MEMI32:$id),
|
||||
!strconcat(op.Text, !strconcat(idType," $dst")),
|
||||
[(set GPRI32:$dst, (intr ADDR:$id))]>;
|
||||
|
||||
|
||||
// TODO: Need to get this working without dst...
|
||||
class AppendNoRet<ILOpCode op, string idType, SDNode intr>
|
||||
: ILFormat<op, (outs GPRI32:$dst),
|
||||
(ins MEMI32:$id),
|
||||
!strconcat(op.Text, !strconcat(idType," $dst")),
|
||||
[(set GPRI32:$dst, (intr ADDR:$id))]>;
|
||||
|
||||
class UniAtom<ILOpCode op, string idType, SDNode intr>
|
||||
: ILFormat<op, (outs GPRI32:$dst),
|
||||
(ins MEMI32:$ptr, i32imm:$id),
|
||||
!strconcat(op.Text, !strconcat(idType," $dst, $ptr")),
|
||||
[(set GPRI32:$dst, (intr ADDR:$ptr, timm:$id))]>;
|
||||
|
||||
|
||||
// TODO: Need to get this working without dst...
|
||||
class UniAtomNoRet<ILOpCode op, string idType, SDNode intr>
|
||||
: ILFormat<op, (outs GPRI32:$dst), (ins MEMI32:$ptr, i32imm:$id),
|
||||
!strconcat(op.Text, !strconcat(idType," $ptr")),
|
||||
[(set GPRI32:$dst, (intr ADDR:$ptr, timm:$id))]>;
|
||||
|
||||
class BinAtom<ILOpCode op, string idType, SDNode intr>
|
||||
: ILFormat<op, (outs GPRI32:$dst),
|
||||
(ins MEMI32:$ptr, GPRI32:$src, i32imm:$id),
|
||||
!strconcat(op.Text, !strconcat(idType," $dst, $ptr, $src")),
|
||||
[(set GPRI32:$dst, (intr ADDR:$ptr, GPRI32:$src, timm:$id))]>;
|
||||
|
||||
|
||||
// TODO: Need to get this working without dst...
|
||||
class BinAtomNoRet<ILOpCode op, string idType, SDNode intr>
|
||||
: ILFormat<op, (outs GPRI32:$dst), (ins MEMI32:$ptr, GPRI32:$src, i32imm:$id),
|
||||
!strconcat(op.Text, !strconcat(idType," $ptr, $src")),
|
||||
[(set GPRI32:$dst, (intr ADDR:$ptr, GPRI32:$src, timm:$id))]>;
|
||||
|
||||
class TriAtom<ILOpCode op, string idType, SDNode intr>
|
||||
: ILFormat<op, (outs GPRI32:$dst),
|
||||
(ins MEMI32:$ptr, GPRI32:$src, GPRI32:$src1, i32imm:$id),
|
||||
!strconcat(op.Text, !strconcat(idType," $dst, $ptr, $src, $src1")),
|
||||
[(set GPRI32:$dst, (intr ADDR:$ptr, GPRI32:$src, GPRI32:$src1, timm:$id))]>;
|
||||
|
||||
class CmpXChg<ILOpCode op, string idType, SDNode intr>
|
||||
: ILFormat<op, (outs GPRI32:$dst),
|
||||
(ins MEMI32:$ptr, GPRI32:$src, GPRI32:$src1, i32imm:$id),
|
||||
!strconcat(op.Text, !strconcat(idType," $dst, $ptr, $src1, $src")),
|
||||
[(set GPRI32:$dst, (intr ADDR:$ptr, GPRI32:$src, GPRI32:$src1, timm:$id))]>;
|
||||
|
||||
// TODO: Need to get this working without dst...
|
||||
class TriAtomNoRet<ILOpCode op, string idType, SDNode intr>
|
||||
: ILFormat<op, (outs GPRI32:$dst),
|
||||
(ins MEMI32:$ptr, GPRI32:$src, GPRI32:$src1, i32imm:$id),
|
||||
!strconcat(op.Text, !strconcat(idType," $ptr, $src, $src1")),
|
||||
[(set GPRI32:$dst, (intr ADDR:$ptr, GPRI32:$src, GPRI32:$src1, timm:$id))]>;
|
||||
|
||||
// TODO: Need to get this working without dst...
|
||||
class CmpXChgNoRet<ILOpCode op, string idType, SDNode intr>
|
||||
: ILFormat<op, (outs GPRI32:$dst),
|
||||
(ins MEMI32:$ptr, GPRI32:$src, GPRI32:$src1, i32imm:$id),
|
||||
!strconcat(op.Text, !strconcat(idType," $ptr, $src1, $src")),
|
||||
[(set GPRI32:$dst, (intr ADDR:$ptr, GPRI32:$src, GPRI32:$src1, timm:$id))]>;
|
||||
|
||||
|
||||
//===--------------------------------------------------------------------===//
|
||||
// Classes for dealing with atomic instructions w/ 64bit pointers
|
||||
//===--------------------------------------------------------------------===//
|
||||
class Append64<ILOpCode op, string idType, SDNode intr>
|
||||
: ILFormat<op, (outs GPRI32:$dst),
|
||||
(ins MEMI64:$id),
|
||||
!strconcat(op.Text, !strconcat(idType," $dst")),
|
||||
[(set GPRI32:$dst, (intr ADDR64:$id))]>;
|
||||
|
||||
|
||||
// TODO: Need to get this working without dst...
|
||||
class AppendNoRet64<ILOpCode op, string idType, SDNode intr>
|
||||
: ILFormat<op, (outs GPRI32:$dst),
|
||||
(ins MEMI64:$id),
|
||||
!strconcat(op.Text, !strconcat(idType," $dst")),
|
||||
[(set GPRI32:$dst, (intr ADDR64:$id))]>;
|
||||
|
||||
class UniAtom64<ILOpCode op, string idType, SDNode intr>
|
||||
: ILFormat<op, (outs GPRI32:$dst),
|
||||
(ins MEMI64:$ptr, i32imm:$id),
|
||||
!strconcat(op.Text, !strconcat(idType," $dst, $ptr")),
|
||||
[(set GPRI32:$dst, (intr ADDR64:$ptr, timm:$id))]>;
|
||||
|
||||
|
||||
// TODO: Need to get this working without dst...
|
||||
class UniAtomNoRet64<ILOpCode op, string idType, SDNode intr>
|
||||
: ILFormat<op, (outs GPRI32:$dst), (ins MEMI64:$ptr, i32imm:$id),
|
||||
!strconcat(op.Text, !strconcat(idType," $ptr")),
|
||||
[(set GPRI32:$dst, (intr ADDR64:$ptr, timm:$id))]>;
|
||||
|
||||
class BinAtom64<ILOpCode op, string idType, SDNode intr>
|
||||
: ILFormat<op, (outs GPRI32:$dst),
|
||||
(ins MEMI64:$ptr, GPRI32:$src, i32imm:$id),
|
||||
!strconcat(op.Text, !strconcat(idType," $dst, $ptr, $src")),
|
||||
[(set GPRI32:$dst, (intr ADDR64:$ptr, GPRI32:$src, timm:$id))]>;
|
||||
|
||||
|
||||
// TODO: Need to get this working without dst...
|
||||
class BinAtomNoRet64<ILOpCode op, string idType, SDNode intr>
|
||||
: ILFormat<op, (outs GPRI32:$dst), (ins MEMI64:$ptr, GPRI32:$src, i32imm:$id),
|
||||
!strconcat(op.Text, !strconcat(idType," $ptr, $src")),
|
||||
[(set GPRI32:$dst, (intr ADDR64:$ptr, GPRI32:$src, timm:$id))]>;
|
||||
|
||||
class TriAtom64<ILOpCode op, string idType, SDNode intr>
|
||||
: ILFormat<op, (outs GPRI32:$dst),
|
||||
(ins MEMI64:$ptr, GPRI32:$src, GPRI32:$src1, i32imm:$id),
|
||||
!strconcat(op.Text, !strconcat(idType," $dst, $ptr, $src, $src1")),
|
||||
[(set GPRI32:$dst, (intr ADDR64:$ptr, GPRI32:$src, GPRI32:$src1, timm:$id))]>;
|
||||
|
||||
class CmpXChg64<ILOpCode op, string idType, SDNode intr>
|
||||
: ILFormat<op, (outs GPRI32:$dst),
|
||||
(ins MEMI64:$ptr, GPRI32:$src, GPRI32:$src1, i32imm:$id),
|
||||
!strconcat(op.Text, !strconcat(idType," $dst, $ptr, $src1, $src")),
|
||||
[(set GPRI32:$dst, (intr ADDR64:$ptr, GPRI32:$src, GPRI32:$src1, timm:$id))]>;
|
||||
|
||||
// TODO: Need to get this working without dst...
|
||||
class TriAtomNoRet64<ILOpCode op, string idType, SDNode intr>
|
||||
: ILFormat<op, (outs GPRI32:$dst),
|
||||
(ins MEMI64:$ptr, GPRI32:$src, GPRI32:$src1, i32imm:$id),
|
||||
!strconcat(op.Text, !strconcat(idType," $ptr, $src, $src1")),
|
||||
[(set GPRI32:$dst, (intr ADDR64:$ptr, GPRI32:$src, GPRI32:$src1, timm:$id))]>;
|
||||
|
||||
// TODO: Need to get this working without dst...
|
||||
class CmpXChgNoRet64<ILOpCode op, string idType, SDNode intr>
|
||||
: ILFormat<op, (outs GPRI32:$dst),
|
||||
(ins MEMI64:$ptr, GPRI32:$src, GPRI32:$src1, i32imm:$id),
|
||||
!strconcat(op.Text, !strconcat(idType," $ptr, $src1, $src")),
|
||||
[(set GPRI32:$dst, (intr ADDR64:$ptr, GPRI32:$src, GPRI32:$src1, timm:$id))]>;
|
||||
|
||||
//===--------------------------------------------------------------------===//
|
||||
// Intrinsic classes
|
||||
// Generic versions of the above classes but for Target specific intrinsics
|
||||
|
|
|
|||
|
|
@ -65,8 +65,6 @@ private:
|
|||
static bool isLocalLoad(const LoadSDNode *N);
|
||||
static bool isRegionLoad(const LoadSDNode *N);
|
||||
|
||||
SDNode *xformAtomicInst(SDNode *N);
|
||||
|
||||
bool SelectADDR8BitOffset(SDValue Addr, SDValue& Base, SDValue& Offset);
|
||||
bool SelectADDRReg(SDValue Addr, SDValue& Base, SDValue& Offset);
|
||||
bool SelectADDRVTX_READ(SDValue Addr, SDValue &Base, SDValue &Offset);
|
||||
|
|
@ -170,11 +168,6 @@ SDNode *AMDILDAGToDAGISel::Select(SDNode *N) {
|
|||
}
|
||||
break;
|
||||
}
|
||||
// For all atomic instructions, we need to add a constant
|
||||
// operand that stores the resource ID in the instruction
|
||||
if (Opc > AMDILISD::ADDADDR && Opc < AMDILISD::APPEND_ALLOC) {
|
||||
N = xformAtomicInst(N);
|
||||
}
|
||||
return SelectCode(N);
|
||||
}
|
||||
|
||||
|
|
@ -313,206 +306,6 @@ const char *AMDILDAGToDAGISel::getPassName() const {
|
|||
return "AMDIL DAG->DAG Pattern Instruction Selection";
|
||||
}
|
||||
|
||||
SDNode*
|
||||
AMDILDAGToDAGISel::xformAtomicInst(SDNode *N)
|
||||
{
|
||||
uint32_t addVal = 1;
|
||||
bool addOne = false;
|
||||
// bool bitCastToInt = (N->getValueType(0) == MVT::f32);
|
||||
unsigned opc = N->getOpcode();
|
||||
switch (opc) {
|
||||
default: return N;
|
||||
case AMDILISD::ATOM_G_ADD:
|
||||
case AMDILISD::ATOM_G_AND:
|
||||
case AMDILISD::ATOM_G_MAX:
|
||||
case AMDILISD::ATOM_G_UMAX:
|
||||
case AMDILISD::ATOM_G_MIN:
|
||||
case AMDILISD::ATOM_G_UMIN:
|
||||
case AMDILISD::ATOM_G_OR:
|
||||
case AMDILISD::ATOM_G_SUB:
|
||||
case AMDILISD::ATOM_G_RSUB:
|
||||
case AMDILISD::ATOM_G_XCHG:
|
||||
case AMDILISD::ATOM_G_XOR:
|
||||
case AMDILISD::ATOM_G_ADD_NORET:
|
||||
case AMDILISD::ATOM_G_AND_NORET:
|
||||
case AMDILISD::ATOM_G_MAX_NORET:
|
||||
case AMDILISD::ATOM_G_UMAX_NORET:
|
||||
case AMDILISD::ATOM_G_MIN_NORET:
|
||||
case AMDILISD::ATOM_G_UMIN_NORET:
|
||||
case AMDILISD::ATOM_G_OR_NORET:
|
||||
case AMDILISD::ATOM_G_SUB_NORET:
|
||||
case AMDILISD::ATOM_G_RSUB_NORET:
|
||||
case AMDILISD::ATOM_G_XCHG_NORET:
|
||||
case AMDILISD::ATOM_G_XOR_NORET:
|
||||
case AMDILISD::ATOM_L_ADD:
|
||||
case AMDILISD::ATOM_L_AND:
|
||||
case AMDILISD::ATOM_L_MAX:
|
||||
case AMDILISD::ATOM_L_UMAX:
|
||||
case AMDILISD::ATOM_L_MIN:
|
||||
case AMDILISD::ATOM_L_UMIN:
|
||||
case AMDILISD::ATOM_L_OR:
|
||||
case AMDILISD::ATOM_L_SUB:
|
||||
case AMDILISD::ATOM_L_RSUB:
|
||||
case AMDILISD::ATOM_L_XCHG:
|
||||
case AMDILISD::ATOM_L_XOR:
|
||||
case AMDILISD::ATOM_L_ADD_NORET:
|
||||
case AMDILISD::ATOM_L_AND_NORET:
|
||||
case AMDILISD::ATOM_L_MAX_NORET:
|
||||
case AMDILISD::ATOM_L_UMAX_NORET:
|
||||
case AMDILISD::ATOM_L_MIN_NORET:
|
||||
case AMDILISD::ATOM_L_UMIN_NORET:
|
||||
case AMDILISD::ATOM_L_OR_NORET:
|
||||
case AMDILISD::ATOM_L_SUB_NORET:
|
||||
case AMDILISD::ATOM_L_RSUB_NORET:
|
||||
case AMDILISD::ATOM_L_XCHG_NORET:
|
||||
case AMDILISD::ATOM_L_XOR_NORET:
|
||||
case AMDILISD::ATOM_R_ADD:
|
||||
case AMDILISD::ATOM_R_AND:
|
||||
case AMDILISD::ATOM_R_MAX:
|
||||
case AMDILISD::ATOM_R_UMAX:
|
||||
case AMDILISD::ATOM_R_MIN:
|
||||
case AMDILISD::ATOM_R_UMIN:
|
||||
case AMDILISD::ATOM_R_OR:
|
||||
case AMDILISD::ATOM_R_SUB:
|
||||
case AMDILISD::ATOM_R_RSUB:
|
||||
case AMDILISD::ATOM_R_XCHG:
|
||||
case AMDILISD::ATOM_R_XOR:
|
||||
case AMDILISD::ATOM_R_ADD_NORET:
|
||||
case AMDILISD::ATOM_R_AND_NORET:
|
||||
case AMDILISD::ATOM_R_MAX_NORET:
|
||||
case AMDILISD::ATOM_R_UMAX_NORET:
|
||||
case AMDILISD::ATOM_R_MIN_NORET:
|
||||
case AMDILISD::ATOM_R_UMIN_NORET:
|
||||
case AMDILISD::ATOM_R_OR_NORET:
|
||||
case AMDILISD::ATOM_R_SUB_NORET:
|
||||
case AMDILISD::ATOM_R_RSUB_NORET:
|
||||
case AMDILISD::ATOM_R_XCHG_NORET:
|
||||
case AMDILISD::ATOM_R_XOR_NORET:
|
||||
case AMDILISD::ATOM_G_CMPXCHG:
|
||||
case AMDILISD::ATOM_G_CMPXCHG_NORET:
|
||||
case AMDILISD::ATOM_L_CMPXCHG:
|
||||
case AMDILISD::ATOM_L_CMPXCHG_NORET:
|
||||
case AMDILISD::ATOM_R_CMPXCHG:
|
||||
case AMDILISD::ATOM_R_CMPXCHG_NORET:
|
||||
break;
|
||||
case AMDILISD::ATOM_G_DEC:
|
||||
addOne = true;
|
||||
if (Subtarget.calVersion() >= CAL_VERSION_SC_136) {
|
||||
addVal = (uint32_t)-1;
|
||||
} else {
|
||||
opc = AMDILISD::ATOM_G_SUB;
|
||||
}
|
||||
break;
|
||||
case AMDILISD::ATOM_G_INC:
|
||||
addOne = true;
|
||||
if (Subtarget.calVersion() >= CAL_VERSION_SC_136) {
|
||||
addVal = (uint32_t)-1;
|
||||
} else {
|
||||
opc = AMDILISD::ATOM_G_ADD;
|
||||
}
|
||||
break;
|
||||
case AMDILISD::ATOM_G_DEC_NORET:
|
||||
addOne = true;
|
||||
if (Subtarget.calVersion() >= CAL_VERSION_SC_136) {
|
||||
addVal = (uint32_t)-1;
|
||||
} else {
|
||||
opc = AMDILISD::ATOM_G_SUB_NORET;
|
||||
}
|
||||
break;
|
||||
case AMDILISD::ATOM_G_INC_NORET:
|
||||
addOne = true;
|
||||
if (Subtarget.calVersion() >= CAL_VERSION_SC_136) {
|
||||
addVal = (uint32_t)-1;
|
||||
} else {
|
||||
opc = AMDILISD::ATOM_G_ADD_NORET;
|
||||
}
|
||||
break;
|
||||
case AMDILISD::ATOM_L_DEC:
|
||||
addOne = true;
|
||||
if (Subtarget.calVersion() >= CAL_VERSION_SC_136) {
|
||||
addVal = (uint32_t)-1;
|
||||
} else {
|
||||
opc = AMDILISD::ATOM_L_SUB;
|
||||
}
|
||||
break;
|
||||
case AMDILISD::ATOM_L_INC:
|
||||
addOne = true;
|
||||
if (Subtarget.calVersion() >= CAL_VERSION_SC_136) {
|
||||
addVal = (uint32_t)-1;
|
||||
} else {
|
||||
opc = AMDILISD::ATOM_L_ADD;
|
||||
}
|
||||
break;
|
||||
case AMDILISD::ATOM_L_DEC_NORET:
|
||||
addOne = true;
|
||||
if (Subtarget.calVersion() >= CAL_VERSION_SC_136) {
|
||||
addVal = (uint32_t)-1;
|
||||
} else {
|
||||
opc = AMDILISD::ATOM_L_SUB_NORET;
|
||||
}
|
||||
break;
|
||||
case AMDILISD::ATOM_L_INC_NORET:
|
||||
addOne = true;
|
||||
if (Subtarget.calVersion() >= CAL_VERSION_SC_136) {
|
||||
addVal = (uint32_t)-1;
|
||||
} else {
|
||||
opc = AMDILISD::ATOM_L_ADD_NORET;
|
||||
}
|
||||
break;
|
||||
case AMDILISD::ATOM_R_DEC:
|
||||
addOne = true;
|
||||
if (Subtarget.calVersion() >= CAL_VERSION_SC_136) {
|
||||
addVal = (uint32_t)-1;
|
||||
} else {
|
||||
opc = AMDILISD::ATOM_R_SUB;
|
||||
}
|
||||
break;
|
||||
case AMDILISD::ATOM_R_INC:
|
||||
addOne = true;
|
||||
if (Subtarget.calVersion() >= CAL_VERSION_SC_136) {
|
||||
addVal = (uint32_t)-1;
|
||||
} else {
|
||||
opc = AMDILISD::ATOM_R_ADD;
|
||||
}
|
||||
break;
|
||||
case AMDILISD::ATOM_R_DEC_NORET:
|
||||
addOne = true;
|
||||
if (Subtarget.calVersion() >= CAL_VERSION_SC_136) {
|
||||
addVal = (uint32_t)-1;
|
||||
} else {
|
||||
opc = AMDILISD::ATOM_R_SUB;
|
||||
}
|
||||
break;
|
||||
case AMDILISD::ATOM_R_INC_NORET:
|
||||
addOne = true;
|
||||
if (Subtarget.calVersion() >= CAL_VERSION_SC_136) {
|
||||
addVal = (uint32_t)-1;
|
||||
} else {
|
||||
opc = AMDILISD::ATOM_R_ADD_NORET;
|
||||
}
|
||||
break;
|
||||
}
|
||||
// The largest we can have is a cmpxchg w/ a return value and an output chain.
|
||||
// The cmpxchg function has 3 inputs and a single output along with an
|
||||
// output change and a target constant, giving a total of 6.
|
||||
SDValue Ops[12];
|
||||
unsigned x = 0;
|
||||
unsigned y = N->getNumOperands();
|
||||
for (x = 0; x < y; ++x) {
|
||||
Ops[x] = N->getOperand(x);
|
||||
}
|
||||
if (addOne) {
|
||||
Ops[x++] = SDValue(SelectCode(CurDAG->getConstant(addVal, MVT::i32).getNode()), 0);
|
||||
}
|
||||
Ops[x++] = CurDAG->getTargetConstant(0, MVT::i32);
|
||||
SDVTList Tys = N->getVTList();
|
||||
MemSDNode *MemNode = dyn_cast<MemSDNode>(N);
|
||||
assert(MemNode && "Atomic should be of MemSDNode type!");
|
||||
N = CurDAG->getMemIntrinsicNode(opc, N->getDebugLoc(), Tys, Ops, x,
|
||||
MemNode->getMemoryVT(), MemNode->getMemOperand()).getNode();
|
||||
return N;
|
||||
}
|
||||
|
||||
#ifdef DEBUGTMP
|
||||
#undef INT64_C
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -670,45 +670,13 @@ AMDILTargetLowering::getTargetNodeName(unsigned Opcode) const
|
|||
{
|
||||
switch (Opcode) {
|
||||
default: return 0;
|
||||
case AMDILISD::INTTOANY: return "AMDILISD::INTTOANY";
|
||||
case AMDILISD::DP_TO_FP: return "AMDILISD::DP_TO_FP";
|
||||
case AMDILISD::FP_TO_DP: return "AMDILISD::FP_TO_DP";
|
||||
case AMDILISD::BITCONV: return "AMDILISD::BITCONV";
|
||||
case AMDILISD::CMOV: return "AMDILISD::CMOV";
|
||||
case AMDILISD::CMOVLOG: return "AMDILISD::CMOVLOG";
|
||||
case AMDILISD::INEGATE: return "AMDILISD::INEGATE";
|
||||
case AMDILISD::MAD: return "AMDILISD::MAD";
|
||||
case AMDILISD::UMAD: return "AMDILISD::UMAD";
|
||||
case AMDILISD::CALL: return "AMDILISD::CALL";
|
||||
case AMDILISD::RET: return "AMDILISD::RET";
|
||||
case AMDILISD::IFFB_HI: return "AMDILISD::IFFB_HI";
|
||||
case AMDILISD::IFFB_LO: return "AMDILISD::IFFB_LO";
|
||||
case AMDILISD::ADD: return "AMDILISD::ADD";
|
||||
case AMDILISD::SELECT_CC: return "AMDILISD::SELECT_CC";
|
||||
case AMDILISD::UMUL: return "AMDILISD::UMUL";
|
||||
case AMDILISD::AND: return "AMDILISD::AND";
|
||||
case AMDILISD::OR: return "AMDILISD::OR";
|
||||
case AMDILISD::NOT: return "AMDILISD::NOT";
|
||||
case AMDILISD::XOR: return "AMDILISD::XOR";
|
||||
case AMDILISD::DIV_INF: return "AMDILISD::DIV_INF";
|
||||
case AMDILISD::SMAX: return "AMDILISD::SMAX";
|
||||
case AMDILISD::PHIMOVE: return "AMDILISD::PHIMOVE";
|
||||
case AMDILISD::MOVE: return "AMDILISD::MOVE";
|
||||
case AMDILISD::VBUILD: return "AMDILISD::VBUILD";
|
||||
case AMDILISD::VEXTRACT: return "AMDILISD::VEXTRACT";
|
||||
case AMDILISD::VINSERT: return "AMDILISD::VINSERT";
|
||||
case AMDILISD::VCONCAT: return "AMDILISD::VCONCAT";
|
||||
case AMDILISD::LCREATE: return "AMDILISD::LCREATE";
|
||||
case AMDILISD::LCOMPHI: return "AMDILISD::LCOMPHI";
|
||||
case AMDILISD::LCOMPLO: return "AMDILISD::LCOMPLO";
|
||||
case AMDILISD::DCREATE: return "AMDILISD::DCREATE";
|
||||
case AMDILISD::DCOMPHI: return "AMDILISD::DCOMPHI";
|
||||
case AMDILISD::DCOMPLO: return "AMDILISD::DCOMPLO";
|
||||
case AMDILISD::LCREATE2: return "AMDILISD::LCREATE2";
|
||||
case AMDILISD::LCOMPHI2: return "AMDILISD::LCOMPHI2";
|
||||
case AMDILISD::LCOMPLO2: return "AMDILISD::LCOMPLO2";
|
||||
case AMDILISD::DCREATE2: return "AMDILISD::DCREATE2";
|
||||
case AMDILISD::DCOMPHI2: return "AMDILISD::DCOMPHI2";
|
||||
case AMDILISD::DCOMPLO2: return "AMDILISD::DCOMPLO2";
|
||||
case AMDILISD::CMP: return "AMDILISD::CMP";
|
||||
case AMDILISD::IL_CC_I_LT: return "AMDILISD::IL_CC_I_LT";
|
||||
case AMDILISD::IL_CC_I_LE: return "AMDILISD::IL_CC_I_LE";
|
||||
|
|
@ -718,107 +686,6 @@ AMDILTargetLowering::getTargetNodeName(unsigned Opcode) const
|
|||
case AMDILISD::IL_CC_I_NE: return "AMDILISD::IL_CC_I_NE";
|
||||
case AMDILISD::RET_FLAG: return "AMDILISD::RET_FLAG";
|
||||
case AMDILISD::BRANCH_COND: return "AMDILISD::BRANCH_COND";
|
||||
case AMDILISD::LOOP_NZERO: return "AMDILISD::LOOP_NZERO";
|
||||
case AMDILISD::LOOP_ZERO: return "AMDILISD::LOOP_ZERO";
|
||||
case AMDILISD::LOOP_CMP: return "AMDILISD::LOOP_CMP";
|
||||
case AMDILISD::ADDADDR: return "AMDILISD::ADDADDR";
|
||||
case AMDILISD::ATOM_G_ADD: return "AMDILISD::ATOM_G_ADD";
|
||||
case AMDILISD::ATOM_G_AND: return "AMDILISD::ATOM_G_AND";
|
||||
case AMDILISD::ATOM_G_CMPXCHG: return "AMDILISD::ATOM_G_CMPXCHG";
|
||||
case AMDILISD::ATOM_G_DEC: return "AMDILISD::ATOM_G_DEC";
|
||||
case AMDILISD::ATOM_G_INC: return "AMDILISD::ATOM_G_INC";
|
||||
case AMDILISD::ATOM_G_MAX: return "AMDILISD::ATOM_G_MAX";
|
||||
case AMDILISD::ATOM_G_UMAX: return "AMDILISD::ATOM_G_UMAX";
|
||||
case AMDILISD::ATOM_G_MIN: return "AMDILISD::ATOM_G_MIN";
|
||||
case AMDILISD::ATOM_G_UMIN: return "AMDILISD::ATOM_G_UMIN";
|
||||
case AMDILISD::ATOM_G_OR: return "AMDILISD::ATOM_G_OR";
|
||||
case AMDILISD::ATOM_G_SUB: return "AMDILISD::ATOM_G_SUB";
|
||||
case AMDILISD::ATOM_G_RSUB: return "AMDILISD::ATOM_G_RSUB";
|
||||
case AMDILISD::ATOM_G_XCHG: return "AMDILISD::ATOM_G_XCHG";
|
||||
case AMDILISD::ATOM_G_XOR: return "AMDILISD::ATOM_G_XOR";
|
||||
case AMDILISD::ATOM_G_ADD_NORET: return "AMDILISD::ATOM_G_ADD_NORET";
|
||||
case AMDILISD::ATOM_G_AND_NORET: return "AMDILISD::ATOM_G_AND_NORET";
|
||||
case AMDILISD::ATOM_G_CMPXCHG_NORET: return "AMDILISD::ATOM_G_CMPXCHG_NORET";
|
||||
case AMDILISD::ATOM_G_DEC_NORET: return "AMDILISD::ATOM_G_DEC_NORET";
|
||||
case AMDILISD::ATOM_G_INC_NORET: return "AMDILISD::ATOM_G_INC_NORET";
|
||||
case AMDILISD::ATOM_G_MAX_NORET: return "AMDILISD::ATOM_G_MAX_NORET";
|
||||
case AMDILISD::ATOM_G_UMAX_NORET: return "AMDILISD::ATOM_G_UMAX_NORET";
|
||||
case AMDILISD::ATOM_G_MIN_NORET: return "AMDILISD::ATOM_G_MIN_NORET";
|
||||
case AMDILISD::ATOM_G_UMIN_NORET: return "AMDILISD::ATOM_G_UMIN_NORET";
|
||||
case AMDILISD::ATOM_G_OR_NORET: return "AMDILISD::ATOM_G_OR_NORET";
|
||||
case AMDILISD::ATOM_G_SUB_NORET: return "AMDILISD::ATOM_G_SUB_NORET";
|
||||
case AMDILISD::ATOM_G_RSUB_NORET: return "AMDILISD::ATOM_G_RSUB_NORET";
|
||||
case AMDILISD::ATOM_G_XCHG_NORET: return "AMDILISD::ATOM_G_XCHG_NORET";
|
||||
case AMDILISD::ATOM_G_XOR_NORET: return "AMDILISD::ATOM_G_XOR_NORET";
|
||||
case AMDILISD::ATOM_L_ADD: return "AMDILISD::ATOM_L_ADD";
|
||||
case AMDILISD::ATOM_L_AND: return "AMDILISD::ATOM_L_AND";
|
||||
case AMDILISD::ATOM_L_CMPXCHG: return "AMDILISD::ATOM_L_CMPXCHG";
|
||||
case AMDILISD::ATOM_L_DEC: return "AMDILISD::ATOM_L_DEC";
|
||||
case AMDILISD::ATOM_L_INC: return "AMDILISD::ATOM_L_INC";
|
||||
case AMDILISD::ATOM_L_MAX: return "AMDILISD::ATOM_L_MAX";
|
||||
case AMDILISD::ATOM_L_UMAX: return "AMDILISD::ATOM_L_UMAX";
|
||||
case AMDILISD::ATOM_L_MIN: return "AMDILISD::ATOM_L_MIN";
|
||||
case AMDILISD::ATOM_L_UMIN: return "AMDILISD::ATOM_L_UMIN";
|
||||
case AMDILISD::ATOM_L_OR: return "AMDILISD::ATOM_L_OR";
|
||||
case AMDILISD::ATOM_L_SUB: return "AMDILISD::ATOM_L_SUB";
|
||||
case AMDILISD::ATOM_L_RSUB: return "AMDILISD::ATOM_L_RSUB";
|
||||
case AMDILISD::ATOM_L_XCHG: return "AMDILISD::ATOM_L_XCHG";
|
||||
case AMDILISD::ATOM_L_XOR: return "AMDILISD::ATOM_L_XOR";
|
||||
case AMDILISD::ATOM_L_ADD_NORET: return "AMDILISD::ATOM_L_ADD_NORET";
|
||||
case AMDILISD::ATOM_L_AND_NORET: return "AMDILISD::ATOM_L_AND_NORET";
|
||||
case AMDILISD::ATOM_L_CMPXCHG_NORET: return "AMDILISD::ATOM_L_CMPXCHG_NORET";
|
||||
case AMDILISD::ATOM_L_DEC_NORET: return "AMDILISD::ATOM_L_DEC_NORET";
|
||||
case AMDILISD::ATOM_L_INC_NORET: return "AMDILISD::ATOM_L_INC_NORET";
|
||||
case AMDILISD::ATOM_L_MAX_NORET: return "AMDILISD::ATOM_L_MAX_NORET";
|
||||
case AMDILISD::ATOM_L_UMAX_NORET: return "AMDILISD::ATOM_L_UMAX_NORET";
|
||||
case AMDILISD::ATOM_L_MIN_NORET: return "AMDILISD::ATOM_L_MIN_NORET";
|
||||
case AMDILISD::ATOM_L_UMIN_NORET: return "AMDILISD::ATOM_L_UMIN_NORET";
|
||||
case AMDILISD::ATOM_L_OR_NORET: return "AMDILISD::ATOM_L_OR_NORET";
|
||||
case AMDILISD::ATOM_L_SUB_NORET: return "AMDILISD::ATOM_L_SUB_NORET";
|
||||
case AMDILISD::ATOM_L_RSUB_NORET: return "AMDILISD::ATOM_L_RSUB_NORET";
|
||||
case AMDILISD::ATOM_L_XCHG_NORET: return "AMDILISD::ATOM_L_XCHG_NORET";
|
||||
case AMDILISD::ATOM_R_ADD: return "AMDILISD::ATOM_R_ADD";
|
||||
case AMDILISD::ATOM_R_AND: return "AMDILISD::ATOM_R_AND";
|
||||
case AMDILISD::ATOM_R_CMPXCHG: return "AMDILISD::ATOM_R_CMPXCHG";
|
||||
case AMDILISD::ATOM_R_DEC: return "AMDILISD::ATOM_R_DEC";
|
||||
case AMDILISD::ATOM_R_INC: return "AMDILISD::ATOM_R_INC";
|
||||
case AMDILISD::ATOM_R_MAX: return "AMDILISD::ATOM_R_MAX";
|
||||
case AMDILISD::ATOM_R_UMAX: return "AMDILISD::ATOM_R_UMAX";
|
||||
case AMDILISD::ATOM_R_MIN: return "AMDILISD::ATOM_R_MIN";
|
||||
case AMDILISD::ATOM_R_UMIN: return "AMDILISD::ATOM_R_UMIN";
|
||||
case AMDILISD::ATOM_R_OR: return "AMDILISD::ATOM_R_OR";
|
||||
case AMDILISD::ATOM_R_MSKOR: return "AMDILISD::ATOM_R_MSKOR";
|
||||
case AMDILISD::ATOM_R_SUB: return "AMDILISD::ATOM_R_SUB";
|
||||
case AMDILISD::ATOM_R_RSUB: return "AMDILISD::ATOM_R_RSUB";
|
||||
case AMDILISD::ATOM_R_XCHG: return "AMDILISD::ATOM_R_XCHG";
|
||||
case AMDILISD::ATOM_R_XOR: return "AMDILISD::ATOM_R_XOR";
|
||||
case AMDILISD::ATOM_R_ADD_NORET: return "AMDILISD::ATOM_R_ADD_NORET";
|
||||
case AMDILISD::ATOM_R_AND_NORET: return "AMDILISD::ATOM_R_AND_NORET";
|
||||
case AMDILISD::ATOM_R_CMPXCHG_NORET: return "AMDILISD::ATOM_R_CMPXCHG_NORET";
|
||||
case AMDILISD::ATOM_R_DEC_NORET: return "AMDILISD::ATOM_R_DEC_NORET";
|
||||
case AMDILISD::ATOM_R_INC_NORET: return "AMDILISD::ATOM_R_INC_NORET";
|
||||
case AMDILISD::ATOM_R_MAX_NORET: return "AMDILISD::ATOM_R_MAX_NORET";
|
||||
case AMDILISD::ATOM_R_UMAX_NORET: return "AMDILISD::ATOM_R_UMAX_NORET";
|
||||
case AMDILISD::ATOM_R_MIN_NORET: return "AMDILISD::ATOM_R_MIN_NORET";
|
||||
case AMDILISD::ATOM_R_UMIN_NORET: return "AMDILISD::ATOM_R_UMIN_NORET";
|
||||
case AMDILISD::ATOM_R_OR_NORET: return "AMDILISD::ATOM_R_OR_NORET";
|
||||
case AMDILISD::ATOM_R_MSKOR_NORET: return "AMDILISD::ATOM_R_MSKOR_NORET";
|
||||
case AMDILISD::ATOM_R_SUB_NORET: return "AMDILISD::ATOM_R_SUB_NORET";
|
||||
case AMDILISD::ATOM_R_RSUB_NORET: return "AMDILISD::ATOM_R_RSUB_NORET";
|
||||
case AMDILISD::ATOM_R_XCHG_NORET: return "AMDILISD::ATOM_R_XCHG_NORET";
|
||||
case AMDILISD::ATOM_R_XOR_NORET: return "AMDILISD::ATOM_R_XOR_NORET";
|
||||
case AMDILISD::APPEND_ALLOC: return "AMDILISD::APPEND_ALLOC";
|
||||
case AMDILISD::APPEND_ALLOC_NORET: return "AMDILISD::APPEND_ALLOC_NORET";
|
||||
case AMDILISD::APPEND_CONSUME: return "AMDILISD::APPEND_CONSUME";
|
||||
case AMDILISD::APPEND_CONSUME_NORET: return "AMDILISD::APPEND_CONSUME_NORET";
|
||||
case AMDILISD::IMAGE2D_READ: return "AMDILISD::IMAGE2D_READ";
|
||||
case AMDILISD::IMAGE2D_WRITE: return "AMDILISD::IMAGE2D_WRITE";
|
||||
case AMDILISD::IMAGE2D_INFO0: return "AMDILISD::IMAGE2D_INFO0";
|
||||
case AMDILISD::IMAGE2D_INFO1: return "AMDILISD::IMAGE2D_INFO1";
|
||||
case AMDILISD::IMAGE3D_READ: return "AMDILISD::IMAGE3D_READ";
|
||||
case AMDILISD::IMAGE3D_WRITE: return "AMDILISD::IMAGE3D_WRITE";
|
||||
case AMDILISD::IMAGE3D_INFO0: return "AMDILISD::IMAGE3D_INFO0";
|
||||
case AMDILISD::IMAGE3D_INFO1: return "AMDILISD::IMAGE3D_INFO1";
|
||||
|
||||
};
|
||||
}
|
||||
|
|
@ -826,380 +693,7 @@ bool
|
|||
AMDILTargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info,
|
||||
const CallInst &I, unsigned Intrinsic) const
|
||||
{
|
||||
if (Intrinsic <= AMDGPUIntrinsic::last_non_AMDIL_intrinsic
|
||||
|| Intrinsic > AMDGPUIntrinsic::num_AMDIL_intrinsics) {
|
||||
return false;
|
||||
}
|
||||
bool bitCastToInt = false;
|
||||
unsigned IntNo;
|
||||
bool isRet = true;
|
||||
const AMDILSubtarget *STM = &this->getTargetMachine()
|
||||
.getSubtarget<AMDILSubtarget>();
|
||||
switch (Intrinsic) {
|
||||
default: return false; // Don't custom lower most intrinsics.
|
||||
case AMDGPUIntrinsic::AMDIL_atomic_add_gi32:
|
||||
case AMDGPUIntrinsic::AMDIL_atomic_add_gu32:
|
||||
IntNo = AMDILISD::ATOM_G_ADD; break;
|
||||
case AMDGPUIntrinsic::AMDIL_atomic_add_gi32_noret:
|
||||
case AMDGPUIntrinsic::AMDIL_atomic_add_gu32_noret:
|
||||
isRet = false;
|
||||
IntNo = AMDILISD::ATOM_G_ADD_NORET; break;
|
||||
case AMDGPUIntrinsic::AMDIL_atomic_add_lu32:
|
||||
case AMDGPUIntrinsic::AMDIL_atomic_add_li32:
|
||||
IntNo = AMDILISD::ATOM_L_ADD; break;
|
||||
case AMDGPUIntrinsic::AMDIL_atomic_add_li32_noret:
|
||||
case AMDGPUIntrinsic::AMDIL_atomic_add_lu32_noret:
|
||||
isRet = false;
|
||||
IntNo = AMDILISD::ATOM_L_ADD_NORET; break;
|
||||
case AMDGPUIntrinsic::AMDIL_atomic_add_ru32:
|
||||
case AMDGPUIntrinsic::AMDIL_atomic_add_ri32:
|
||||
IntNo = AMDILISD::ATOM_R_ADD; break;
|
||||
case AMDGPUIntrinsic::AMDIL_atomic_add_ri32_noret:
|
||||
case AMDGPUIntrinsic::AMDIL_atomic_add_ru32_noret:
|
||||
isRet = false;
|
||||
IntNo = AMDILISD::ATOM_R_ADD_NORET; break;
|
||||
case AMDGPUIntrinsic::AMDIL_atomic_and_gi32:
|
||||
case AMDGPUIntrinsic::AMDIL_atomic_and_gu32:
|
||||
IntNo = AMDILISD::ATOM_G_AND; break;
|
||||
case AMDGPUIntrinsic::AMDIL_atomic_and_gi32_noret:
|
||||
case AMDGPUIntrinsic::AMDIL_atomic_and_gu32_noret:
|
||||
isRet = false;
|
||||
IntNo = AMDILISD::ATOM_G_AND_NORET; break;
|
||||
case AMDGPUIntrinsic::AMDIL_atomic_and_li32:
|
||||
case AMDGPUIntrinsic::AMDIL_atomic_and_lu32:
|
||||
IntNo = AMDILISD::ATOM_L_AND; break;
|
||||
case AMDGPUIntrinsic::AMDIL_atomic_and_li32_noret:
|
||||
case AMDGPUIntrinsic::AMDIL_atomic_and_lu32_noret:
|
||||
isRet = false;
|
||||
IntNo = AMDILISD::ATOM_L_AND_NORET; break;
|
||||
case AMDGPUIntrinsic::AMDIL_atomic_and_ri32:
|
||||
case AMDGPUIntrinsic::AMDIL_atomic_and_ru32:
|
||||
IntNo = AMDILISD::ATOM_R_AND; break;
|
||||
case AMDGPUIntrinsic::AMDIL_atomic_and_ri32_noret:
|
||||
case AMDGPUIntrinsic::AMDIL_atomic_and_ru32_noret:
|
||||
isRet = false;
|
||||
IntNo = AMDILISD::ATOM_R_AND_NORET; break;
|
||||
case AMDGPUIntrinsic::AMDIL_atomic_cmpxchg_gi32:
|
||||
case AMDGPUIntrinsic::AMDIL_atomic_cmpxchg_gu32:
|
||||
IntNo = AMDILISD::ATOM_G_CMPXCHG; break;
|
||||
case AMDGPUIntrinsic::AMDIL_atomic_cmpxchg_gi32_noret:
|
||||
case AMDGPUIntrinsic::AMDIL_atomic_cmpxchg_gu32_noret:
|
||||
isRet = false;
|
||||
IntNo = AMDILISD::ATOM_G_CMPXCHG_NORET; break;
|
||||
case AMDGPUIntrinsic::AMDIL_atomic_cmpxchg_li32:
|
||||
case AMDGPUIntrinsic::AMDIL_atomic_cmpxchg_lu32:
|
||||
IntNo = AMDILISD::ATOM_L_CMPXCHG; break;
|
||||
case AMDGPUIntrinsic::AMDIL_atomic_cmpxchg_li32_noret:
|
||||
case AMDGPUIntrinsic::AMDIL_atomic_cmpxchg_lu32_noret:
|
||||
isRet = false;
|
||||
IntNo = AMDILISD::ATOM_L_CMPXCHG_NORET; break;
|
||||
case AMDGPUIntrinsic::AMDIL_atomic_cmpxchg_ri32:
|
||||
case AMDGPUIntrinsic::AMDIL_atomic_cmpxchg_ru32:
|
||||
IntNo = AMDILISD::ATOM_R_CMPXCHG; break;
|
||||
case AMDGPUIntrinsic::AMDIL_atomic_cmpxchg_ri32_noret:
|
||||
case AMDGPUIntrinsic::AMDIL_atomic_cmpxchg_ru32_noret:
|
||||
isRet = false;
|
||||
IntNo = AMDILISD::ATOM_R_CMPXCHG_NORET; break;
|
||||
case AMDGPUIntrinsic::AMDIL_atomic_dec_gi32:
|
||||
case AMDGPUIntrinsic::AMDIL_atomic_dec_gu32:
|
||||
if (STM->calVersion() >= CAL_VERSION_SC_136) {
|
||||
IntNo = AMDILISD::ATOM_G_DEC;
|
||||
} else {
|
||||
IntNo = AMDILISD::ATOM_G_SUB;
|
||||
}
|
||||
break;
|
||||
case AMDGPUIntrinsic::AMDIL_atomic_dec_gi32_noret:
|
||||
case AMDGPUIntrinsic::AMDIL_atomic_dec_gu32_noret:
|
||||
isRet = false;
|
||||
if (STM->calVersion() >= CAL_VERSION_SC_136) {
|
||||
IntNo = AMDILISD::ATOM_G_DEC_NORET;
|
||||
} else {
|
||||
IntNo = AMDILISD::ATOM_G_SUB_NORET;
|
||||
}
|
||||
break;
|
||||
case AMDGPUIntrinsic::AMDIL_atomic_dec_li32:
|
||||
case AMDGPUIntrinsic::AMDIL_atomic_dec_lu32:
|
||||
if (STM->calVersion() >= CAL_VERSION_SC_136) {
|
||||
IntNo = AMDILISD::ATOM_L_DEC;
|
||||
} else {
|
||||
IntNo = AMDILISD::ATOM_L_SUB;
|
||||
}
|
||||
break;
|
||||
case AMDGPUIntrinsic::AMDIL_atomic_dec_li32_noret:
|
||||
case AMDGPUIntrinsic::AMDIL_atomic_dec_lu32_noret:
|
||||
isRet = false;
|
||||
if (STM->calVersion() >= CAL_VERSION_SC_136) {
|
||||
IntNo = AMDILISD::ATOM_L_DEC_NORET;
|
||||
} else {
|
||||
IntNo = AMDILISD::ATOM_L_SUB_NORET;
|
||||
}
|
||||
break;
|
||||
case AMDGPUIntrinsic::AMDIL_atomic_dec_ri32:
|
||||
case AMDGPUIntrinsic::AMDIL_atomic_dec_ru32:
|
||||
if (STM->calVersion() >= CAL_VERSION_SC_136) {
|
||||
IntNo = AMDILISD::ATOM_R_DEC;
|
||||
} else {
|
||||
IntNo = AMDILISD::ATOM_R_SUB;
|
||||
}
|
||||
break;
|
||||
case AMDGPUIntrinsic::AMDIL_atomic_dec_ri32_noret:
|
||||
case AMDGPUIntrinsic::AMDIL_atomic_dec_ru32_noret:
|
||||
isRet = false;
|
||||
if (STM->calVersion() >= CAL_VERSION_SC_136) {
|
||||
IntNo = AMDILISD::ATOM_R_DEC_NORET;
|
||||
} else {
|
||||
IntNo = AMDILISD::ATOM_R_SUB_NORET;
|
||||
}
|
||||
break;
|
||||
case AMDGPUIntrinsic::AMDIL_atomic_inc_gi32:
|
||||
case AMDGPUIntrinsic::AMDIL_atomic_inc_gu32:
|
||||
if (STM->calVersion() >= CAL_VERSION_SC_136) {
|
||||
IntNo = AMDILISD::ATOM_G_INC;
|
||||
} else {
|
||||
IntNo = AMDILISD::ATOM_G_ADD;
|
||||
}
|
||||
break;
|
||||
case AMDGPUIntrinsic::AMDIL_atomic_inc_gi32_noret:
|
||||
case AMDGPUIntrinsic::AMDIL_atomic_inc_gu32_noret:
|
||||
isRet = false;
|
||||
if (STM->calVersion() >= CAL_VERSION_SC_136) {
|
||||
IntNo = AMDILISD::ATOM_G_INC_NORET;
|
||||
} else {
|
||||
IntNo = AMDILISD::ATOM_G_ADD_NORET;
|
||||
}
|
||||
break;
|
||||
case AMDGPUIntrinsic::AMDIL_atomic_inc_li32:
|
||||
case AMDGPUIntrinsic::AMDIL_atomic_inc_lu32:
|
||||
if (STM->calVersion() >= CAL_VERSION_SC_136) {
|
||||
IntNo = AMDILISD::ATOM_L_INC;
|
||||
} else {
|
||||
IntNo = AMDILISD::ATOM_L_ADD;
|
||||
}
|
||||
break;
|
||||
case AMDGPUIntrinsic::AMDIL_atomic_inc_li32_noret:
|
||||
case AMDGPUIntrinsic::AMDIL_atomic_inc_lu32_noret:
|
||||
isRet = false;
|
||||
if (STM->calVersion() >= CAL_VERSION_SC_136) {
|
||||
IntNo = AMDILISD::ATOM_L_INC_NORET;
|
||||
} else {
|
||||
IntNo = AMDILISD::ATOM_L_ADD_NORET;
|
||||
}
|
||||
break;
|
||||
case AMDGPUIntrinsic::AMDIL_atomic_inc_ri32:
|
||||
case AMDGPUIntrinsic::AMDIL_atomic_inc_ru32:
|
||||
if (STM->calVersion() >= CAL_VERSION_SC_136) {
|
||||
IntNo = AMDILISD::ATOM_R_INC;
|
||||
} else {
|
||||
IntNo = AMDILISD::ATOM_R_ADD;
|
||||
}
|
||||
break;
|
||||
case AMDGPUIntrinsic::AMDIL_atomic_inc_ri32_noret:
|
||||
case AMDGPUIntrinsic::AMDIL_atomic_inc_ru32_noret:
|
||||
isRet = false;
|
||||
if (STM->calVersion() >= CAL_VERSION_SC_136) {
|
||||
IntNo = AMDILISD::ATOM_R_INC_NORET;
|
||||
} else {
|
||||
IntNo = AMDILISD::ATOM_R_ADD_NORET;
|
||||
}
|
||||
break;
|
||||
case AMDGPUIntrinsic::AMDIL_atomic_max_gi32:
|
||||
IntNo = AMDILISD::ATOM_G_MAX; break;
|
||||
case AMDGPUIntrinsic::AMDIL_atomic_max_gu32:
|
||||
IntNo = AMDILISD::ATOM_G_UMAX; break;
|
||||
case AMDGPUIntrinsic::AMDIL_atomic_max_gi32_noret:
|
||||
isRet = false;
|
||||
IntNo = AMDILISD::ATOM_G_MAX_NORET; break;
|
||||
case AMDGPUIntrinsic::AMDIL_atomic_max_gu32_noret:
|
||||
isRet = false;
|
||||
IntNo = AMDILISD::ATOM_G_UMAX_NORET; break;
|
||||
case AMDGPUIntrinsic::AMDIL_atomic_max_li32:
|
||||
IntNo = AMDILISD::ATOM_L_MAX; break;
|
||||
case AMDGPUIntrinsic::AMDIL_atomic_max_lu32:
|
||||
IntNo = AMDILISD::ATOM_L_UMAX; break;
|
||||
case AMDGPUIntrinsic::AMDIL_atomic_max_li32_noret:
|
||||
isRet = false;
|
||||
IntNo = AMDILISD::ATOM_L_MAX_NORET; break;
|
||||
case AMDGPUIntrinsic::AMDIL_atomic_max_lu32_noret:
|
||||
isRet = false;
|
||||
IntNo = AMDILISD::ATOM_L_UMAX_NORET; break;
|
||||
case AMDGPUIntrinsic::AMDIL_atomic_max_ri32:
|
||||
IntNo = AMDILISD::ATOM_R_MAX; break;
|
||||
case AMDGPUIntrinsic::AMDIL_atomic_max_ru32:
|
||||
IntNo = AMDILISD::ATOM_R_UMAX; break;
|
||||
case AMDGPUIntrinsic::AMDIL_atomic_max_ri32_noret:
|
||||
isRet = false;
|
||||
IntNo = AMDILISD::ATOM_R_MAX_NORET; break;
|
||||
case AMDGPUIntrinsic::AMDIL_atomic_max_ru32_noret:
|
||||
isRet = false;
|
||||
IntNo = AMDILISD::ATOM_R_UMAX_NORET; break;
|
||||
case AMDGPUIntrinsic::AMDIL_atomic_min_gi32:
|
||||
IntNo = AMDILISD::ATOM_G_MIN; break;
|
||||
case AMDGPUIntrinsic::AMDIL_atomic_min_gu32:
|
||||
IntNo = AMDILISD::ATOM_G_UMIN; break;
|
||||
case AMDGPUIntrinsic::AMDIL_atomic_min_gi32_noret:
|
||||
isRet = false;
|
||||
IntNo = AMDILISD::ATOM_G_MIN_NORET; break;
|
||||
case AMDGPUIntrinsic::AMDIL_atomic_min_gu32_noret:
|
||||
isRet = false;
|
||||
IntNo = AMDILISD::ATOM_G_UMIN_NORET; break;
|
||||
case AMDGPUIntrinsic::AMDIL_atomic_min_li32:
|
||||
IntNo = AMDILISD::ATOM_L_MIN; break;
|
||||
case AMDGPUIntrinsic::AMDIL_atomic_min_lu32:
|
||||
IntNo = AMDILISD::ATOM_L_UMIN; break;
|
||||
case AMDGPUIntrinsic::AMDIL_atomic_min_li32_noret:
|
||||
isRet = false;
|
||||
IntNo = AMDILISD::ATOM_L_MIN_NORET; break;
|
||||
case AMDGPUIntrinsic::AMDIL_atomic_min_lu32_noret:
|
||||
isRet = false;
|
||||
IntNo = AMDILISD::ATOM_L_UMIN_NORET; break;
|
||||
case AMDGPUIntrinsic::AMDIL_atomic_min_ri32:
|
||||
IntNo = AMDILISD::ATOM_R_MIN; break;
|
||||
case AMDGPUIntrinsic::AMDIL_atomic_min_ru32:
|
||||
IntNo = AMDILISD::ATOM_R_UMIN; break;
|
||||
case AMDGPUIntrinsic::AMDIL_atomic_min_ri32_noret:
|
||||
isRet = false;
|
||||
IntNo = AMDILISD::ATOM_R_MIN_NORET; break;
|
||||
case AMDGPUIntrinsic::AMDIL_atomic_min_ru32_noret:
|
||||
isRet = false;
|
||||
IntNo = AMDILISD::ATOM_R_UMIN_NORET; break;
|
||||
case AMDGPUIntrinsic::AMDIL_atomic_or_gi32:
|
||||
case AMDGPUIntrinsic::AMDIL_atomic_or_gu32:
|
||||
IntNo = AMDILISD::ATOM_G_OR; break;
|
||||
case AMDGPUIntrinsic::AMDIL_atomic_or_gi32_noret:
|
||||
case AMDGPUIntrinsic::AMDIL_atomic_or_gu32_noret:
|
||||
isRet = false;
|
||||
IntNo = AMDILISD::ATOM_G_OR_NORET; break;
|
||||
case AMDGPUIntrinsic::AMDIL_atomic_or_li32:
|
||||
case AMDGPUIntrinsic::AMDIL_atomic_or_lu32:
|
||||
IntNo = AMDILISD::ATOM_L_OR; break;
|
||||
case AMDGPUIntrinsic::AMDIL_atomic_or_li32_noret:
|
||||
case AMDGPUIntrinsic::AMDIL_atomic_or_lu32_noret:
|
||||
isRet = false;
|
||||
IntNo = AMDILISD::ATOM_L_OR_NORET; break;
|
||||
case AMDGPUIntrinsic::AMDIL_atomic_or_ri32:
|
||||
case AMDGPUIntrinsic::AMDIL_atomic_or_ru32:
|
||||
IntNo = AMDILISD::ATOM_R_OR; break;
|
||||
case AMDGPUIntrinsic::AMDIL_atomic_or_ri32_noret:
|
||||
case AMDGPUIntrinsic::AMDIL_atomic_or_ru32_noret:
|
||||
isRet = false;
|
||||
IntNo = AMDILISD::ATOM_R_OR_NORET; break;
|
||||
case AMDGPUIntrinsic::AMDIL_atomic_sub_gi32:
|
||||
case AMDGPUIntrinsic::AMDIL_atomic_sub_gu32:
|
||||
IntNo = AMDILISD::ATOM_G_SUB; break;
|
||||
case AMDGPUIntrinsic::AMDIL_atomic_sub_gi32_noret:
|
||||
case AMDGPUIntrinsic::AMDIL_atomic_sub_gu32_noret:
|
||||
isRet = false;
|
||||
IntNo = AMDILISD::ATOM_G_SUB_NORET; break;
|
||||
case AMDGPUIntrinsic::AMDIL_atomic_sub_li32:
|
||||
case AMDGPUIntrinsic::AMDIL_atomic_sub_lu32:
|
||||
IntNo = AMDILISD::ATOM_L_SUB; break;
|
||||
case AMDGPUIntrinsic::AMDIL_atomic_sub_li32_noret:
|
||||
case AMDGPUIntrinsic::AMDIL_atomic_sub_lu32_noret:
|
||||
isRet = false;
|
||||
IntNo = AMDILISD::ATOM_L_SUB_NORET; break;
|
||||
case AMDGPUIntrinsic::AMDIL_atomic_sub_ri32:
|
||||
case AMDGPUIntrinsic::AMDIL_atomic_sub_ru32:
|
||||
IntNo = AMDILISD::ATOM_R_SUB; break;
|
||||
case AMDGPUIntrinsic::AMDIL_atomic_sub_ri32_noret:
|
||||
case AMDGPUIntrinsic::AMDIL_atomic_sub_ru32_noret:
|
||||
isRet = false;
|
||||
IntNo = AMDILISD::ATOM_R_SUB_NORET; break;
|
||||
case AMDGPUIntrinsic::AMDIL_atomic_rsub_gi32:
|
||||
case AMDGPUIntrinsic::AMDIL_atomic_rsub_gu32:
|
||||
IntNo = AMDILISD::ATOM_G_RSUB; break;
|
||||
case AMDGPUIntrinsic::AMDIL_atomic_rsub_gi32_noret:
|
||||
case AMDGPUIntrinsic::AMDIL_atomic_rsub_gu32_noret:
|
||||
isRet = false;
|
||||
IntNo = AMDILISD::ATOM_G_RSUB_NORET; break;
|
||||
case AMDGPUIntrinsic::AMDIL_atomic_rsub_li32:
|
||||
case AMDGPUIntrinsic::AMDIL_atomic_rsub_lu32:
|
||||
IntNo = AMDILISD::ATOM_L_RSUB; break;
|
||||
case AMDGPUIntrinsic::AMDIL_atomic_rsub_li32_noret:
|
||||
case AMDGPUIntrinsic::AMDIL_atomic_rsub_lu32_noret:
|
||||
isRet = false;
|
||||
IntNo = AMDILISD::ATOM_L_RSUB_NORET; break;
|
||||
case AMDGPUIntrinsic::AMDIL_atomic_rsub_ri32:
|
||||
case AMDGPUIntrinsic::AMDIL_atomic_rsub_ru32:
|
||||
IntNo = AMDILISD::ATOM_R_RSUB; break;
|
||||
case AMDGPUIntrinsic::AMDIL_atomic_rsub_ri32_noret:
|
||||
case AMDGPUIntrinsic::AMDIL_atomic_rsub_ru32_noret:
|
||||
isRet = false;
|
||||
IntNo = AMDILISD::ATOM_R_RSUB_NORET; break;
|
||||
case AMDGPUIntrinsic::AMDIL_atomic_xchg_gf32:
|
||||
bitCastToInt = true;
|
||||
case AMDGPUIntrinsic::AMDIL_atomic_xchg_gi32:
|
||||
case AMDGPUIntrinsic::AMDIL_atomic_xchg_gu32:
|
||||
IntNo = AMDILISD::ATOM_G_XCHG; break;
|
||||
case AMDGPUIntrinsic::AMDIL_atomic_xchg_gf32_noret:
|
||||
bitCastToInt = true;
|
||||
case AMDGPUIntrinsic::AMDIL_atomic_xchg_gi32_noret:
|
||||
case AMDGPUIntrinsic::AMDIL_atomic_xchg_gu32_noret:
|
||||
isRet = false;
|
||||
IntNo = AMDILISD::ATOM_G_XCHG_NORET; break;
|
||||
case AMDGPUIntrinsic::AMDIL_atomic_xchg_lf32:
|
||||
bitCastToInt = true;
|
||||
case AMDGPUIntrinsic::AMDIL_atomic_xchg_li32:
|
||||
case AMDGPUIntrinsic::AMDIL_atomic_xchg_lu32:
|
||||
IntNo = AMDILISD::ATOM_L_XCHG; break;
|
||||
case AMDGPUIntrinsic::AMDIL_atomic_xchg_lf32_noret:
|
||||
bitCastToInt = true;
|
||||
case AMDGPUIntrinsic::AMDIL_atomic_xchg_li32_noret:
|
||||
case AMDGPUIntrinsic::AMDIL_atomic_xchg_lu32_noret:
|
||||
isRet = false;
|
||||
IntNo = AMDILISD::ATOM_L_XCHG_NORET; break;
|
||||
case AMDGPUIntrinsic::AMDIL_atomic_xchg_rf32:
|
||||
bitCastToInt = true;
|
||||
case AMDGPUIntrinsic::AMDIL_atomic_xchg_ri32:
|
||||
case AMDGPUIntrinsic::AMDIL_atomic_xchg_ru32:
|
||||
IntNo = AMDILISD::ATOM_R_XCHG; break;
|
||||
case AMDGPUIntrinsic::AMDIL_atomic_xchg_rf32_noret:
|
||||
bitCastToInt = true;
|
||||
case AMDGPUIntrinsic::AMDIL_atomic_xchg_ri32_noret:
|
||||
case AMDGPUIntrinsic::AMDIL_atomic_xchg_ru32_noret:
|
||||
isRet = false;
|
||||
IntNo = AMDILISD::ATOM_R_XCHG_NORET; break;
|
||||
case AMDGPUIntrinsic::AMDIL_atomic_xor_gi32:
|
||||
case AMDGPUIntrinsic::AMDIL_atomic_xor_gu32:
|
||||
IntNo = AMDILISD::ATOM_G_XOR; break;
|
||||
case AMDGPUIntrinsic::AMDIL_atomic_xor_gi32_noret:
|
||||
case AMDGPUIntrinsic::AMDIL_atomic_xor_gu32_noret:
|
||||
isRet = false;
|
||||
IntNo = AMDILISD::ATOM_G_XOR_NORET; break;
|
||||
case AMDGPUIntrinsic::AMDIL_atomic_xor_li32:
|
||||
case AMDGPUIntrinsic::AMDIL_atomic_xor_lu32:
|
||||
IntNo = AMDILISD::ATOM_L_XOR; break;
|
||||
case AMDGPUIntrinsic::AMDIL_atomic_xor_li32_noret:
|
||||
case AMDGPUIntrinsic::AMDIL_atomic_xor_lu32_noret:
|
||||
isRet = false;
|
||||
IntNo = AMDILISD::ATOM_L_XOR_NORET; break;
|
||||
case AMDGPUIntrinsic::AMDIL_atomic_xor_ri32:
|
||||
case AMDGPUIntrinsic::AMDIL_atomic_xor_ru32:
|
||||
IntNo = AMDILISD::ATOM_R_XOR; break;
|
||||
case AMDGPUIntrinsic::AMDIL_atomic_xor_ri32_noret:
|
||||
case AMDGPUIntrinsic::AMDIL_atomic_xor_ru32_noret:
|
||||
isRet = false;
|
||||
IntNo = AMDILISD::ATOM_R_XOR_NORET; break;
|
||||
case AMDGPUIntrinsic::AMDIL_append_alloc_i32:
|
||||
IntNo = AMDILISD::APPEND_ALLOC; break;
|
||||
case AMDGPUIntrinsic::AMDIL_append_alloc_i32_noret:
|
||||
isRet = false;
|
||||
IntNo = AMDILISD::APPEND_ALLOC_NORET; break;
|
||||
case AMDGPUIntrinsic::AMDIL_append_consume_i32:
|
||||
IntNo = AMDILISD::APPEND_CONSUME; break;
|
||||
case AMDGPUIntrinsic::AMDIL_append_consume_i32_noret:
|
||||
isRet = false;
|
||||
IntNo = AMDILISD::APPEND_CONSUME_NORET; break;
|
||||
};
|
||||
|
||||
Info.opc = IntNo;
|
||||
Info.memVT = (bitCastToInt) ? MVT::f32 : MVT::i32;
|
||||
Info.ptrVal = I.getOperand(0);
|
||||
Info.offset = 0;
|
||||
Info.align = 4;
|
||||
Info.vol = true;
|
||||
Info.readMem = isRet;
|
||||
Info.writeMem = true;
|
||||
return true;
|
||||
return false;
|
||||
}
|
||||
// The backend supports 32 and 64 bit floating point immediates
|
||||
bool
|
||||
|
|
|
|||
|
|
@ -27,60 +27,13 @@ namespace llvm
|
|||
enum
|
||||
{
|
||||
FIRST_NUMBER = ISD::BUILTIN_OP_END,
|
||||
INTTOANY, // Dummy instruction that takes an int and goes to
|
||||
// any type converts the SDNode to an int
|
||||
DP_TO_FP, // Conversion from 64bit FP to 32bit FP
|
||||
FP_TO_DP, // Conversion from 32bit FP to 64bit FP
|
||||
BITCONV, // instruction that converts from any type to any type
|
||||
CMOV, // 32bit FP Conditional move instruction
|
||||
CMOVLOG, // 32bit FP Conditional move logical instruction
|
||||
SELECT, // 32bit FP Conditional move logical instruction
|
||||
SETCC, // 32bit FP Conditional move logical instruction
|
||||
ISGN, // 32bit Int Sign instruction
|
||||
INEGATE, // 32bit Int Negation instruction
|
||||
MAD, // 32bit Fused Multiply Add instruction
|
||||
ADD, // 32/64 bit pseudo instruction
|
||||
AND, // 128 bit and instruction
|
||||
OR, // 128 bit or instruction
|
||||
NOT, // 128 bit not instruction
|
||||
XOR, // 128 bit xor instruction
|
||||
MOVE, // generic mov instruction
|
||||
PHIMOVE, // generic phi-node mov instruction
|
||||
VBUILD, // scalar to vector mov instruction
|
||||
VEXTRACT, // extract vector components
|
||||
VINSERT, // insert vector components
|
||||
VCONCAT, // concat a single vector to another vector
|
||||
UMAD, // 32bit UInt Fused Multiply Add instruction
|
||||
CALL, // Function call based on a single integer
|
||||
RET, // Return from a function call
|
||||
SELECT_CC, // Select the correct conditional instruction
|
||||
BRCC, // Select the correct branch instruction
|
||||
CMPCC, // Compare to GPR operands
|
||||
CMPICC, // Compare two GPR operands, set icc.
|
||||
CMPFCC, // Compare two FP operands, set fcc.
|
||||
BRICC, // Branch to dest on icc condition
|
||||
BRFCC, // Branch to dest on fcc condition
|
||||
SELECT_ICC, // Select between two values using the current ICC
|
||||
//flags.
|
||||
SELECT_FCC, // Select between two values using the current FCC
|
||||
//flags.
|
||||
LCREATE, // Create a 64bit integer from two 32 bit integers
|
||||
LCOMPHI, // Get the hi 32 bits from a 64 bit integer
|
||||
LCOMPLO, // Get the lo 32 bits from a 64 bit integer
|
||||
DCREATE, // Create a 64bit float from two 32 bit integers
|
||||
DCOMPHI, // Get the hi 32 bits from a 64 bit float
|
||||
DCOMPLO, // Get the lo 32 bits from a 64 bit float
|
||||
LCREATE2, // Create a 64bit integer from two 32 bit integers
|
||||
LCOMPHI2, // Get the hi 32 bits from a 64 bit integer
|
||||
LCOMPLO2, // Get the lo 32 bits from a 64 bit integer
|
||||
DCREATE2, // Create a 64bit float from two 32 bit integers
|
||||
DCOMPHI2, // Get the hi 32 bits from a 64 bit float
|
||||
DCOMPLO2, // Get the lo 32 bits from a 64 bit float
|
||||
UMUL, // 32bit unsigned multiplication
|
||||
IFFB_HI, // 32bit find first hi bit instruction
|
||||
IFFB_LO, // 32bit find first low bit instruction
|
||||
DIV_INF, // Divide with infinity returned on zero divisor
|
||||
SMAX, // Signed integer max
|
||||
CMP,
|
||||
IL_CC_I_GT,
|
||||
IL_CC_I_LT,
|
||||
|
|
@ -90,119 +43,6 @@ namespace llvm
|
|||
IL_CC_I_NE,
|
||||
RET_FLAG,
|
||||
BRANCH_COND,
|
||||
LOOP_NZERO,
|
||||
LOOP_ZERO,
|
||||
LOOP_CMP,
|
||||
ADDADDR,
|
||||
LAST_NON_MEMORY_OPCODE,
|
||||
// ATOMIC Operations
|
||||
// Global Memory
|
||||
ATOM_G_ADD = ISD::FIRST_TARGET_MEMORY_OPCODE,
|
||||
ATOM_G_AND,
|
||||
ATOM_G_CMPXCHG,
|
||||
ATOM_G_DEC,
|
||||
ATOM_G_INC,
|
||||
ATOM_G_MAX,
|
||||
ATOM_G_UMAX,
|
||||
ATOM_G_MIN,
|
||||
ATOM_G_UMIN,
|
||||
ATOM_G_OR,
|
||||
ATOM_G_SUB,
|
||||
ATOM_G_RSUB,
|
||||
ATOM_G_XCHG,
|
||||
ATOM_G_XOR,
|
||||
ATOM_G_ADD_NORET,
|
||||
ATOM_G_AND_NORET,
|
||||
ATOM_G_CMPXCHG_NORET,
|
||||
ATOM_G_DEC_NORET,
|
||||
ATOM_G_INC_NORET,
|
||||
ATOM_G_MAX_NORET,
|
||||
ATOM_G_UMAX_NORET,
|
||||
ATOM_G_MIN_NORET,
|
||||
ATOM_G_UMIN_NORET,
|
||||
ATOM_G_OR_NORET,
|
||||
ATOM_G_SUB_NORET,
|
||||
ATOM_G_RSUB_NORET,
|
||||
ATOM_G_XCHG_NORET,
|
||||
ATOM_G_XOR_NORET,
|
||||
// Local Memory
|
||||
ATOM_L_ADD,
|
||||
ATOM_L_AND,
|
||||
ATOM_L_CMPXCHG,
|
||||
ATOM_L_DEC,
|
||||
ATOM_L_INC,
|
||||
ATOM_L_MAX,
|
||||
ATOM_L_UMAX,
|
||||
ATOM_L_MIN,
|
||||
ATOM_L_UMIN,
|
||||
ATOM_L_OR,
|
||||
ATOM_L_MSKOR,
|
||||
ATOM_L_SUB,
|
||||
ATOM_L_RSUB,
|
||||
ATOM_L_XCHG,
|
||||
ATOM_L_XOR,
|
||||
ATOM_L_ADD_NORET,
|
||||
ATOM_L_AND_NORET,
|
||||
ATOM_L_CMPXCHG_NORET,
|
||||
ATOM_L_DEC_NORET,
|
||||
ATOM_L_INC_NORET,
|
||||
ATOM_L_MAX_NORET,
|
||||
ATOM_L_UMAX_NORET,
|
||||
ATOM_L_MIN_NORET,
|
||||
ATOM_L_UMIN_NORET,
|
||||
ATOM_L_OR_NORET,
|
||||
ATOM_L_MSKOR_NORET,
|
||||
ATOM_L_SUB_NORET,
|
||||
ATOM_L_RSUB_NORET,
|
||||
ATOM_L_XCHG_NORET,
|
||||
ATOM_L_XOR_NORET,
|
||||
// Region Memory
|
||||
ATOM_R_ADD,
|
||||
ATOM_R_AND,
|
||||
ATOM_R_CMPXCHG,
|
||||
ATOM_R_DEC,
|
||||
ATOM_R_INC,
|
||||
ATOM_R_MAX,
|
||||
ATOM_R_UMAX,
|
||||
ATOM_R_MIN,
|
||||
ATOM_R_UMIN,
|
||||
ATOM_R_OR,
|
||||
ATOM_R_MSKOR,
|
||||
ATOM_R_SUB,
|
||||
ATOM_R_RSUB,
|
||||
ATOM_R_XCHG,
|
||||
ATOM_R_XOR,
|
||||
ATOM_R_ADD_NORET,
|
||||
ATOM_R_AND_NORET,
|
||||
ATOM_R_CMPXCHG_NORET,
|
||||
ATOM_R_DEC_NORET,
|
||||
ATOM_R_INC_NORET,
|
||||
ATOM_R_MAX_NORET,
|
||||
ATOM_R_UMAX_NORET,
|
||||
ATOM_R_MIN_NORET,
|
||||
ATOM_R_UMIN_NORET,
|
||||
ATOM_R_OR_NORET,
|
||||
ATOM_R_MSKOR_NORET,
|
||||
ATOM_R_SUB_NORET,
|
||||
ATOM_R_RSUB_NORET,
|
||||
ATOM_R_XCHG_NORET,
|
||||
ATOM_R_XOR_NORET,
|
||||
// Append buffer
|
||||
APPEND_ALLOC,
|
||||
APPEND_ALLOC_NORET,
|
||||
APPEND_CONSUME,
|
||||
APPEND_CONSUME_NORET,
|
||||
// 2D Images
|
||||
IMAGE2D_READ,
|
||||
IMAGE2D_WRITE,
|
||||
IMAGE2D_INFO0,
|
||||
IMAGE2D_INFO1,
|
||||
// 3D Images
|
||||
IMAGE3D_READ,
|
||||
IMAGE3D_WRITE,
|
||||
IMAGE3D_INFO0,
|
||||
IMAGE3D_INFO1,
|
||||
|
||||
LAST_ISD_NUMBER
|
||||
};
|
||||
} // AMDILISD
|
||||
|
|
|
|||
|
|
@ -27,7 +27,7 @@
|
|||
using namespace llvm;
|
||||
|
||||
AMDILInstrInfo::AMDILInstrInfo(TargetMachine &tm)
|
||||
: AMDILGenInstrInfo(AMDIL::ADJCALLSTACKDOWN, AMDIL::ADJCALLSTACKUP),
|
||||
: AMDILGenInstrInfo(),
|
||||
RI(tm, *this),
|
||||
TM(tm) {
|
||||
}
|
||||
|
|
@ -154,12 +154,8 @@ unsigned int AMDILInstrInfo::getBranchInstr(const MachineOperand &op) const {
|
|||
|
||||
switch (MI->getDesc().OpInfo->RegClass) {
|
||||
default: // FIXME: fallthrough??
|
||||
case AMDIL::GPRI8RegClassID: return AMDIL::BRANCH_COND_i8;
|
||||
case AMDIL::GPRI16RegClassID: return AMDIL::BRANCH_COND_i16;
|
||||
case AMDIL::GPRI32RegClassID: return AMDIL::BRANCH_COND_i32;
|
||||
case AMDIL::GPRI64RegClassID: return AMDIL::BRANCH_COND_i64;
|
||||
case AMDIL::GPRF32RegClassID: return AMDIL::BRANCH_COND_f32;
|
||||
case AMDIL::GPRF64RegClassID: return AMDIL::BRANCH_COND_f64;
|
||||
};
|
||||
}
|
||||
|
||||
|
|
@ -257,57 +253,12 @@ AMDILInstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
|
|||
|
||||
DebugLoc DL;
|
||||
switch (RC->getID()) {
|
||||
default:
|
||||
Opc = AMDIL::PRIVATESTORE_v4i32;
|
||||
break;
|
||||
case AMDIL::GPRF32RegClassID:
|
||||
Opc = AMDIL::PRIVATESTORE_f32;
|
||||
break;
|
||||
case AMDIL::GPRF64RegClassID:
|
||||
Opc = AMDIL::PRIVATESTORE_f64;
|
||||
break;
|
||||
case AMDIL::GPRI16RegClassID:
|
||||
Opc = AMDIL::PRIVATESTORE_i16;
|
||||
break;
|
||||
case AMDIL::GPRI32RegClassID:
|
||||
Opc = AMDIL::PRIVATESTORE_i32;
|
||||
break;
|
||||
case AMDIL::GPRI8RegClassID:
|
||||
Opc = AMDIL::PRIVATESTORE_i8;
|
||||
break;
|
||||
case AMDIL::GPRI64RegClassID:
|
||||
Opc = AMDIL::PRIVATESTORE_i64;
|
||||
break;
|
||||
case AMDIL::GPRV2F32RegClassID:
|
||||
Opc = AMDIL::PRIVATESTORE_v2f32;
|
||||
break;
|
||||
case AMDIL::GPRV2F64RegClassID:
|
||||
Opc = AMDIL::PRIVATESTORE_v2f64;
|
||||
break;
|
||||
case AMDIL::GPRV2I16RegClassID:
|
||||
Opc = AMDIL::PRIVATESTORE_v2i16;
|
||||
break;
|
||||
case AMDIL::GPRV2I32RegClassID:
|
||||
Opc = AMDIL::PRIVATESTORE_v2i32;
|
||||
break;
|
||||
case AMDIL::GPRV2I8RegClassID:
|
||||
Opc = AMDIL::PRIVATESTORE_v2i8;
|
||||
break;
|
||||
case AMDIL::GPRV2I64RegClassID:
|
||||
Opc = AMDIL::PRIVATESTORE_v2i64;
|
||||
break;
|
||||
case AMDIL::GPRV4F32RegClassID:
|
||||
Opc = AMDIL::PRIVATESTORE_v4f32;
|
||||
break;
|
||||
case AMDIL::GPRV4I16RegClassID:
|
||||
Opc = AMDIL::PRIVATESTORE_v4i16;
|
||||
break;
|
||||
case AMDIL::GPRV4I32RegClassID:
|
||||
Opc = AMDIL::PRIVATESTORE_v4i32;
|
||||
break;
|
||||
case AMDIL::GPRV4I8RegClassID:
|
||||
Opc = AMDIL::PRIVATESTORE_v4i8;
|
||||
break;
|
||||
}
|
||||
if (MI != MBB.end()) DL = MI->getDebugLoc();
|
||||
MachineMemOperand *MMO =
|
||||
|
|
@ -337,57 +288,12 @@ AMDILInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
|
|||
MachineFrameInfo &MFI = *MF.getFrameInfo();
|
||||
DebugLoc DL;
|
||||
switch (RC->getID()) {
|
||||
default:
|
||||
Opc = AMDIL::PRIVATELOAD_v4i32;
|
||||
break;
|
||||
case AMDIL::GPRF32RegClassID:
|
||||
Opc = AMDIL::PRIVATELOAD_f32;
|
||||
break;
|
||||
case AMDIL::GPRF64RegClassID:
|
||||
Opc = AMDIL::PRIVATELOAD_f64;
|
||||
break;
|
||||
case AMDIL::GPRI16RegClassID:
|
||||
Opc = AMDIL::PRIVATELOAD_i16;
|
||||
break;
|
||||
case AMDIL::GPRI32RegClassID:
|
||||
Opc = AMDIL::PRIVATELOAD_i32;
|
||||
break;
|
||||
case AMDIL::GPRI8RegClassID:
|
||||
Opc = AMDIL::PRIVATELOAD_i8;
|
||||
break;
|
||||
case AMDIL::GPRI64RegClassID:
|
||||
Opc = AMDIL::PRIVATELOAD_i64;
|
||||
break;
|
||||
case AMDIL::GPRV2F32RegClassID:
|
||||
Opc = AMDIL::PRIVATELOAD_v2f32;
|
||||
break;
|
||||
case AMDIL::GPRV2F64RegClassID:
|
||||
Opc = AMDIL::PRIVATELOAD_v2f64;
|
||||
break;
|
||||
case AMDIL::GPRV2I16RegClassID:
|
||||
Opc = AMDIL::PRIVATELOAD_v2i16;
|
||||
break;
|
||||
case AMDIL::GPRV2I32RegClassID:
|
||||
Opc = AMDIL::PRIVATELOAD_v2i32;
|
||||
break;
|
||||
case AMDIL::GPRV2I8RegClassID:
|
||||
Opc = AMDIL::PRIVATELOAD_v2i8;
|
||||
break;
|
||||
case AMDIL::GPRV2I64RegClassID:
|
||||
Opc = AMDIL::PRIVATELOAD_v2i64;
|
||||
break;
|
||||
case AMDIL::GPRV4F32RegClassID:
|
||||
Opc = AMDIL::PRIVATELOAD_v4f32;
|
||||
break;
|
||||
case AMDIL::GPRV4I16RegClassID:
|
||||
Opc = AMDIL::PRIVATELOAD_v4i16;
|
||||
break;
|
||||
case AMDIL::GPRV4I32RegClassID:
|
||||
Opc = AMDIL::PRIVATELOAD_v4i32;
|
||||
break;
|
||||
case AMDIL::GPRV4I8RegClassID:
|
||||
Opc = AMDIL::PRIVATELOAD_v4i8;
|
||||
break;
|
||||
}
|
||||
|
||||
MachineMemOperand *MMO =
|
||||
|
|
@ -512,16 +418,6 @@ bool AMDILInstrInfo::isLoadInst(MachineInstr *MI) const {
|
|||
|
||||
bool AMDILInstrInfo::isSWSExtLoadInst(MachineInstr *MI) const
|
||||
{
|
||||
switch (MI->getOpcode()) {
|
||||
default:
|
||||
break;
|
||||
ExpandCaseToByteShortTypes(AMDIL::LOCALLOAD);
|
||||
ExpandCaseToByteShortTypes(AMDIL::REGIONLOAD);
|
||||
ExpandCaseToByteShortTypes(AMDIL::PRIVATELOAD);
|
||||
ExpandCaseToByteShortTypes(AMDIL::CPOOLLOAD);
|
||||
ExpandCaseToByteShortTypes(AMDIL::CONSTANTLOAD);
|
||||
return true;
|
||||
};
|
||||
return false;
|
||||
}
|
||||
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
File diff suppressed because it is too large
Load diff
|
|
@ -7,13 +7,6 @@
|
|||
//
|
||||
//==-----------------------------------------------------------------------===//
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
// Conversion DAG Nodes
|
||||
//===----------------------------------------------------------------------===//
|
||||
// Double to Single conversion
|
||||
def IL_d2f : SDNode<"AMDILISD::DP_TO_FP" , SDTIL_DPToFPOp>;
|
||||
|
||||
def IL_inttoany: SDNode<"AMDILISD::INTTOANY", SDTIL_IntToAny>;
|
||||
//===----------------------------------------------------------------------===//
|
||||
// Flow Control DAG Nodes
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
|
@ -27,299 +20,28 @@ def IL_cmp : SDNode<"AMDILISD::CMP", SDTIL_Cmp>;
|
|||
//===----------------------------------------------------------------------===//
|
||||
// Call/Return DAG Nodes
|
||||
//===----------------------------------------------------------------------===//
|
||||
def IL_callseq_start : SDNode<"ISD::CALLSEQ_START", SDTIL_CallSeqStart,
|
||||
[SDNPHasChain, SDNPOutGlue]>;
|
||||
def IL_callseq_end : SDNode<"ISD::CALLSEQ_END", SDTIL_CallSeqEnd,
|
||||
[SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
|
||||
def IL_call : SDNode<"AMDILISD::CALL", SDTIL_Call,
|
||||
[SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
|
||||
|
||||
def IL_retflag : SDNode<"AMDILISD::RET_FLAG", SDTNone,
|
||||
[SDNPHasChain, SDNPOptInGlue]>;
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
// Arithmetic DAG Nodes
|
||||
//===----------------------------------------------------------------------===//
|
||||
// Address modification nodes
|
||||
def IL_addaddrri : SDNode<"AMDILISD::ADDADDR", SDTIL_AddAddrri,
|
||||
[SDNPCommutative, SDNPAssociative]>;
|
||||
def IL_addaddrir : SDNode<"AMDILISD::ADDADDR", SDTIL_AddAddrir,
|
||||
[SDNPCommutative, SDNPAssociative]>;
|
||||
|
||||
//===--------------------------------------------------------------------===//
|
||||
// Instructions
|
||||
//===--------------------------------------------------------------------===//
|
||||
// Floating point math functions
|
||||
def IL_cmov_logical : SDNode<"AMDILISD::CMOVLOG", SDTIL_GenTernaryOp>;
|
||||
def IL_add : SDNode<"AMDILISD::ADD" , SDTIL_GenBinaryOp>;
|
||||
def IL_cmov : SDNode<"AMDILISD::CMOV" , SDTIL_GenBinaryOp>;
|
||||
def IL_or : SDNode<"AMDILISD::OR" ,SDTIL_GenBinaryOp>;
|
||||
def IL_and : SDNode<"AMDILISD::AND" ,SDTIL_GenBinaryOp>;
|
||||
def IL_xor : SDNode<"AMDILISD::XOR", SDTIL_GenBinaryOp>;
|
||||
def IL_not : SDNode<"AMDILISD::NOT", SDTIL_GenUnaryOp>;
|
||||
def IL_div_inf : SDNode<"AMDILISD::DIV_INF", SDTIL_GenBinaryOp>;
|
||||
def IL_mad : SDNode<"AMDILISD::MAD", SDTIL_GenTernaryOp>;
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
// Integer functions
|
||||
//===----------------------------------------------------------------------===//
|
||||
def IL_inegate : SDNode<"AMDILISD::INEGATE" , SDTIntUnaryOp>;
|
||||
def IL_umul : SDNode<"AMDILISD::UMUL" , SDTIntBinOp,
|
||||
[SDNPCommutative, SDNPAssociative]>;
|
||||
def IL_mov : SDNode<"AMDILISD::MOVE", SDTIL_GenUnaryOp>;
|
||||
def IL_phimov : SDNode<"AMDILISD::PHIMOVE", SDTIL_GenUnaryOp>;
|
||||
def IL_bitconv : SDNode<"AMDILISD::BITCONV", SDTIL_GenBitConv>;
|
||||
def IL_ffb_hi : SDNode<"AMDILISD::IFFB_HI", SDTIL_GenUnaryOp>;
|
||||
def IL_ffb_lo : SDNode<"AMDILISD::IFFB_LO", SDTIL_GenUnaryOp>;
|
||||
def IL_smax : SDNode<"AMDILISD::SMAX", SDTIL_GenBinaryOp>;
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
// Double functions
|
||||
//===----------------------------------------------------------------------===//
|
||||
def IL_dcreate : SDNode<"AMDILISD::DCREATE" , SDTIL_DCreate>;
|
||||
def IL_dcomphi : SDNode<"AMDILISD::DCOMPHI" , SDTIL_DComp>;
|
||||
def IL_dcomplo : SDNode<"AMDILISD::DCOMPLO" , SDTIL_DComp>;
|
||||
def IL_dcreate2 : SDNode<"AMDILISD::DCREATE2" , SDTIL_DCreate2>;
|
||||
def IL_dcomphi2 : SDNode<"AMDILISD::DCOMPHI2" , SDTIL_DComp2>;
|
||||
def IL_dcomplo2 : SDNode<"AMDILISD::DCOMPLO2" , SDTIL_DComp2>;
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
// Long functions
|
||||
//===----------------------------------------------------------------------===//
|
||||
def IL_lcreate : SDNode<"AMDILISD::LCREATE" , SDTIL_LCreate>;
|
||||
def IL_lcreate2 : SDNode<"AMDILISD::LCREATE2" , SDTIL_LCreate2>;
|
||||
def IL_lcomphi : SDNode<"AMDILISD::LCOMPHI" , SDTIL_LComp>;
|
||||
def IL_lcomphi2 : SDNode<"AMDILISD::LCOMPHI2" , SDTIL_LComp2>;
|
||||
def IL_lcomplo : SDNode<"AMDILISD::LCOMPLO" , SDTIL_LComp>;
|
||||
def IL_lcomplo2 : SDNode<"AMDILISD::LCOMPLO2" , SDTIL_LComp2>;
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
// Vector functions
|
||||
//===----------------------------------------------------------------------===//
|
||||
def IL_vbuild : SDNode<"AMDILISD::VBUILD", SDTIL_GenVecBuild,
|
||||
[]>;
|
||||
def IL_vextract : SDNode<"AMDILISD::VEXTRACT", SDTIL_GenVecExtract,
|
||||
[]>;
|
||||
def IL_vinsert : SDNode<"AMDILISD::VINSERT", SDTIL_GenVecInsert,
|
||||
[]>;
|
||||
def IL_vconcat : SDNode<"AMDILISD::VCONCAT", SDTIL_GenVecConcat,
|
||||
[]>;
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
// AMDIL Image Custom SDNodes
|
||||
//===----------------------------------------------------------------------===//
|
||||
def image2d_read : SDNode<"AMDILISD::IMAGE2D_READ", SDTIL_ImageRead,
|
||||
[SDNPHasChain, SDNPMayLoad]>;
|
||||
def image2d_write : SDNode<"AMDILISD::IMAGE2D_WRITE", SDTIL_ImageWrite,
|
||||
[SDNPHasChain, SDNPMayStore]>;
|
||||
def image2d_info0 : SDNode<"AMDILISD::IMAGE2D_INFO0", SDTIL_ImageInfo, []>;
|
||||
def image2d_info1 : SDNode<"AMDILISD::IMAGE2D_INFO1", SDTIL_ImageInfo, []>;
|
||||
def image3d_read : SDNode<"AMDILISD::IMAGE3D_READ", SDTIL_ImageRead,
|
||||
[SDNPHasChain, SDNPMayLoad]>;
|
||||
def image3d_write : SDNode<"AMDILISD::IMAGE3D_WRITE", SDTIL_ImageWrite3D,
|
||||
[SDNPHasChain, SDNPMayStore]>;
|
||||
def image3d_info0 : SDNode<"AMDILISD::IMAGE3D_INFO0", SDTIL_ImageInfo, []>;
|
||||
def image3d_info1 : SDNode<"AMDILISD::IMAGE3D_INFO1", SDTIL_ImageInfo, []>;
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
// AMDIL Atomic Custom SDNodes
|
||||
//===----------------------------------------------------------------------===//
|
||||
//===-------------- 32 bit global atomics with return values --------------===//
|
||||
def atom_g_add : SDNode<"AMDILISD::ATOM_G_ADD", SDTIL_BinAtom,
|
||||
[SDNPHasChain, SDNPMayLoad, SDNPMayStore, SDNPMemOperand]>;
|
||||
def atom_g_and : SDNode<"AMDILISD::ATOM_G_AND", SDTIL_BinAtom,
|
||||
[SDNPHasChain, SDNPMayLoad, SDNPMayStore, SDNPMemOperand]>;
|
||||
def atom_g_cmpxchg : SDNode<"AMDILISD::ATOM_G_CMPXCHG", SDTIL_TriAtom,
|
||||
[SDNPHasChain, SDNPMayLoad, SDNPMayStore, SDNPMemOperand]>;
|
||||
def atom_g_dec : SDNode<"AMDILISD::ATOM_G_DEC", SDTIL_BinAtom,
|
||||
[SDNPHasChain, SDNPMayLoad, SDNPMayStore, SDNPMemOperand]>;
|
||||
def atom_g_inc : SDNode<"AMDILISD::ATOM_G_INC", SDTIL_BinAtom,
|
||||
[SDNPHasChain, SDNPMayLoad, SDNPMayStore, SDNPMemOperand]>;
|
||||
def atom_g_max : SDNode<"AMDILISD::ATOM_G_MAX", SDTIL_BinAtom,
|
||||
[SDNPHasChain, SDNPMayLoad, SDNPMayStore, SDNPMemOperand]>;
|
||||
def atom_g_umax : SDNode<"AMDILISD::ATOM_G_UMAX", SDTIL_BinAtom,
|
||||
[SDNPHasChain, SDNPMayLoad, SDNPMayStore, SDNPMemOperand]>;
|
||||
def atom_g_min : SDNode<"AMDILISD::ATOM_G_MIN", SDTIL_BinAtom,
|
||||
[SDNPHasChain, SDNPMayLoad, SDNPMayStore, SDNPMemOperand]>;
|
||||
def atom_g_umin : SDNode<"AMDILISD::ATOM_G_UMIN", SDTIL_BinAtom,
|
||||
[SDNPHasChain, SDNPMayLoad, SDNPMayStore, SDNPMemOperand]>;
|
||||
def atom_g_or : SDNode<"AMDILISD::ATOM_G_OR", SDTIL_BinAtom,
|
||||
[SDNPHasChain, SDNPMayLoad, SDNPMayStore, SDNPMemOperand]>;
|
||||
def atom_g_sub : SDNode<"AMDILISD::ATOM_G_SUB", SDTIL_BinAtom,
|
||||
[SDNPHasChain, SDNPMayLoad, SDNPMayStore, SDNPMemOperand]>;
|
||||
def atom_g_rsub : SDNode<"AMDILISD::ATOM_G_RSUB", SDTIL_BinAtom,
|
||||
[SDNPHasChain, SDNPMayLoad, SDNPMayStore, SDNPMemOperand]>;
|
||||
def atom_g_xchg : SDNode<"AMDILISD::ATOM_G_XCHG", SDTIL_BinAtom,
|
||||
[SDNPHasChain, SDNPMayLoad, SDNPMayStore, SDNPMemOperand]>;
|
||||
def atom_g_xor : SDNode<"AMDILISD::ATOM_G_XOR", SDTIL_BinAtom,
|
||||
[SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
|
||||
|
||||
//===------------- 32 bit global atomics without return values ------------===//
|
||||
def atom_g_add_noret : SDNode<"AMDILISD::ATOM_G_ADD_NORET", SDTIL_BinAtom,
|
||||
[SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
|
||||
def atom_g_and_noret : SDNode<"AMDILISD::ATOM_G_AND_NORET", SDTIL_BinAtom,
|
||||
[SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
|
||||
def atom_g_cmpxchg_noret : SDNode<"AMDILISD::ATOM_G_CMPXCHG_NORET",
|
||||
SDTIL_TriAtom, [SDNPHasChain, SDNPMayLoad, SDNPMayStore, SDNPMemOperand]>;
|
||||
def atom_g_cmp_noret : SDNode<"AMDILISD::ATOM_G_CMPXCHG_NORET",
|
||||
SDTIL_TriAtom, [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
|
||||
def atom_g_dec_noret : SDNode<"AMDILISD::ATOM_G_DEC_NORET", SDTIL_BinAtom,
|
||||
[SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
|
||||
def atom_g_inc_noret : SDNode<"AMDILISD::ATOM_G_INC_NORET", SDTIL_BinAtom,
|
||||
[SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
|
||||
def atom_g_max_noret : SDNode<"AMDILISD::ATOM_G_MAX_NORET", SDTIL_BinAtom,
|
||||
[SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
|
||||
def atom_g_umax_noret: SDNode<"AMDILISD::ATOM_G_UMAX_NORET",
|
||||
SDTIL_BinAtom, [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
|
||||
def atom_g_min_noret : SDNode<"AMDILISD::ATOM_G_MIN_NORET", SDTIL_BinAtom,
|
||||
[SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
|
||||
def atom_g_umin_noret: SDNode<"AMDILISD::ATOM_G_UMIN_NORET",
|
||||
SDTIL_BinAtom, [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
|
||||
def atom_g_or_noret : SDNode<"AMDILISD::ATOM_G_OR_NORET", SDTIL_BinAtom,
|
||||
[SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
|
||||
def atom_g_sub_noret : SDNode<"AMDILISD::ATOM_G_SUB_NORET", SDTIL_BinAtom,
|
||||
[SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
|
||||
def atom_g_rsub_noret : SDNode<"AMDILISD::ATOM_G_RSUB_NORET", SDTIL_BinAtom,
|
||||
[SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
|
||||
def atom_g_xchg_noret: SDNode<"AMDILISD::ATOM_G_XCHG_NORET",
|
||||
SDTIL_BinAtom, [SDNPHasChain, SDNPMayLoad, SDNPMayStore, SDNPMemOperand]>;
|
||||
def atom_g_xor_noret : SDNode<"AMDILISD::ATOM_G_XOR_NORET", SDTIL_BinAtom,
|
||||
[SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
|
||||
|
||||
//===--------------- 32 bit local atomics with return values --------------===//
|
||||
def atom_l_add : SDNode<"AMDILISD::ATOM_L_ADD", SDTIL_BinAtom,
|
||||
[SDNPHasChain, SDNPMayLoad, SDNPMayStore, SDNPMemOperand]>;
|
||||
def atom_l_and : SDNode<"AMDILISD::ATOM_L_AND", SDTIL_BinAtom,
|
||||
[SDNPHasChain, SDNPMayLoad, SDNPMayStore, SDNPMemOperand]>;
|
||||
def atom_l_cmpxchg : SDNode<"AMDILISD::ATOM_L_CMPXCHG", SDTIL_TriAtom,
|
||||
[SDNPHasChain, SDNPMayLoad, SDNPMayStore, SDNPMemOperand]>;
|
||||
def atom_l_dec : SDNode<"AMDILISD::ATOM_L_DEC", SDTIL_BinAtom,
|
||||
[SDNPHasChain, SDNPMayLoad, SDNPMayStore, SDNPMemOperand]>;
|
||||
def atom_l_inc : SDNode<"AMDILISD::ATOM_L_INC", SDTIL_BinAtom,
|
||||
[SDNPHasChain, SDNPMayLoad, SDNPMayStore, SDNPMemOperand]>;
|
||||
def atom_l_max : SDNode<"AMDILISD::ATOM_L_MAX", SDTIL_BinAtom,
|
||||
[SDNPHasChain, SDNPMayLoad, SDNPMayStore, SDNPMemOperand]>;
|
||||
def atom_l_umax : SDNode<"AMDILISD::ATOM_L_UMAX", SDTIL_BinAtom,
|
||||
[SDNPHasChain, SDNPMayLoad, SDNPMayStore, SDNPMemOperand]>;
|
||||
def atom_l_min : SDNode<"AMDILISD::ATOM_L_MIN", SDTIL_BinAtom,
|
||||
[SDNPHasChain, SDNPMayLoad, SDNPMayStore, SDNPMemOperand]>;
|
||||
def atom_l_umin : SDNode<"AMDILISD::ATOM_L_UMIN", SDTIL_BinAtom,
|
||||
[SDNPHasChain, SDNPMayLoad, SDNPMayStore, SDNPMemOperand]>;
|
||||
def atom_l_or : SDNode<"AMDILISD::ATOM_L_OR", SDTIL_BinAtom,
|
||||
[SDNPHasChain, SDNPMayLoad, SDNPMayStore, SDNPMemOperand]>;
|
||||
def atom_l_mskor : SDNode<"AMDILISD::ATOM_L_MSKOR", SDTIL_TriAtom,
|
||||
[SDNPHasChain, SDNPMayLoad, SDNPMayStore, SDNPMemOperand]>;
|
||||
def atom_l_sub : SDNode<"AMDILISD::ATOM_L_SUB", SDTIL_BinAtom,
|
||||
[SDNPHasChain, SDNPMayLoad, SDNPMayStore, SDNPMemOperand]>;
|
||||
def atom_l_rsub : SDNode<"AMDILISD::ATOM_L_RSUB", SDTIL_BinAtom,
|
||||
[SDNPHasChain, SDNPMayLoad, SDNPMayStore, SDNPMemOperand]>;
|
||||
def atom_l_xchg : SDNode<"AMDILISD::ATOM_L_XCHG", SDTIL_BinAtom,
|
||||
[SDNPHasChain, SDNPMayLoad, SDNPMayStore, SDNPMemOperand]>;
|
||||
def atom_l_xor : SDNode<"AMDILISD::ATOM_L_XOR", SDTIL_BinAtom,
|
||||
[SDNPHasChain, SDNPMayLoad, SDNPMayStore, SDNPMemOperand]>;
|
||||
|
||||
//===-------------- 32 bit local atomics without return values ------------===//
|
||||
def atom_l_add_noret : SDNode<"AMDILISD::ATOM_L_ADD_NORET", SDTIL_BinAtom,
|
||||
[SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
|
||||
def atom_l_and_noret : SDNode<"AMDILISD::ATOM_L_AND_NORET", SDTIL_BinAtom,
|
||||
[SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
|
||||
def atom_l_cmpxchg_noret : SDNode<"AMDILISD::ATOM_L_CMPXCHG_NORET",
|
||||
SDTIL_TriAtom, [SDNPHasChain, SDNPMayLoad, SDNPMayStore, SDNPMemOperand]>;
|
||||
def atom_l_dec_noret : SDNode<"AMDILISD::ATOM_L_DEC_NORET", SDTIL_BinAtom,
|
||||
[SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
|
||||
def atom_l_inc_noret : SDNode<"AMDILISD::ATOM_L_INC_NORET", SDTIL_BinAtom,
|
||||
[SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
|
||||
def atom_l_max_noret : SDNode<"AMDILISD::ATOM_L_MAX_NORET", SDTIL_BinAtom,
|
||||
[SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
|
||||
def atom_l_umax_noret: SDNode<"AMDILISD::ATOM_L_UMAX_NORET",
|
||||
SDTIL_BinAtom, [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
|
||||
def atom_l_min_noret : SDNode<"AMDILISD::ATOM_L_MIN_NORET", SDTIL_BinAtom,
|
||||
[SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
|
||||
def atom_l_umin_noret: SDNode<"AMDILISD::ATOM_L_UMIN_NORET",
|
||||
SDTIL_BinAtom, [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
|
||||
def atom_l_or_noret : SDNode<"AMDILISD::ATOM_L_OR_NORET", SDTIL_BinAtom,
|
||||
[SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
|
||||
def atom_l_mskor_noret : SDNode<"AMDILISD::ATOM_L_MSKOR_NORET",
|
||||
SDTIL_TriAtom, [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
|
||||
def atom_l_sub_noret : SDNode<"AMDILISD::ATOM_L_SUB_NORET", SDTIL_BinAtom,
|
||||
[SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
|
||||
def atom_l_rsub_noret : SDNode<"AMDILISD::ATOM_L_RSUB_NORET",
|
||||
SDTIL_BinAtom, [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
|
||||
def atom_l_xchg_noret: SDNode<"AMDILISD::ATOM_L_XCHG_NORET",
|
||||
SDTIL_BinAtom, [SDNPHasChain, SDNPMayLoad, SDNPMayStore, SDNPMemOperand]>;
|
||||
def atom_l_xor_noret : SDNode<"AMDILISD::ATOM_L_XOR_NORET", SDTIL_BinAtom,
|
||||
[SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
|
||||
|
||||
//===--------------- 32 bit local atomics with return values --------------===//
|
||||
def atom_r_add : SDNode<"AMDILISD::ATOM_R_ADD", SDTIL_BinAtom,
|
||||
[SDNPHasChain, SDNPMayLoad, SDNPMayStore, SDNPMemOperand]>;
|
||||
def atom_r_and : SDNode<"AMDILISD::ATOM_R_AND", SDTIL_BinAtom,
|
||||
[SDNPHasChain, SDNPMayLoad, SDNPMayStore, SDNPMemOperand]>;
|
||||
def atom_r_cmpxchg : SDNode<"AMDILISD::ATOM_R_CMPXCHG", SDTIL_TriAtom,
|
||||
[SDNPHasChain, SDNPMayLoad, SDNPMayStore, SDNPMemOperand]>;
|
||||
def atom_r_dec : SDNode<"AMDILISD::ATOM_R_DEC", SDTIL_BinAtom,
|
||||
[SDNPHasChain, SDNPMayLoad, SDNPMayStore, SDNPMemOperand]>;
|
||||
def atom_r_inc : SDNode<"AMDILISD::ATOM_R_INC", SDTIL_BinAtom,
|
||||
[SDNPHasChain, SDNPMayLoad, SDNPMayStore, SDNPMemOperand]>;
|
||||
def atom_r_max : SDNode<"AMDILISD::ATOM_R_MAX", SDTIL_BinAtom,
|
||||
[SDNPHasChain, SDNPMayLoad, SDNPMayStore, SDNPMemOperand]>;
|
||||
def atom_r_umax : SDNode<"AMDILISD::ATOM_R_UMAX", SDTIL_BinAtom,
|
||||
[SDNPHasChain, SDNPMayLoad, SDNPMayStore, SDNPMemOperand]>;
|
||||
def atom_r_min : SDNode<"AMDILISD::ATOM_R_MIN", SDTIL_BinAtom,
|
||||
[SDNPHasChain, SDNPMayLoad, SDNPMayStore, SDNPMemOperand]>;
|
||||
def atom_r_umin : SDNode<"AMDILISD::ATOM_R_UMIN", SDTIL_BinAtom,
|
||||
[SDNPHasChain, SDNPMayLoad, SDNPMayStore, SDNPMemOperand]>;
|
||||
def atom_r_or : SDNode<"AMDILISD::ATOM_R_OR", SDTIL_BinAtom,
|
||||
[SDNPHasChain, SDNPMayLoad, SDNPMayStore, SDNPMemOperand]>;
|
||||
def atom_r_mskor : SDNode<"AMDILISD::ATOM_R_MSKOR", SDTIL_TriAtom,
|
||||
[SDNPHasChain, SDNPMayLoad, SDNPMayStore, SDNPMemOperand]>;
|
||||
def atom_r_sub : SDNode<"AMDILISD::ATOM_R_SUB", SDTIL_BinAtom,
|
||||
[SDNPHasChain, SDNPMayLoad, SDNPMayStore, SDNPMemOperand]>;
|
||||
def atom_r_rsub : SDNode<"AMDILISD::ATOM_R_RSUB", SDTIL_BinAtom,
|
||||
[SDNPHasChain, SDNPMayLoad, SDNPMayStore, SDNPMemOperand]>;
|
||||
def atom_r_xchg : SDNode<"AMDILISD::ATOM_R_XCHG", SDTIL_BinAtom,
|
||||
[SDNPHasChain, SDNPMayLoad, SDNPMayStore, SDNPMemOperand]>;
|
||||
def atom_r_xor : SDNode<"AMDILISD::ATOM_R_XOR", SDTIL_BinAtom,
|
||||
[SDNPHasChain, SDNPMayLoad, SDNPMayStore, SDNPMemOperand]>;
|
||||
|
||||
//===-------------- 32 bit local atomics without return values ------------===//
|
||||
def atom_r_add_noret : SDNode<"AMDILISD::ATOM_R_ADD_NORET", SDTIL_BinAtom,
|
||||
[SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
|
||||
def atom_r_and_noret : SDNode<"AMDILISD::ATOM_R_AND_NORET", SDTIL_BinAtom,
|
||||
[SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
|
||||
def atom_r_cmpxchg_noret : SDNode<"AMDILISD::ATOM_R_CMPXCHG_NORET",
|
||||
SDTIL_TriAtom, [SDNPHasChain, SDNPMayLoad, SDNPMayStore, SDNPMemOperand]>;
|
||||
def atom_r_dec_noret : SDNode<"AMDILISD::ATOM_R_DEC_NORET", SDTIL_BinAtom,
|
||||
[SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
|
||||
def atom_r_inc_noret : SDNode<"AMDILISD::ATOM_R_INC_NORET", SDTIL_BinAtom,
|
||||
[SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
|
||||
def atom_r_max_noret : SDNode<"AMDILISD::ATOM_R_MAX_NORET", SDTIL_BinAtom,
|
||||
[SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
|
||||
def atom_r_umax_noret: SDNode<"AMDILISD::ATOM_R_UMAX_NORET",
|
||||
SDTIL_BinAtom, [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
|
||||
def atom_r_min_noret : SDNode<"AMDILISD::ATOM_R_MIN_NORET", SDTIL_BinAtom,
|
||||
[SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
|
||||
def atom_r_umin_noret: SDNode<"AMDILISD::ATOM_R_UMIN_NORET",
|
||||
SDTIL_BinAtom, [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
|
||||
def atom_r_or_noret : SDNode<"AMDILISD::ATOM_R_OR_NORET", SDTIL_BinAtom,
|
||||
[SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
|
||||
def atom_r_mskor_noret : SDNode<"AMDILISD::ATOM_R_MSKOR_NORET", SDTIL_TriAtom,
|
||||
[SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
|
||||
def atom_r_sub_noret : SDNode<"AMDILISD::ATOM_R_SUB_NORET", SDTIL_BinAtom,
|
||||
[SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
|
||||
def atom_r_rsub_noret : SDNode<"AMDILISD::ATOM_R_RSUB_NORET", SDTIL_BinAtom,
|
||||
[SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
|
||||
def atom_r_xchg_noret: SDNode<"AMDILISD::ATOM_R_XCHG_NORET",
|
||||
SDTIL_BinAtom, [SDNPHasChain, SDNPMayLoad, SDNPMayStore, SDNPMemOperand]>;
|
||||
def atom_r_xor_noret : SDNode<"AMDILISD::ATOM_R_XOR_NORET", SDTIL_BinAtom,
|
||||
[SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
|
||||
|
||||
//===--------------- 32 bit atomic counter instructions -------------------===//
|
||||
def append_alloc : SDNode<"AMDILISD::APPEND_ALLOC", SDTIL_Append,
|
||||
[SDNPHasChain, SDNPMayLoad, SDNPMayStore]>;
|
||||
def append_consume : SDNode<"AMDILISD::APPEND_CONSUME", SDTIL_Append,
|
||||
[SDNPHasChain, SDNPMayLoad, SDNPMayStore]>;
|
||||
def append_alloc_noret : SDNode<"AMDILISD::APPEND_ALLOC_NORET", SDTIL_Append,
|
||||
[SDNPHasChain, SDNPMayStore]>;
|
||||
def append_consume_noret : SDNode<"AMDILISD::APPEND_CONSUME_NORET",
|
||||
SDTIL_Append, [SDNPHasChain, SDNPMayStore]>;
|
||||
|
|
|
|||
|
|
@ -15,11 +15,6 @@ def MEMI32 : Operand<i32> {
|
|||
let MIOperandInfo = (ops GPRI32, GPRI32);
|
||||
}
|
||||
|
||||
def MEMI64 : Operand<i64> {
|
||||
let PrintMethod = "printMemOperand";
|
||||
let MIOperandInfo = (ops GPRI64, GPRI64);
|
||||
}
|
||||
|
||||
// Call target types
|
||||
def calltarget : Operand<i32>;
|
||||
def brtarget : Operand<OtherVT>;
|
||||
|
|
|
|||
|
|
@ -40,753 +40,6 @@ def R17 : AMDILReg<17, "r17">, DwarfRegNum<[17]>;
|
|||
def R18 : AMDILReg<18, "r18">, DwarfRegNum<[18]>;
|
||||
def R19 : AMDILReg<19, "r19">, DwarfRegNum<[19]>;
|
||||
def R20 : AMDILReg<20, "r20">, DwarfRegNum<[20]>;
|
||||
def R21 : AMDILReg<21, "r21">, DwarfRegNum<[21]>;
|
||||
def R22 : AMDILReg<22, "r22">, DwarfRegNum<[22]>;
|
||||
def R23 : AMDILReg<23, "r23">, DwarfRegNum<[23]>;
|
||||
def R24 : AMDILReg<24, "r24">, DwarfRegNum<[24]>;
|
||||
def R25 : AMDILReg<25, "r25">, DwarfRegNum<[25]>;
|
||||
def R26 : AMDILReg<26, "r26">, DwarfRegNum<[26]>;
|
||||
def R27 : AMDILReg<27, "r27">, DwarfRegNum<[27]>;
|
||||
def R28 : AMDILReg<28, "r28">, DwarfRegNum<[28]>;
|
||||
def R29 : AMDILReg<29, "r29">, DwarfRegNum<[29]>;
|
||||
def R30 : AMDILReg<30, "r30">, DwarfRegNum<[30]>;
|
||||
def R31 : AMDILReg<31, "r31">, DwarfRegNum<[31]>;
|
||||
def R32 : AMDILReg<32, "r32">, DwarfRegNum<[32]>;
|
||||
def R33 : AMDILReg<33, "r33">, DwarfRegNum<[33]>;
|
||||
def R34 : AMDILReg<34, "r34">, DwarfRegNum<[34]>;
|
||||
def R35 : AMDILReg<35, "r35">, DwarfRegNum<[35]>;
|
||||
def R36 : AMDILReg<36, "r36">, DwarfRegNum<[36]>;
|
||||
def R37 : AMDILReg<37, "r37">, DwarfRegNum<[37]>;
|
||||
def R38 : AMDILReg<38, "r38">, DwarfRegNum<[38]>;
|
||||
def R39 : AMDILReg<39, "r39">, DwarfRegNum<[39]>;
|
||||
def R40 : AMDILReg<40, "r40">, DwarfRegNum<[40]>;
|
||||
def R41 : AMDILReg<41, "r41">, DwarfRegNum<[41]>;
|
||||
def R42 : AMDILReg<42, "r42">, DwarfRegNum<[42]>;
|
||||
def R43 : AMDILReg<43, "r43">, DwarfRegNum<[43]>;
|
||||
def R44 : AMDILReg<44, "r44">, DwarfRegNum<[44]>;
|
||||
def R45 : AMDILReg<45, "r45">, DwarfRegNum<[45]>;
|
||||
def R46 : AMDILReg<46, "r46">, DwarfRegNum<[46]>;
|
||||
def R47 : AMDILReg<47, "r47">, DwarfRegNum<[47]>;
|
||||
def R48 : AMDILReg<48, "r48">, DwarfRegNum<[48]>;
|
||||
def R49 : AMDILReg<49, "r49">, DwarfRegNum<[49]>;
|
||||
def R50 : AMDILReg<50, "r50">, DwarfRegNum<[50]>;
|
||||
def R51 : AMDILReg<51, "r51">, DwarfRegNum<[51]>;
|
||||
def R52 : AMDILReg<52, "r52">, DwarfRegNum<[52]>;
|
||||
def R53 : AMDILReg<53, "r53">, DwarfRegNum<[53]>;
|
||||
def R54 : AMDILReg<54, "r54">, DwarfRegNum<[54]>;
|
||||
def R55 : AMDILReg<55, "r55">, DwarfRegNum<[55]>;
|
||||
def R56 : AMDILReg<56, "r56">, DwarfRegNum<[56]>;
|
||||
def R57 : AMDILReg<57, "r57">, DwarfRegNum<[57]>;
|
||||
def R58 : AMDILReg<58, "r58">, DwarfRegNum<[58]>;
|
||||
def R59 : AMDILReg<59, "r59">, DwarfRegNum<[59]>;
|
||||
def R60 : AMDILReg<60, "r60">, DwarfRegNum<[60]>;
|
||||
def R61 : AMDILReg<61, "r61">, DwarfRegNum<[61]>;
|
||||
def R62 : AMDILReg<62, "r62">, DwarfRegNum<[62]>;
|
||||
def R63 : AMDILReg<63, "r63">, DwarfRegNum<[63]>;
|
||||
def R64 : AMDILReg<64, "r64">, DwarfRegNum<[64]>;
|
||||
def R65 : AMDILReg<65, "r65">, DwarfRegNum<[65]>;
|
||||
def R66 : AMDILReg<66, "r66">, DwarfRegNum<[66]>;
|
||||
def R67 : AMDILReg<67, "r67">, DwarfRegNum<[67]>;
|
||||
def R68 : AMDILReg<68, "r68">, DwarfRegNum<[68]>;
|
||||
def R69 : AMDILReg<69, "r69">, DwarfRegNum<[69]>;
|
||||
def R70 : AMDILReg<70, "r70">, DwarfRegNum<[70]>;
|
||||
def R71 : AMDILReg<71, "r71">, DwarfRegNum<[71]>;
|
||||
def R72 : AMDILReg<72, "r72">, DwarfRegNum<[72]>;
|
||||
def R73 : AMDILReg<73, "r73">, DwarfRegNum<[73]>;
|
||||
def R74 : AMDILReg<74, "r74">, DwarfRegNum<[74]>;
|
||||
def R75 : AMDILReg<75, "r75">, DwarfRegNum<[75]>;
|
||||
def R76 : AMDILReg<76, "r76">, DwarfRegNum<[76]>;
|
||||
def R77 : AMDILReg<77, "r77">, DwarfRegNum<[77]>;
|
||||
def R78 : AMDILReg<78, "r78">, DwarfRegNum<[78]>;
|
||||
def R79 : AMDILReg<79, "r79">, DwarfRegNum<[79]>;
|
||||
def R80 : AMDILReg<80, "r80">, DwarfRegNum<[80]>;
|
||||
def R81 : AMDILReg<81, "r81">, DwarfRegNum<[81]>;
|
||||
def R82 : AMDILReg<82, "r82">, DwarfRegNum<[82]>;
|
||||
def R83 : AMDILReg<83, "r83">, DwarfRegNum<[83]>;
|
||||
def R84 : AMDILReg<84, "r84">, DwarfRegNum<[84]>;
|
||||
def R85 : AMDILReg<85, "r85">, DwarfRegNum<[85]>;
|
||||
def R86 : AMDILReg<86, "r86">, DwarfRegNum<[86]>;
|
||||
def R87 : AMDILReg<87, "r87">, DwarfRegNum<[87]>;
|
||||
def R88 : AMDILReg<88, "r88">, DwarfRegNum<[88]>;
|
||||
def R89 : AMDILReg<89, "r89">, DwarfRegNum<[89]>;
|
||||
def R90 : AMDILReg<90, "r90">, DwarfRegNum<[90]>;
|
||||
def R91 : AMDILReg<91, "r91">, DwarfRegNum<[91]>;
|
||||
def R92 : AMDILReg<92, "r92">, DwarfRegNum<[92]>;
|
||||
def R93 : AMDILReg<93, "r93">, DwarfRegNum<[93]>;
|
||||
def R94 : AMDILReg<94, "r94">, DwarfRegNum<[94]>;
|
||||
def R95 : AMDILReg<95, "r95">, DwarfRegNum<[95]>;
|
||||
def R96 : AMDILReg<96, "r96">, DwarfRegNum<[96]>;
|
||||
def R97 : AMDILReg<97, "r97">, DwarfRegNum<[97]>;
|
||||
def R98 : AMDILReg<98, "r98">, DwarfRegNum<[98]>;
|
||||
def R99 : AMDILReg<99, "r99">, DwarfRegNum<[99]>;
|
||||
def R100 : AMDILReg<100, "r100">, DwarfRegNum<[100]>;
|
||||
def R101 : AMDILReg<101, "r101">, DwarfRegNum<[101]>;
|
||||
def R102 : AMDILReg<102, "r102">, DwarfRegNum<[102]>;
|
||||
def R103 : AMDILReg<103, "r103">, DwarfRegNum<[103]>;
|
||||
def R104 : AMDILReg<104, "r104">, DwarfRegNum<[104]>;
|
||||
def R105 : AMDILReg<105, "r105">, DwarfRegNum<[105]>;
|
||||
def R106 : AMDILReg<106, "r106">, DwarfRegNum<[106]>;
|
||||
def R107 : AMDILReg<107, "r107">, DwarfRegNum<[107]>;
|
||||
def R108 : AMDILReg<108, "r108">, DwarfRegNum<[108]>;
|
||||
def R109 : AMDILReg<109, "r109">, DwarfRegNum<[109]>;
|
||||
def R110 : AMDILReg<110, "r110">, DwarfRegNum<[110]>;
|
||||
def R111 : AMDILReg<111, "r111">, DwarfRegNum<[111]>;
|
||||
def R112 : AMDILReg<112, "r112">, DwarfRegNum<[112]>;
|
||||
def R113 : AMDILReg<113, "r113">, DwarfRegNum<[113]>;
|
||||
def R114 : AMDILReg<114, "r114">, DwarfRegNum<[114]>;
|
||||
def R115 : AMDILReg<115, "r115">, DwarfRegNum<[115]>;
|
||||
def R116 : AMDILReg<116, "r116">, DwarfRegNum<[116]>;
|
||||
def R117 : AMDILReg<117, "r117">, DwarfRegNum<[117]>;
|
||||
def R118 : AMDILReg<118, "r118">, DwarfRegNum<[118]>;
|
||||
def R119 : AMDILReg<119, "r119">, DwarfRegNum<[119]>;
|
||||
def R120 : AMDILReg<120, "r120">, DwarfRegNum<[120]>;
|
||||
def R121 : AMDILReg<121, "r121">, DwarfRegNum<[121]>;
|
||||
def R122 : AMDILReg<122, "r122">, DwarfRegNum<[122]>;
|
||||
def R123 : AMDILReg<123, "r123">, DwarfRegNum<[123]>;
|
||||
def R124 : AMDILReg<124, "r124">, DwarfRegNum<[124]>;
|
||||
def R125 : AMDILReg<125, "r125">, DwarfRegNum<[125]>;
|
||||
def R126 : AMDILReg<126, "r126">, DwarfRegNum<[126]>;
|
||||
def R127 : AMDILReg<127, "r127">, DwarfRegNum<[127]>;
|
||||
def R128 : AMDILReg<128, "r128">, DwarfRegNum<[128]>;
|
||||
def R129 : AMDILReg<129, "r129">, DwarfRegNum<[129]>;
|
||||
def R130 : AMDILReg<130, "r130">, DwarfRegNum<[130]>;
|
||||
def R131 : AMDILReg<131, "r131">, DwarfRegNum<[131]>;
|
||||
def R132 : AMDILReg<132, "r132">, DwarfRegNum<[132]>;
|
||||
def R133 : AMDILReg<133, "r133">, DwarfRegNum<[133]>;
|
||||
def R134 : AMDILReg<134, "r134">, DwarfRegNum<[134]>;
|
||||
def R135 : AMDILReg<135, "r135">, DwarfRegNum<[135]>;
|
||||
def R136 : AMDILReg<136, "r136">, DwarfRegNum<[136]>;
|
||||
def R137 : AMDILReg<137, "r137">, DwarfRegNum<[137]>;
|
||||
def R138 : AMDILReg<138, "r138">, DwarfRegNum<[138]>;
|
||||
def R139 : AMDILReg<139, "r139">, DwarfRegNum<[139]>;
|
||||
def R140 : AMDILReg<140, "r140">, DwarfRegNum<[140]>;
|
||||
def R141 : AMDILReg<141, "r141">, DwarfRegNum<[141]>;
|
||||
def R142 : AMDILReg<142, "r142">, DwarfRegNum<[142]>;
|
||||
def R143 : AMDILReg<143, "r143">, DwarfRegNum<[143]>;
|
||||
def R144 : AMDILReg<144, "r144">, DwarfRegNum<[144]>;
|
||||
def R145 : AMDILReg<145, "r145">, DwarfRegNum<[145]>;
|
||||
def R146 : AMDILReg<146, "r146">, DwarfRegNum<[146]>;
|
||||
def R147 : AMDILReg<147, "r147">, DwarfRegNum<[147]>;
|
||||
def R148 : AMDILReg<148, "r148">, DwarfRegNum<[148]>;
|
||||
def R149 : AMDILReg<149, "r149">, DwarfRegNum<[149]>;
|
||||
def R150 : AMDILReg<150, "r150">, DwarfRegNum<[150]>;
|
||||
def R151 : AMDILReg<151, "r151">, DwarfRegNum<[151]>;
|
||||
def R152 : AMDILReg<152, "r152">, DwarfRegNum<[152]>;
|
||||
def R153 : AMDILReg<153, "r153">, DwarfRegNum<[153]>;
|
||||
def R154 : AMDILReg<154, "r154">, DwarfRegNum<[154]>;
|
||||
def R155 : AMDILReg<155, "r155">, DwarfRegNum<[155]>;
|
||||
def R156 : AMDILReg<156, "r156">, DwarfRegNum<[156]>;
|
||||
def R157 : AMDILReg<157, "r157">, DwarfRegNum<[157]>;
|
||||
def R158 : AMDILReg<158, "r158">, DwarfRegNum<[158]>;
|
||||
def R159 : AMDILReg<159, "r159">, DwarfRegNum<[159]>;
|
||||
def R160 : AMDILReg<160, "r160">, DwarfRegNum<[160]>;
|
||||
def R161 : AMDILReg<161, "r161">, DwarfRegNum<[161]>;
|
||||
def R162 : AMDILReg<162, "r162">, DwarfRegNum<[162]>;
|
||||
def R163 : AMDILReg<163, "r163">, DwarfRegNum<[163]>;
|
||||
def R164 : AMDILReg<164, "r164">, DwarfRegNum<[164]>;
|
||||
def R165 : AMDILReg<165, "r165">, DwarfRegNum<[165]>;
|
||||
def R166 : AMDILReg<166, "r166">, DwarfRegNum<[166]>;
|
||||
def R167 : AMDILReg<167, "r167">, DwarfRegNum<[167]>;
|
||||
def R168 : AMDILReg<168, "r168">, DwarfRegNum<[168]>;
|
||||
def R169 : AMDILReg<169, "r169">, DwarfRegNum<[169]>;
|
||||
def R170 : AMDILReg<170, "r170">, DwarfRegNum<[170]>;
|
||||
def R171 : AMDILReg<171, "r171">, DwarfRegNum<[171]>;
|
||||
def R172 : AMDILReg<172, "r172">, DwarfRegNum<[172]>;
|
||||
def R173 : AMDILReg<173, "r173">, DwarfRegNum<[173]>;
|
||||
def R174 : AMDILReg<174, "r174">, DwarfRegNum<[174]>;
|
||||
def R175 : AMDILReg<175, "r175">, DwarfRegNum<[175]>;
|
||||
def R176 : AMDILReg<176, "r176">, DwarfRegNum<[176]>;
|
||||
def R177 : AMDILReg<177, "r177">, DwarfRegNum<[177]>;
|
||||
def R178 : AMDILReg<178, "r178">, DwarfRegNum<[178]>;
|
||||
def R179 : AMDILReg<179, "r179">, DwarfRegNum<[179]>;
|
||||
def R180 : AMDILReg<180, "r180">, DwarfRegNum<[180]>;
|
||||
def R181 : AMDILReg<181, "r181">, DwarfRegNum<[181]>;
|
||||
def R182 : AMDILReg<182, "r182">, DwarfRegNum<[182]>;
|
||||
def R183 : AMDILReg<183, "r183">, DwarfRegNum<[183]>;
|
||||
def R184 : AMDILReg<184, "r184">, DwarfRegNum<[184]>;
|
||||
def R185 : AMDILReg<185, "r185">, DwarfRegNum<[185]>;
|
||||
def R186 : AMDILReg<186, "r186">, DwarfRegNum<[186]>;
|
||||
def R187 : AMDILReg<187, "r187">, DwarfRegNum<[187]>;
|
||||
def R188 : AMDILReg<188, "r188">, DwarfRegNum<[188]>;
|
||||
def R189 : AMDILReg<189, "r189">, DwarfRegNum<[189]>;
|
||||
def R190 : AMDILReg<190, "r190">, DwarfRegNum<[190]>;
|
||||
def R191 : AMDILReg<191, "r191">, DwarfRegNum<[191]>;
|
||||
def R192 : AMDILReg<192, "r192">, DwarfRegNum<[192]>;
|
||||
def R193 : AMDILReg<193, "r193">, DwarfRegNum<[193]>;
|
||||
def R194 : AMDILReg<194, "r194">, DwarfRegNum<[194]>;
|
||||
def R195 : AMDILReg<195, "r195">, DwarfRegNum<[195]>;
|
||||
def R196 : AMDILReg<196, "r196">, DwarfRegNum<[196]>;
|
||||
def R197 : AMDILReg<197, "r197">, DwarfRegNum<[197]>;
|
||||
def R198 : AMDILReg<198, "r198">, DwarfRegNum<[198]>;
|
||||
def R199 : AMDILReg<199, "r199">, DwarfRegNum<[199]>;
|
||||
def R200 : AMDILReg<200, "r200">, DwarfRegNum<[200]>;
|
||||
def R201 : AMDILReg<201, "r201">, DwarfRegNum<[201]>;
|
||||
def R202 : AMDILReg<202, "r202">, DwarfRegNum<[202]>;
|
||||
def R203 : AMDILReg<203, "r203">, DwarfRegNum<[203]>;
|
||||
def R204 : AMDILReg<204, "r204">, DwarfRegNum<[204]>;
|
||||
def R205 : AMDILReg<205, "r205">, DwarfRegNum<[205]>;
|
||||
def R206 : AMDILReg<206, "r206">, DwarfRegNum<[206]>;
|
||||
def R207 : AMDILReg<207, "r207">, DwarfRegNum<[207]>;
|
||||
def R208 : AMDILReg<208, "r208">, DwarfRegNum<[208]>;
|
||||
def R209 : AMDILReg<209, "r209">, DwarfRegNum<[209]>;
|
||||
def R210 : AMDILReg<210, "r210">, DwarfRegNum<[210]>;
|
||||
def R211 : AMDILReg<211, "r211">, DwarfRegNum<[211]>;
|
||||
def R212 : AMDILReg<212, "r212">, DwarfRegNum<[212]>;
|
||||
def R213 : AMDILReg<213, "r213">, DwarfRegNum<[213]>;
|
||||
def R214 : AMDILReg<214, "r214">, DwarfRegNum<[214]>;
|
||||
def R215 : AMDILReg<215, "r215">, DwarfRegNum<[215]>;
|
||||
def R216 : AMDILReg<216, "r216">, DwarfRegNum<[216]>;
|
||||
def R217 : AMDILReg<217, "r217">, DwarfRegNum<[217]>;
|
||||
def R218 : AMDILReg<218, "r218">, DwarfRegNum<[218]>;
|
||||
def R219 : AMDILReg<219, "r219">, DwarfRegNum<[219]>;
|
||||
def R220 : AMDILReg<220, "r220">, DwarfRegNum<[220]>;
|
||||
def R221 : AMDILReg<221, "r221">, DwarfRegNum<[221]>;
|
||||
def R222 : AMDILReg<222, "r222">, DwarfRegNum<[222]>;
|
||||
def R223 : AMDILReg<223, "r223">, DwarfRegNum<[223]>;
|
||||
def R224 : AMDILReg<224, "r224">, DwarfRegNum<[224]>;
|
||||
def R225 : AMDILReg<225, "r225">, DwarfRegNum<[225]>;
|
||||
def R226 : AMDILReg<226, "r226">, DwarfRegNum<[226]>;
|
||||
def R227 : AMDILReg<227, "r227">, DwarfRegNum<[227]>;
|
||||
def R228 : AMDILReg<228, "r228">, DwarfRegNum<[228]>;
|
||||
def R229 : AMDILReg<229, "r229">, DwarfRegNum<[229]>;
|
||||
def R230 : AMDILReg<230, "r230">, DwarfRegNum<[230]>;
|
||||
def R231 : AMDILReg<231, "r231">, DwarfRegNum<[231]>;
|
||||
def R232 : AMDILReg<232, "r232">, DwarfRegNum<[232]>;
|
||||
def R233 : AMDILReg<233, "r233">, DwarfRegNum<[233]>;
|
||||
def R234 : AMDILReg<234, "r234">, DwarfRegNum<[234]>;
|
||||
def R235 : AMDILReg<235, "r235">, DwarfRegNum<[235]>;
|
||||
def R236 : AMDILReg<236, "r236">, DwarfRegNum<[236]>;
|
||||
def R237 : AMDILReg<237, "r237">, DwarfRegNum<[237]>;
|
||||
def R238 : AMDILReg<238, "r238">, DwarfRegNum<[238]>;
|
||||
def R239 : AMDILReg<239, "r239">, DwarfRegNum<[239]>;
|
||||
def R240 : AMDILReg<240, "r240">, DwarfRegNum<[240]>;
|
||||
def R241 : AMDILReg<241, "r241">, DwarfRegNum<[241]>;
|
||||
def R242 : AMDILReg<242, "r242">, DwarfRegNum<[242]>;
|
||||
def R243 : AMDILReg<243, "r243">, DwarfRegNum<[243]>;
|
||||
def R244 : AMDILReg<244, "r244">, DwarfRegNum<[244]>;
|
||||
def R245 : AMDILReg<245, "r245">, DwarfRegNum<[245]>;
|
||||
def R246 : AMDILReg<246, "r246">, DwarfRegNum<[246]>;
|
||||
def R247 : AMDILReg<247, "r247">, DwarfRegNum<[247]>;
|
||||
def R248 : AMDILReg<248, "r248">, DwarfRegNum<[248]>;
|
||||
def R249 : AMDILReg<249, "r249">, DwarfRegNum<[249]>;
|
||||
def R250 : AMDILReg<250, "r250">, DwarfRegNum<[250]>;
|
||||
def R251 : AMDILReg<251, "r251">, DwarfRegNum<[251]>;
|
||||
def R252 : AMDILReg<252, "r252">, DwarfRegNum<[252]>;
|
||||
def R253 : AMDILReg<253, "r253">, DwarfRegNum<[253]>;
|
||||
def R254 : AMDILReg<254, "r254">, DwarfRegNum<[254]>;
|
||||
def R255 : AMDILReg<255, "r255">, DwarfRegNum<[255]>;
|
||||
def R256 : AMDILReg<256, "r256">, DwarfRegNum<[256]>;
|
||||
def R257 : AMDILReg<257, "r257">, DwarfRegNum<[257]>;
|
||||
def R258 : AMDILReg<258, "r258">, DwarfRegNum<[258]>;
|
||||
def R259 : AMDILReg<259, "r259">, DwarfRegNum<[259]>;
|
||||
def R260 : AMDILReg<260, "r260">, DwarfRegNum<[260]>;
|
||||
def R261 : AMDILReg<261, "r261">, DwarfRegNum<[261]>;
|
||||
def R262 : AMDILReg<262, "r262">, DwarfRegNum<[262]>;
|
||||
def R263 : AMDILReg<263, "r263">, DwarfRegNum<[263]>;
|
||||
def R264 : AMDILReg<264, "r264">, DwarfRegNum<[264]>;
|
||||
def R265 : AMDILReg<265, "r265">, DwarfRegNum<[265]>;
|
||||
def R266 : AMDILReg<266, "r266">, DwarfRegNum<[266]>;
|
||||
def R267 : AMDILReg<267, "r267">, DwarfRegNum<[267]>;
|
||||
def R268 : AMDILReg<268, "r268">, DwarfRegNum<[268]>;
|
||||
def R269 : AMDILReg<269, "r269">, DwarfRegNum<[269]>;
|
||||
def R270 : AMDILReg<270, "r270">, DwarfRegNum<[270]>;
|
||||
def R271 : AMDILReg<271, "r271">, DwarfRegNum<[271]>;
|
||||
def R272 : AMDILReg<272, "r272">, DwarfRegNum<[272]>;
|
||||
def R273 : AMDILReg<273, "r273">, DwarfRegNum<[273]>;
|
||||
def R274 : AMDILReg<274, "r274">, DwarfRegNum<[274]>;
|
||||
def R275 : AMDILReg<275, "r275">, DwarfRegNum<[275]>;
|
||||
def R276 : AMDILReg<276, "r276">, DwarfRegNum<[276]>;
|
||||
def R277 : AMDILReg<277, "r277">, DwarfRegNum<[277]>;
|
||||
def R278 : AMDILReg<278, "r278">, DwarfRegNum<[278]>;
|
||||
def R279 : AMDILReg<279, "r279">, DwarfRegNum<[279]>;
|
||||
def R280 : AMDILReg<280, "r280">, DwarfRegNum<[280]>;
|
||||
def R281 : AMDILReg<281, "r281">, DwarfRegNum<[281]>;
|
||||
def R282 : AMDILReg<282, "r282">, DwarfRegNum<[282]>;
|
||||
def R283 : AMDILReg<283, "r283">, DwarfRegNum<[283]>;
|
||||
def R284 : AMDILReg<284, "r284">, DwarfRegNum<[284]>;
|
||||
def R285 : AMDILReg<285, "r285">, DwarfRegNum<[285]>;
|
||||
def R286 : AMDILReg<286, "r286">, DwarfRegNum<[286]>;
|
||||
def R287 : AMDILReg<287, "r287">, DwarfRegNum<[287]>;
|
||||
def R288 : AMDILReg<288, "r288">, DwarfRegNum<[288]>;
|
||||
def R289 : AMDILReg<289, "r289">, DwarfRegNum<[289]>;
|
||||
def R290 : AMDILReg<290, "r290">, DwarfRegNum<[290]>;
|
||||
def R291 : AMDILReg<291, "r291">, DwarfRegNum<[291]>;
|
||||
def R292 : AMDILReg<292, "r292">, DwarfRegNum<[292]>;
|
||||
def R293 : AMDILReg<293, "r293">, DwarfRegNum<[293]>;
|
||||
def R294 : AMDILReg<294, "r294">, DwarfRegNum<[294]>;
|
||||
def R295 : AMDILReg<295, "r295">, DwarfRegNum<[295]>;
|
||||
def R296 : AMDILReg<296, "r296">, DwarfRegNum<[296]>;
|
||||
def R297 : AMDILReg<297, "r297">, DwarfRegNum<[297]>;
|
||||
def R298 : AMDILReg<298, "r298">, DwarfRegNum<[298]>;
|
||||
def R299 : AMDILReg<299, "r299">, DwarfRegNum<[299]>;
|
||||
def R300 : AMDILReg<300, "r300">, DwarfRegNum<[300]>;
|
||||
def R301 : AMDILReg<301, "r301">, DwarfRegNum<[301]>;
|
||||
def R302 : AMDILReg<302, "r302">, DwarfRegNum<[302]>;
|
||||
def R303 : AMDILReg<303, "r303">, DwarfRegNum<[303]>;
|
||||
def R304 : AMDILReg<304, "r304">, DwarfRegNum<[304]>;
|
||||
def R305 : AMDILReg<305, "r305">, DwarfRegNum<[305]>;
|
||||
def R306 : AMDILReg<306, "r306">, DwarfRegNum<[306]>;
|
||||
def R307 : AMDILReg<307, "r307">, DwarfRegNum<[307]>;
|
||||
def R308 : AMDILReg<308, "r308">, DwarfRegNum<[308]>;
|
||||
def R309 : AMDILReg<309, "r309">, DwarfRegNum<[309]>;
|
||||
def R310 : AMDILReg<310, "r310">, DwarfRegNum<[310]>;
|
||||
def R311 : AMDILReg<311, "r311">, DwarfRegNum<[311]>;
|
||||
def R312 : AMDILReg<312, "r312">, DwarfRegNum<[312]>;
|
||||
def R313 : AMDILReg<313, "r313">, DwarfRegNum<[313]>;
|
||||
def R314 : AMDILReg<314, "r314">, DwarfRegNum<[314]>;
|
||||
def R315 : AMDILReg<315, "r315">, DwarfRegNum<[315]>;
|
||||
def R316 : AMDILReg<316, "r316">, DwarfRegNum<[316]>;
|
||||
def R317 : AMDILReg<317, "r317">, DwarfRegNum<[317]>;
|
||||
def R318 : AMDILReg<318, "r318">, DwarfRegNum<[318]>;
|
||||
def R319 : AMDILReg<319, "r319">, DwarfRegNum<[319]>;
|
||||
def R320 : AMDILReg<320, "r320">, DwarfRegNum<[320]>;
|
||||
def R321 : AMDILReg<321, "r321">, DwarfRegNum<[321]>;
|
||||
def R322 : AMDILReg<322, "r322">, DwarfRegNum<[322]>;
|
||||
def R323 : AMDILReg<323, "r323">, DwarfRegNum<[323]>;
|
||||
def R324 : AMDILReg<324, "r324">, DwarfRegNum<[324]>;
|
||||
def R325 : AMDILReg<325, "r325">, DwarfRegNum<[325]>;
|
||||
def R326 : AMDILReg<326, "r326">, DwarfRegNum<[326]>;
|
||||
def R327 : AMDILReg<327, "r327">, DwarfRegNum<[327]>;
|
||||
def R328 : AMDILReg<328, "r328">, DwarfRegNum<[328]>;
|
||||
def R329 : AMDILReg<329, "r329">, DwarfRegNum<[329]>;
|
||||
def R330 : AMDILReg<330, "r330">, DwarfRegNum<[330]>;
|
||||
def R331 : AMDILReg<331, "r331">, DwarfRegNum<[331]>;
|
||||
def R332 : AMDILReg<332, "r332">, DwarfRegNum<[332]>;
|
||||
def R333 : AMDILReg<333, "r333">, DwarfRegNum<[333]>;
|
||||
def R334 : AMDILReg<334, "r334">, DwarfRegNum<[334]>;
|
||||
def R335 : AMDILReg<335, "r335">, DwarfRegNum<[335]>;
|
||||
def R336 : AMDILReg<336, "r336">, DwarfRegNum<[336]>;
|
||||
def R337 : AMDILReg<337, "r337">, DwarfRegNum<[337]>;
|
||||
def R338 : AMDILReg<338, "r338">, DwarfRegNum<[338]>;
|
||||
def R339 : AMDILReg<339, "r339">, DwarfRegNum<[339]>;
|
||||
def R340 : AMDILReg<340, "r340">, DwarfRegNum<[340]>;
|
||||
def R341 : AMDILReg<341, "r341">, DwarfRegNum<[341]>;
|
||||
def R342 : AMDILReg<342, "r342">, DwarfRegNum<[342]>;
|
||||
def R343 : AMDILReg<343, "r343">, DwarfRegNum<[343]>;
|
||||
def R344 : AMDILReg<344, "r344">, DwarfRegNum<[344]>;
|
||||
def R345 : AMDILReg<345, "r345">, DwarfRegNum<[345]>;
|
||||
def R346 : AMDILReg<346, "r346">, DwarfRegNum<[346]>;
|
||||
def R347 : AMDILReg<347, "r347">, DwarfRegNum<[347]>;
|
||||
def R348 : AMDILReg<348, "r348">, DwarfRegNum<[348]>;
|
||||
def R349 : AMDILReg<349, "r349">, DwarfRegNum<[349]>;
|
||||
def R350 : AMDILReg<350, "r350">, DwarfRegNum<[350]>;
|
||||
def R351 : AMDILReg<351, "r351">, DwarfRegNum<[351]>;
|
||||
def R352 : AMDILReg<352, "r352">, DwarfRegNum<[352]>;
|
||||
def R353 : AMDILReg<353, "r353">, DwarfRegNum<[353]>;
|
||||
def R354 : AMDILReg<354, "r354">, DwarfRegNum<[354]>;
|
||||
def R355 : AMDILReg<355, "r355">, DwarfRegNum<[355]>;
|
||||
def R356 : AMDILReg<356, "r356">, DwarfRegNum<[356]>;
|
||||
def R357 : AMDILReg<357, "r357">, DwarfRegNum<[357]>;
|
||||
def R358 : AMDILReg<358, "r358">, DwarfRegNum<[358]>;
|
||||
def R359 : AMDILReg<359, "r359">, DwarfRegNum<[359]>;
|
||||
def R360 : AMDILReg<360, "r360">, DwarfRegNum<[360]>;
|
||||
def R361 : AMDILReg<361, "r361">, DwarfRegNum<[361]>;
|
||||
def R362 : AMDILReg<362, "r362">, DwarfRegNum<[362]>;
|
||||
def R363 : AMDILReg<363, "r363">, DwarfRegNum<[363]>;
|
||||
def R364 : AMDILReg<364, "r364">, DwarfRegNum<[364]>;
|
||||
def R365 : AMDILReg<365, "r365">, DwarfRegNum<[365]>;
|
||||
def R366 : AMDILReg<366, "r366">, DwarfRegNum<[366]>;
|
||||
def R367 : AMDILReg<367, "r367">, DwarfRegNum<[367]>;
|
||||
def R368 : AMDILReg<368, "r368">, DwarfRegNum<[368]>;
|
||||
def R369 : AMDILReg<369, "r369">, DwarfRegNum<[369]>;
|
||||
def R370 : AMDILReg<370, "r370">, DwarfRegNum<[370]>;
|
||||
def R371 : AMDILReg<371, "r371">, DwarfRegNum<[371]>;
|
||||
def R372 : AMDILReg<372, "r372">, DwarfRegNum<[372]>;
|
||||
def R373 : AMDILReg<373, "r373">, DwarfRegNum<[373]>;
|
||||
def R374 : AMDILReg<374, "r374">, DwarfRegNum<[374]>;
|
||||
def R375 : AMDILReg<375, "r375">, DwarfRegNum<[375]>;
|
||||
def R376 : AMDILReg<376, "r376">, DwarfRegNum<[376]>;
|
||||
def R377 : AMDILReg<377, "r377">, DwarfRegNum<[377]>;
|
||||
def R378 : AMDILReg<378, "r378">, DwarfRegNum<[378]>;
|
||||
def R379 : AMDILReg<379, "r379">, DwarfRegNum<[379]>;
|
||||
def R380 : AMDILReg<380, "r380">, DwarfRegNum<[380]>;
|
||||
def R381 : AMDILReg<381, "r381">, DwarfRegNum<[381]>;
|
||||
def R382 : AMDILReg<382, "r382">, DwarfRegNum<[382]>;
|
||||
def R383 : AMDILReg<383, "r383">, DwarfRegNum<[383]>;
|
||||
def R384 : AMDILReg<384, "r384">, DwarfRegNum<[384]>;
|
||||
def R385 : AMDILReg<385, "r385">, DwarfRegNum<[385]>;
|
||||
def R386 : AMDILReg<386, "r386">, DwarfRegNum<[386]>;
|
||||
def R387 : AMDILReg<387, "r387">, DwarfRegNum<[387]>;
|
||||
def R388 : AMDILReg<388, "r388">, DwarfRegNum<[388]>;
|
||||
def R389 : AMDILReg<389, "r389">, DwarfRegNum<[389]>;
|
||||
def R390 : AMDILReg<390, "r390">, DwarfRegNum<[390]>;
|
||||
def R391 : AMDILReg<391, "r391">, DwarfRegNum<[391]>;
|
||||
def R392 : AMDILReg<392, "r392">, DwarfRegNum<[392]>;
|
||||
def R393 : AMDILReg<393, "r393">, DwarfRegNum<[393]>;
|
||||
def R394 : AMDILReg<394, "r394">, DwarfRegNum<[394]>;
|
||||
def R395 : AMDILReg<395, "r395">, DwarfRegNum<[395]>;
|
||||
def R396 : AMDILReg<396, "r396">, DwarfRegNum<[396]>;
|
||||
def R397 : AMDILReg<397, "r397">, DwarfRegNum<[397]>;
|
||||
def R398 : AMDILReg<398, "r398">, DwarfRegNum<[398]>;
|
||||
def R399 : AMDILReg<399, "r399">, DwarfRegNum<[399]>;
|
||||
def R400 : AMDILReg<400, "r400">, DwarfRegNum<[400]>;
|
||||
def R401 : AMDILReg<401, "r401">, DwarfRegNum<[401]>;
|
||||
def R402 : AMDILReg<402, "r402">, DwarfRegNum<[402]>;
|
||||
def R403 : AMDILReg<403, "r403">, DwarfRegNum<[403]>;
|
||||
def R404 : AMDILReg<404, "r404">, DwarfRegNum<[404]>;
|
||||
def R405 : AMDILReg<405, "r405">, DwarfRegNum<[405]>;
|
||||
def R406 : AMDILReg<406, "r406">, DwarfRegNum<[406]>;
|
||||
def R407 : AMDILReg<407, "r407">, DwarfRegNum<[407]>;
|
||||
def R408 : AMDILReg<408, "r408">, DwarfRegNum<[408]>;
|
||||
def R409 : AMDILReg<409, "r409">, DwarfRegNum<[409]>;
|
||||
def R410 : AMDILReg<410, "r410">, DwarfRegNum<[410]>;
|
||||
def R411 : AMDILReg<411, "r411">, DwarfRegNum<[411]>;
|
||||
def R412 : AMDILReg<412, "r412">, DwarfRegNum<[412]>;
|
||||
def R413 : AMDILReg<413, "r413">, DwarfRegNum<[413]>;
|
||||
def R414 : AMDILReg<414, "r414">, DwarfRegNum<[414]>;
|
||||
def R415 : AMDILReg<415, "r415">, DwarfRegNum<[415]>;
|
||||
def R416 : AMDILReg<416, "r416">, DwarfRegNum<[416]>;
|
||||
def R417 : AMDILReg<417, "r417">, DwarfRegNum<[417]>;
|
||||
def R418 : AMDILReg<418, "r418">, DwarfRegNum<[418]>;
|
||||
def R419 : AMDILReg<419, "r419">, DwarfRegNum<[419]>;
|
||||
def R420 : AMDILReg<420, "r420">, DwarfRegNum<[420]>;
|
||||
def R421 : AMDILReg<421, "r421">, DwarfRegNum<[421]>;
|
||||
def R422 : AMDILReg<422, "r422">, DwarfRegNum<[422]>;
|
||||
def R423 : AMDILReg<423, "r423">, DwarfRegNum<[423]>;
|
||||
def R424 : AMDILReg<424, "r424">, DwarfRegNum<[424]>;
|
||||
def R425 : AMDILReg<425, "r425">, DwarfRegNum<[425]>;
|
||||
def R426 : AMDILReg<426, "r426">, DwarfRegNum<[426]>;
|
||||
def R427 : AMDILReg<427, "r427">, DwarfRegNum<[427]>;
|
||||
def R428 : AMDILReg<428, "r428">, DwarfRegNum<[428]>;
|
||||
def R429 : AMDILReg<429, "r429">, DwarfRegNum<[429]>;
|
||||
def R430 : AMDILReg<430, "r430">, DwarfRegNum<[430]>;
|
||||
def R431 : AMDILReg<431, "r431">, DwarfRegNum<[431]>;
|
||||
def R432 : AMDILReg<432, "r432">, DwarfRegNum<[432]>;
|
||||
def R433 : AMDILReg<433, "r433">, DwarfRegNum<[433]>;
|
||||
def R434 : AMDILReg<434, "r434">, DwarfRegNum<[434]>;
|
||||
def R435 : AMDILReg<435, "r435">, DwarfRegNum<[435]>;
|
||||
def R436 : AMDILReg<436, "r436">, DwarfRegNum<[436]>;
|
||||
def R437 : AMDILReg<437, "r437">, DwarfRegNum<[437]>;
|
||||
def R438 : AMDILReg<438, "r438">, DwarfRegNum<[438]>;
|
||||
def R439 : AMDILReg<439, "r439">, DwarfRegNum<[439]>;
|
||||
def R440 : AMDILReg<440, "r440">, DwarfRegNum<[440]>;
|
||||
def R441 : AMDILReg<441, "r441">, DwarfRegNum<[441]>;
|
||||
def R442 : AMDILReg<442, "r442">, DwarfRegNum<[442]>;
|
||||
def R443 : AMDILReg<443, "r443">, DwarfRegNum<[443]>;
|
||||
def R444 : AMDILReg<444, "r444">, DwarfRegNum<[444]>;
|
||||
def R445 : AMDILReg<445, "r445">, DwarfRegNum<[445]>;
|
||||
def R446 : AMDILReg<446, "r446">, DwarfRegNum<[446]>;
|
||||
def R447 : AMDILReg<447, "r447">, DwarfRegNum<[447]>;
|
||||
def R448 : AMDILReg<448, "r448">, DwarfRegNum<[448]>;
|
||||
def R449 : AMDILReg<449, "r449">, DwarfRegNum<[449]>;
|
||||
def R450 : AMDILReg<450, "r450">, DwarfRegNum<[450]>;
|
||||
def R451 : AMDILReg<451, "r451">, DwarfRegNum<[451]>;
|
||||
def R452 : AMDILReg<452, "r452">, DwarfRegNum<[452]>;
|
||||
def R453 : AMDILReg<453, "r453">, DwarfRegNum<[453]>;
|
||||
def R454 : AMDILReg<454, "r454">, DwarfRegNum<[454]>;
|
||||
def R455 : AMDILReg<455, "r455">, DwarfRegNum<[455]>;
|
||||
def R456 : AMDILReg<456, "r456">, DwarfRegNum<[456]>;
|
||||
def R457 : AMDILReg<457, "r457">, DwarfRegNum<[457]>;
|
||||
def R458 : AMDILReg<458, "r458">, DwarfRegNum<[458]>;
|
||||
def R459 : AMDILReg<459, "r459">, DwarfRegNum<[459]>;
|
||||
def R460 : AMDILReg<460, "r460">, DwarfRegNum<[460]>;
|
||||
def R461 : AMDILReg<461, "r461">, DwarfRegNum<[461]>;
|
||||
def R462 : AMDILReg<462, "r462">, DwarfRegNum<[462]>;
|
||||
def R463 : AMDILReg<463, "r463">, DwarfRegNum<[463]>;
|
||||
def R464 : AMDILReg<464, "r464">, DwarfRegNum<[464]>;
|
||||
def R465 : AMDILReg<465, "r465">, DwarfRegNum<[465]>;
|
||||
def R466 : AMDILReg<466, "r466">, DwarfRegNum<[466]>;
|
||||
def R467 : AMDILReg<467, "r467">, DwarfRegNum<[467]>;
|
||||
def R468 : AMDILReg<468, "r468">, DwarfRegNum<[468]>;
|
||||
def R469 : AMDILReg<469, "r469">, DwarfRegNum<[469]>;
|
||||
def R470 : AMDILReg<470, "r470">, DwarfRegNum<[470]>;
|
||||
def R471 : AMDILReg<471, "r471">, DwarfRegNum<[471]>;
|
||||
def R472 : AMDILReg<472, "r472">, DwarfRegNum<[472]>;
|
||||
def R473 : AMDILReg<473, "r473">, DwarfRegNum<[473]>;
|
||||
def R474 : AMDILReg<474, "r474">, DwarfRegNum<[474]>;
|
||||
def R475 : AMDILReg<475, "r475">, DwarfRegNum<[475]>;
|
||||
def R476 : AMDILReg<476, "r476">, DwarfRegNum<[476]>;
|
||||
def R477 : AMDILReg<477, "r477">, DwarfRegNum<[477]>;
|
||||
def R478 : AMDILReg<478, "r478">, DwarfRegNum<[478]>;
|
||||
def R479 : AMDILReg<479, "r479">, DwarfRegNum<[479]>;
|
||||
def R480 : AMDILReg<480, "r480">, DwarfRegNum<[480]>;
|
||||
def R481 : AMDILReg<481, "r481">, DwarfRegNum<[481]>;
|
||||
def R482 : AMDILReg<482, "r482">, DwarfRegNum<[482]>;
|
||||
def R483 : AMDILReg<483, "r483">, DwarfRegNum<[483]>;
|
||||
def R484 : AMDILReg<484, "r484">, DwarfRegNum<[484]>;
|
||||
def R485 : AMDILReg<485, "r485">, DwarfRegNum<[485]>;
|
||||
def R486 : AMDILReg<486, "r486">, DwarfRegNum<[486]>;
|
||||
def R487 : AMDILReg<487, "r487">, DwarfRegNum<[487]>;
|
||||
def R488 : AMDILReg<488, "r488">, DwarfRegNum<[488]>;
|
||||
def R489 : AMDILReg<489, "r489">, DwarfRegNum<[489]>;
|
||||
def R490 : AMDILReg<490, "r490">, DwarfRegNum<[490]>;
|
||||
def R491 : AMDILReg<491, "r491">, DwarfRegNum<[491]>;
|
||||
def R492 : AMDILReg<492, "r492">, DwarfRegNum<[492]>;
|
||||
def R493 : AMDILReg<493, "r493">, DwarfRegNum<[493]>;
|
||||
def R494 : AMDILReg<494, "r494">, DwarfRegNum<[494]>;
|
||||
def R495 : AMDILReg<495, "r495">, DwarfRegNum<[495]>;
|
||||
def R496 : AMDILReg<496, "r496">, DwarfRegNum<[496]>;
|
||||
def R497 : AMDILReg<497, "r497">, DwarfRegNum<[497]>;
|
||||
def R498 : AMDILReg<498, "r498">, DwarfRegNum<[498]>;
|
||||
def R499 : AMDILReg<499, "r499">, DwarfRegNum<[499]>;
|
||||
def R500 : AMDILReg<500, "r500">, DwarfRegNum<[500]>;
|
||||
def R501 : AMDILReg<501, "r501">, DwarfRegNum<[501]>;
|
||||
def R502 : AMDILReg<502, "r502">, DwarfRegNum<[502]>;
|
||||
def R503 : AMDILReg<503, "r503">, DwarfRegNum<[503]>;
|
||||
def R504 : AMDILReg<504, "r504">, DwarfRegNum<[504]>;
|
||||
def R505 : AMDILReg<505, "r505">, DwarfRegNum<[505]>;
|
||||
def R506 : AMDILReg<506, "r506">, DwarfRegNum<[506]>;
|
||||
def R507 : AMDILReg<507, "r507">, DwarfRegNum<[507]>;
|
||||
def R508 : AMDILReg<508, "r508">, DwarfRegNum<[508]>;
|
||||
def R509 : AMDILReg<509, "r509">, DwarfRegNum<[509]>;
|
||||
def R510 : AMDILReg<510, "r510">, DwarfRegNum<[510]>;
|
||||
def R511 : AMDILReg<511, "r511">, DwarfRegNum<[511]>;
|
||||
def R512 : AMDILReg<512, "r512">, DwarfRegNum<[512]>;
|
||||
def R513 : AMDILReg<513, "r513">, DwarfRegNum<[513]>;
|
||||
def R514 : AMDILReg<514, "r514">, DwarfRegNum<[514]>;
|
||||
def R515 : AMDILReg<515, "r515">, DwarfRegNum<[515]>;
|
||||
def R516 : AMDILReg<516, "r516">, DwarfRegNum<[516]>;
|
||||
def R517 : AMDILReg<517, "r517">, DwarfRegNum<[517]>;
|
||||
def R518 : AMDILReg<518, "r518">, DwarfRegNum<[518]>;
|
||||
def R519 : AMDILReg<519, "r519">, DwarfRegNum<[519]>;
|
||||
def R520 : AMDILReg<520, "r520">, DwarfRegNum<[520]>;
|
||||
def R521 : AMDILReg<521, "r521">, DwarfRegNum<[521]>;
|
||||
def R522 : AMDILReg<522, "r522">, DwarfRegNum<[522]>;
|
||||
def R523 : AMDILReg<523, "r523">, DwarfRegNum<[523]>;
|
||||
def R524 : AMDILReg<524, "r524">, DwarfRegNum<[524]>;
|
||||
def R525 : AMDILReg<525, "r525">, DwarfRegNum<[525]>;
|
||||
def R526 : AMDILReg<526, "r526">, DwarfRegNum<[526]>;
|
||||
def R527 : AMDILReg<527, "r527">, DwarfRegNum<[527]>;
|
||||
def R528 : AMDILReg<528, "r528">, DwarfRegNum<[528]>;
|
||||
def R529 : AMDILReg<529, "r529">, DwarfRegNum<[529]>;
|
||||
def R530 : AMDILReg<530, "r530">, DwarfRegNum<[530]>;
|
||||
def R531 : AMDILReg<531, "r531">, DwarfRegNum<[531]>;
|
||||
def R532 : AMDILReg<532, "r532">, DwarfRegNum<[532]>;
|
||||
def R533 : AMDILReg<533, "r533">, DwarfRegNum<[533]>;
|
||||
def R534 : AMDILReg<534, "r534">, DwarfRegNum<[534]>;
|
||||
def R535 : AMDILReg<535, "r535">, DwarfRegNum<[535]>;
|
||||
def R536 : AMDILReg<536, "r536">, DwarfRegNum<[536]>;
|
||||
def R537 : AMDILReg<537, "r537">, DwarfRegNum<[537]>;
|
||||
def R538 : AMDILReg<538, "r538">, DwarfRegNum<[538]>;
|
||||
def R539 : AMDILReg<539, "r539">, DwarfRegNum<[539]>;
|
||||
def R540 : AMDILReg<540, "r540">, DwarfRegNum<[540]>;
|
||||
def R541 : AMDILReg<541, "r541">, DwarfRegNum<[541]>;
|
||||
def R542 : AMDILReg<542, "r542">, DwarfRegNum<[542]>;
|
||||
def R543 : AMDILReg<543, "r543">, DwarfRegNum<[543]>;
|
||||
def R544 : AMDILReg<544, "r544">, DwarfRegNum<[544]>;
|
||||
def R545 : AMDILReg<545, "r545">, DwarfRegNum<[545]>;
|
||||
def R546 : AMDILReg<546, "r546">, DwarfRegNum<[546]>;
|
||||
def R547 : AMDILReg<547, "r547">, DwarfRegNum<[547]>;
|
||||
def R548 : AMDILReg<548, "r548">, DwarfRegNum<[548]>;
|
||||
def R549 : AMDILReg<549, "r549">, DwarfRegNum<[549]>;
|
||||
def R550 : AMDILReg<550, "r550">, DwarfRegNum<[550]>;
|
||||
def R551 : AMDILReg<551, "r551">, DwarfRegNum<[551]>;
|
||||
def R552 : AMDILReg<552, "r552">, DwarfRegNum<[552]>;
|
||||
def R553 : AMDILReg<553, "r553">, DwarfRegNum<[553]>;
|
||||
def R554 : AMDILReg<554, "r554">, DwarfRegNum<[554]>;
|
||||
def R555 : AMDILReg<555, "r555">, DwarfRegNum<[555]>;
|
||||
def R556 : AMDILReg<556, "r556">, DwarfRegNum<[556]>;
|
||||
def R557 : AMDILReg<557, "r557">, DwarfRegNum<[557]>;
|
||||
def R558 : AMDILReg<558, "r558">, DwarfRegNum<[558]>;
|
||||
def R559 : AMDILReg<559, "r559">, DwarfRegNum<[559]>;
|
||||
def R560 : AMDILReg<560, "r560">, DwarfRegNum<[560]>;
|
||||
def R561 : AMDILReg<561, "r561">, DwarfRegNum<[561]>;
|
||||
def R562 : AMDILReg<562, "r562">, DwarfRegNum<[562]>;
|
||||
def R563 : AMDILReg<563, "r563">, DwarfRegNum<[563]>;
|
||||
def R564 : AMDILReg<564, "r564">, DwarfRegNum<[564]>;
|
||||
def R565 : AMDILReg<565, "r565">, DwarfRegNum<[565]>;
|
||||
def R566 : AMDILReg<566, "r566">, DwarfRegNum<[566]>;
|
||||
def R567 : AMDILReg<567, "r567">, DwarfRegNum<[567]>;
|
||||
def R568 : AMDILReg<568, "r568">, DwarfRegNum<[568]>;
|
||||
def R569 : AMDILReg<569, "r569">, DwarfRegNum<[569]>;
|
||||
def R570 : AMDILReg<570, "r570">, DwarfRegNum<[570]>;
|
||||
def R571 : AMDILReg<571, "r571">, DwarfRegNum<[571]>;
|
||||
def R572 : AMDILReg<572, "r572">, DwarfRegNum<[572]>;
|
||||
def R573 : AMDILReg<573, "r573">, DwarfRegNum<[573]>;
|
||||
def R574 : AMDILReg<574, "r574">, DwarfRegNum<[574]>;
|
||||
def R575 : AMDILReg<575, "r575">, DwarfRegNum<[575]>;
|
||||
def R576 : AMDILReg<576, "r576">, DwarfRegNum<[576]>;
|
||||
def R577 : AMDILReg<577, "r577">, DwarfRegNum<[577]>;
|
||||
def R578 : AMDILReg<578, "r578">, DwarfRegNum<[578]>;
|
||||
def R579 : AMDILReg<579, "r579">, DwarfRegNum<[579]>;
|
||||
def R580 : AMDILReg<580, "r580">, DwarfRegNum<[580]>;
|
||||
def R581 : AMDILReg<581, "r581">, DwarfRegNum<[581]>;
|
||||
def R582 : AMDILReg<582, "r582">, DwarfRegNum<[582]>;
|
||||
def R583 : AMDILReg<583, "r583">, DwarfRegNum<[583]>;
|
||||
def R584 : AMDILReg<584, "r584">, DwarfRegNum<[584]>;
|
||||
def R585 : AMDILReg<585, "r585">, DwarfRegNum<[585]>;
|
||||
def R586 : AMDILReg<586, "r586">, DwarfRegNum<[586]>;
|
||||
def R587 : AMDILReg<587, "r587">, DwarfRegNum<[587]>;
|
||||
def R588 : AMDILReg<588, "r588">, DwarfRegNum<[588]>;
|
||||
def R589 : AMDILReg<589, "r589">, DwarfRegNum<[589]>;
|
||||
def R590 : AMDILReg<590, "r590">, DwarfRegNum<[590]>;
|
||||
def R591 : AMDILReg<591, "r591">, DwarfRegNum<[591]>;
|
||||
def R592 : AMDILReg<592, "r592">, DwarfRegNum<[592]>;
|
||||
def R593 : AMDILReg<593, "r593">, DwarfRegNum<[593]>;
|
||||
def R594 : AMDILReg<594, "r594">, DwarfRegNum<[594]>;
|
||||
def R595 : AMDILReg<595, "r595">, DwarfRegNum<[595]>;
|
||||
def R596 : AMDILReg<596, "r596">, DwarfRegNum<[596]>;
|
||||
def R597 : AMDILReg<597, "r597">, DwarfRegNum<[597]>;
|
||||
def R598 : AMDILReg<598, "r598">, DwarfRegNum<[598]>;
|
||||
def R599 : AMDILReg<599, "r599">, DwarfRegNum<[599]>;
|
||||
def R600 : AMDILReg<600, "r600">, DwarfRegNum<[600]>;
|
||||
def R601 : AMDILReg<601, "r601">, DwarfRegNum<[601]>;
|
||||
def R602 : AMDILReg<602, "r602">, DwarfRegNum<[602]>;
|
||||
def R603 : AMDILReg<603, "r603">, DwarfRegNum<[603]>;
|
||||
def R604 : AMDILReg<604, "r604">, DwarfRegNum<[604]>;
|
||||
def R605 : AMDILReg<605, "r605">, DwarfRegNum<[605]>;
|
||||
def R606 : AMDILReg<606, "r606">, DwarfRegNum<[606]>;
|
||||
def R607 : AMDILReg<607, "r607">, DwarfRegNum<[607]>;
|
||||
def R608 : AMDILReg<608, "r608">, DwarfRegNum<[608]>;
|
||||
def R609 : AMDILReg<609, "r609">, DwarfRegNum<[609]>;
|
||||
def R610 : AMDILReg<610, "r610">, DwarfRegNum<[610]>;
|
||||
def R611 : AMDILReg<611, "r611">, DwarfRegNum<[611]>;
|
||||
def R612 : AMDILReg<612, "r612">, DwarfRegNum<[612]>;
|
||||
def R613 : AMDILReg<613, "r613">, DwarfRegNum<[613]>;
|
||||
def R614 : AMDILReg<614, "r614">, DwarfRegNum<[614]>;
|
||||
def R615 : AMDILReg<615, "r615">, DwarfRegNum<[615]>;
|
||||
def R616 : AMDILReg<616, "r616">, DwarfRegNum<[616]>;
|
||||
def R617 : AMDILReg<617, "r617">, DwarfRegNum<[617]>;
|
||||
def R618 : AMDILReg<618, "r618">, DwarfRegNum<[618]>;
|
||||
def R619 : AMDILReg<619, "r619">, DwarfRegNum<[619]>;
|
||||
def R620 : AMDILReg<620, "r620">, DwarfRegNum<[620]>;
|
||||
def R621 : AMDILReg<621, "r621">, DwarfRegNum<[621]>;
|
||||
def R622 : AMDILReg<622, "r622">, DwarfRegNum<[622]>;
|
||||
def R623 : AMDILReg<623, "r623">, DwarfRegNum<[623]>;
|
||||
def R624 : AMDILReg<624, "r624">, DwarfRegNum<[624]>;
|
||||
def R625 : AMDILReg<625, "r625">, DwarfRegNum<[625]>;
|
||||
def R626 : AMDILReg<626, "r626">, DwarfRegNum<[626]>;
|
||||
def R627 : AMDILReg<627, "r627">, DwarfRegNum<[627]>;
|
||||
def R628 : AMDILReg<628, "r628">, DwarfRegNum<[628]>;
|
||||
def R629 : AMDILReg<629, "r629">, DwarfRegNum<[629]>;
|
||||
def R630 : AMDILReg<630, "r630">, DwarfRegNum<[630]>;
|
||||
def R631 : AMDILReg<631, "r631">, DwarfRegNum<[631]>;
|
||||
def R632 : AMDILReg<632, "r632">, DwarfRegNum<[632]>;
|
||||
def R633 : AMDILReg<633, "r633">, DwarfRegNum<[633]>;
|
||||
def R634 : AMDILReg<634, "r634">, DwarfRegNum<[634]>;
|
||||
def R635 : AMDILReg<635, "r635">, DwarfRegNum<[635]>;
|
||||
def R636 : AMDILReg<636, "r636">, DwarfRegNum<[636]>;
|
||||
def R637 : AMDILReg<637, "r637">, DwarfRegNum<[637]>;
|
||||
def R638 : AMDILReg<638, "r638">, DwarfRegNum<[638]>;
|
||||
def R639 : AMDILReg<639, "r639">, DwarfRegNum<[639]>;
|
||||
def R640 : AMDILReg<640, "r640">, DwarfRegNum<[640]>;
|
||||
def R641 : AMDILReg<641, "r641">, DwarfRegNum<[641]>;
|
||||
def R642 : AMDILReg<642, "r642">, DwarfRegNum<[642]>;
|
||||
def R643 : AMDILReg<643, "r643">, DwarfRegNum<[643]>;
|
||||
def R644 : AMDILReg<644, "r644">, DwarfRegNum<[644]>;
|
||||
def R645 : AMDILReg<645, "r645">, DwarfRegNum<[645]>;
|
||||
def R646 : AMDILReg<646, "r646">, DwarfRegNum<[646]>;
|
||||
def R647 : AMDILReg<647, "r647">, DwarfRegNum<[647]>;
|
||||
def R648 : AMDILReg<648, "r648">, DwarfRegNum<[648]>;
|
||||
def R649 : AMDILReg<649, "r649">, DwarfRegNum<[649]>;
|
||||
def R650 : AMDILReg<650, "r650">, DwarfRegNum<[650]>;
|
||||
def R651 : AMDILReg<651, "r651">, DwarfRegNum<[651]>;
|
||||
def R652 : AMDILReg<652, "r652">, DwarfRegNum<[652]>;
|
||||
def R653 : AMDILReg<653, "r653">, DwarfRegNum<[653]>;
|
||||
def R654 : AMDILReg<654, "r654">, DwarfRegNum<[654]>;
|
||||
def R655 : AMDILReg<655, "r655">, DwarfRegNum<[655]>;
|
||||
def R656 : AMDILReg<656, "r656">, DwarfRegNum<[656]>;
|
||||
def R657 : AMDILReg<657, "r657">, DwarfRegNum<[657]>;
|
||||
def R658 : AMDILReg<658, "r658">, DwarfRegNum<[658]>;
|
||||
def R659 : AMDILReg<659, "r659">, DwarfRegNum<[659]>;
|
||||
def R660 : AMDILReg<660, "r660">, DwarfRegNum<[660]>;
|
||||
def R661 : AMDILReg<661, "r661">, DwarfRegNum<[661]>;
|
||||
def R662 : AMDILReg<662, "r662">, DwarfRegNum<[662]>;
|
||||
def R663 : AMDILReg<663, "r663">, DwarfRegNum<[663]>;
|
||||
def R664 : AMDILReg<664, "r664">, DwarfRegNum<[664]>;
|
||||
def R665 : AMDILReg<665, "r665">, DwarfRegNum<[665]>;
|
||||
def R666 : AMDILReg<666, "r666">, DwarfRegNum<[666]>;
|
||||
def R667 : AMDILReg<667, "r667">, DwarfRegNum<[667]>;
|
||||
def R668 : AMDILReg<668, "r668">, DwarfRegNum<[668]>;
|
||||
def R669 : AMDILReg<669, "r669">, DwarfRegNum<[669]>;
|
||||
def R670 : AMDILReg<670, "r670">, DwarfRegNum<[670]>;
|
||||
def R671 : AMDILReg<671, "r671">, DwarfRegNum<[671]>;
|
||||
def R672 : AMDILReg<672, "r672">, DwarfRegNum<[672]>;
|
||||
def R673 : AMDILReg<673, "r673">, DwarfRegNum<[673]>;
|
||||
def R674 : AMDILReg<674, "r674">, DwarfRegNum<[674]>;
|
||||
def R675 : AMDILReg<675, "r675">, DwarfRegNum<[675]>;
|
||||
def R676 : AMDILReg<676, "r676">, DwarfRegNum<[676]>;
|
||||
def R677 : AMDILReg<677, "r677">, DwarfRegNum<[677]>;
|
||||
def R678 : AMDILReg<678, "r678">, DwarfRegNum<[678]>;
|
||||
def R679 : AMDILReg<679, "r679">, DwarfRegNum<[679]>;
|
||||
def R680 : AMDILReg<680, "r680">, DwarfRegNum<[680]>;
|
||||
def R681 : AMDILReg<681, "r681">, DwarfRegNum<[681]>;
|
||||
def R682 : AMDILReg<682, "r682">, DwarfRegNum<[682]>;
|
||||
def R683 : AMDILReg<683, "r683">, DwarfRegNum<[683]>;
|
||||
def R684 : AMDILReg<684, "r684">, DwarfRegNum<[684]>;
|
||||
def R685 : AMDILReg<685, "r685">, DwarfRegNum<[685]>;
|
||||
def R686 : AMDILReg<686, "r686">, DwarfRegNum<[686]>;
|
||||
def R687 : AMDILReg<687, "r687">, DwarfRegNum<[687]>;
|
||||
def R688 : AMDILReg<688, "r688">, DwarfRegNum<[688]>;
|
||||
def R689 : AMDILReg<689, "r689">, DwarfRegNum<[689]>;
|
||||
def R690 : AMDILReg<690, "r690">, DwarfRegNum<[690]>;
|
||||
def R691 : AMDILReg<691, "r691">, DwarfRegNum<[691]>;
|
||||
def R692 : AMDILReg<692, "r692">, DwarfRegNum<[692]>;
|
||||
def R693 : AMDILReg<693, "r693">, DwarfRegNum<[693]>;
|
||||
def R694 : AMDILReg<694, "r694">, DwarfRegNum<[694]>;
|
||||
def R695 : AMDILReg<695, "r695">, DwarfRegNum<[695]>;
|
||||
def R696 : AMDILReg<696, "r696">, DwarfRegNum<[696]>;
|
||||
def R697 : AMDILReg<697, "r697">, DwarfRegNum<[697]>;
|
||||
def R698 : AMDILReg<698, "r698">, DwarfRegNum<[698]>;
|
||||
def R699 : AMDILReg<699, "r699">, DwarfRegNum<[699]>;
|
||||
def R700 : AMDILReg<700, "r700">, DwarfRegNum<[700]>;
|
||||
def R701 : AMDILReg<701, "r701">, DwarfRegNum<[701]>;
|
||||
def R702 : AMDILReg<702, "r702">, DwarfRegNum<[702]>;
|
||||
def R703 : AMDILReg<703, "r703">, DwarfRegNum<[703]>;
|
||||
def R704 : AMDILReg<704, "r704">, DwarfRegNum<[704]>;
|
||||
def R705 : AMDILReg<705, "r705">, DwarfRegNum<[705]>;
|
||||
def R706 : AMDILReg<706, "r706">, DwarfRegNum<[706]>;
|
||||
def R707 : AMDILReg<707, "r707">, DwarfRegNum<[707]>;
|
||||
def R708 : AMDILReg<708, "r708">, DwarfRegNum<[708]>;
|
||||
def R709 : AMDILReg<709, "r709">, DwarfRegNum<[709]>;
|
||||
def R710 : AMDILReg<710, "r710">, DwarfRegNum<[710]>;
|
||||
def R711 : AMDILReg<711, "r711">, DwarfRegNum<[711]>;
|
||||
def R712 : AMDILReg<712, "r712">, DwarfRegNum<[712]>;
|
||||
def R713 : AMDILReg<713, "r713">, DwarfRegNum<[713]>;
|
||||
def R714 : AMDILReg<714, "r714">, DwarfRegNum<[714]>;
|
||||
def R715 : AMDILReg<715, "r715">, DwarfRegNum<[715]>;
|
||||
def R716 : AMDILReg<716, "r716">, DwarfRegNum<[716]>;
|
||||
def R717 : AMDILReg<717, "r717">, DwarfRegNum<[717]>;
|
||||
def R718 : AMDILReg<718, "r718">, DwarfRegNum<[718]>;
|
||||
def R719 : AMDILReg<719, "r719">, DwarfRegNum<[719]>;
|
||||
def R720 : AMDILReg<720, "r720">, DwarfRegNum<[720]>;
|
||||
def R721 : AMDILReg<721, "r721">, DwarfRegNum<[721]>;
|
||||
def R722 : AMDILReg<722, "r722">, DwarfRegNum<[722]>;
|
||||
def R723 : AMDILReg<723, "r723">, DwarfRegNum<[723]>;
|
||||
def R724 : AMDILReg<724, "r724">, DwarfRegNum<[724]>;
|
||||
def R725 : AMDILReg<725, "r725">, DwarfRegNum<[725]>;
|
||||
def R726 : AMDILReg<726, "r726">, DwarfRegNum<[726]>;
|
||||
def R727 : AMDILReg<727, "r727">, DwarfRegNum<[727]>;
|
||||
def R728 : AMDILReg<728, "r728">, DwarfRegNum<[728]>;
|
||||
def R729 : AMDILReg<729, "r729">, DwarfRegNum<[729]>;
|
||||
def R730 : AMDILReg<730, "r730">, DwarfRegNum<[730]>;
|
||||
def R731 : AMDILReg<731, "r731">, DwarfRegNum<[731]>;
|
||||
def R732 : AMDILReg<732, "r732">, DwarfRegNum<[732]>;
|
||||
def R733 : AMDILReg<733, "r733">, DwarfRegNum<[733]>;
|
||||
def R734 : AMDILReg<734, "r734">, DwarfRegNum<[734]>;
|
||||
def R735 : AMDILReg<735, "r735">, DwarfRegNum<[735]>;
|
||||
def R736 : AMDILReg<736, "r736">, DwarfRegNum<[736]>;
|
||||
def R737 : AMDILReg<737, "r737">, DwarfRegNum<[737]>;
|
||||
def R738 : AMDILReg<738, "r738">, DwarfRegNum<[738]>;
|
||||
def R739 : AMDILReg<739, "r739">, DwarfRegNum<[739]>;
|
||||
def R740 : AMDILReg<740, "r740">, DwarfRegNum<[740]>;
|
||||
def R741 : AMDILReg<741, "r741">, DwarfRegNum<[741]>;
|
||||
def R742 : AMDILReg<742, "r742">, DwarfRegNum<[742]>;
|
||||
def R743 : AMDILReg<743, "r743">, DwarfRegNum<[743]>;
|
||||
def R744 : AMDILReg<744, "r744">, DwarfRegNum<[744]>;
|
||||
def R745 : AMDILReg<745, "r745">, DwarfRegNum<[745]>;
|
||||
def R746 : AMDILReg<746, "r746">, DwarfRegNum<[746]>;
|
||||
def R747 : AMDILReg<747, "r747">, DwarfRegNum<[747]>;
|
||||
def R748 : AMDILReg<748, "r748">, DwarfRegNum<[748]>;
|
||||
def R749 : AMDILReg<749, "r749">, DwarfRegNum<[749]>;
|
||||
def R750 : AMDILReg<750, "r750">, DwarfRegNum<[750]>;
|
||||
def R751 : AMDILReg<751, "r751">, DwarfRegNum<[751]>;
|
||||
def R752 : AMDILReg<752, "r752">, DwarfRegNum<[752]>;
|
||||
def R753 : AMDILReg<753, "r753">, DwarfRegNum<[753]>;
|
||||
def R754 : AMDILReg<754, "r754">, DwarfRegNum<[754]>;
|
||||
def R755 : AMDILReg<755, "r755">, DwarfRegNum<[755]>;
|
||||
def R756 : AMDILReg<756, "r756">, DwarfRegNum<[756]>;
|
||||
def R757 : AMDILReg<757, "r757">, DwarfRegNum<[757]>;
|
||||
def R758 : AMDILReg<758, "r758">, DwarfRegNum<[758]>;
|
||||
def R759 : AMDILReg<759, "r759">, DwarfRegNum<[759]>;
|
||||
def R760 : AMDILReg<760, "r760">, DwarfRegNum<[760]>;
|
||||
def R761 : AMDILReg<761, "r761">, DwarfRegNum<[761]>;
|
||||
def R762 : AMDILReg<762, "r762">, DwarfRegNum<[762]>;
|
||||
def R763 : AMDILReg<763, "r763">, DwarfRegNum<[763]>;
|
||||
def R764 : AMDILReg<764, "r764">, DwarfRegNum<[764]>;
|
||||
def R765 : AMDILReg<765, "r765">, DwarfRegNum<[765]>;
|
||||
def R766 : AMDILReg<766, "r766">, DwarfRegNum<[766]>;
|
||||
def R767 : AMDILReg<767, "r767">, DwarfRegNum<[767]>;
|
||||
|
||||
// All registers between 1000 and 1024 are reserved and cannot be used
|
||||
// unless commented in this section
|
||||
|
|
@ -831,134 +84,27 @@ def R1001: AMDILReg<1001, "r1001">, DwarfRegNum<[1001]>;
|
|||
def MEM : AMDILReg<999, "mem">, DwarfRegNum<[999]>;
|
||||
def RA : AMDILReg<998, "r998">, DwarfRegNum<[998]>;
|
||||
def FP : AMDILReg<997, "r997">, DwarfRegNum<[997]>;
|
||||
def GPRI8 : RegisterClass<"AMDIL", [i8], 8,
|
||||
(add (sequence "R%u", 1, 767), RA, SP, T1, T2, T3, T4, T5, SDP, R1010, R1011, R1001, R1002, R1003, R1004, R1005, R1006, R1007, R1008, MEM, R1012)>
|
||||
{
|
||||
let AltOrders = [(add (sequence "R%u", 1, 767))];
|
||||
let AltOrderSelect = [{
|
||||
return 1;
|
||||
}];
|
||||
}
|
||||
def GPRV2I8 : RegisterClass<"AMDIL", [v2i8], 16,
|
||||
(add (sequence "R%u", 1, 767), RA, SP, T1, T2, T3, T4, T5, SDP, R1010, R1011, R1001, R1002, R1003, R1004, R1005, R1006, R1007, R1008, MEM, R1012)>
|
||||
{
|
||||
let AltOrders = [(add (sequence "R%u", 1, 767))];
|
||||
let AltOrderSelect = [{
|
||||
return 1;
|
||||
}];
|
||||
}
|
||||
def GPRV4I8 : RegisterClass<"AMDIL", [v4i8], 32,
|
||||
(add (sequence "R%u", 1, 767), RA, SP, T1, T2, T3, T4, T5, SDP, R1010, R1011, R1001, R1002, R1003, R1004, R1005, R1006, R1007, R1008, MEM, R1012)>
|
||||
{
|
||||
let AltOrders = [(add (sequence "R%u", 1, 767))];
|
||||
let AltOrderSelect = [{
|
||||
return 1;
|
||||
}];
|
||||
}
|
||||
def GPRI16 : RegisterClass<"AMDIL", [i16], 16,
|
||||
(add (sequence "R%u", 1, 767), RA, SP, T1, T2, T3, T4, T5, SDP, R1010, R1011, R1001, R1002, R1003, R1004, R1005, R1006, R1007, R1008, MEM, R1012)>
|
||||
(add (sequence "R%u", 1, 20), RA, SP, T1, T2, T3, T4, T5, SDP, R1010, R1011, R1001, R1002, R1003, R1004, R1005, R1006, R1007, R1008, MEM, R1012)>
|
||||
{
|
||||
let AltOrders = [(add (sequence "R%u", 1, 767))];
|
||||
let AltOrderSelect = [{
|
||||
return 1;
|
||||
}];
|
||||
}
|
||||
def GPRV2I16 : RegisterClass<"AMDIL", [v2i16], 32,
|
||||
(add (sequence "R%u", 1, 767), RA, SP, T1, T2, T3, T4, T5, SDP, R1010, R1011, R1001, R1002, R1003, R1004, R1005, R1006, R1007, R1008, MEM, R1012)>
|
||||
{
|
||||
let AltOrders = [(add (sequence "R%u", 1, 767))];
|
||||
let AltOrderSelect = [{
|
||||
return 1;
|
||||
}];
|
||||
}
|
||||
def GPRV4I16 : RegisterClass<"AMDIL", [v4i16], 64,
|
||||
(add (sequence "R%u", 1, 767), RA, SP, T1, T2, T3, T4, T5, SDP, R1010, R1011, R1001, R1002, R1003, R1004, R1005, R1006, R1007, R1008, MEM, R1012)>
|
||||
{
|
||||
let AltOrders = [(add (sequence "R%u", 1, 767))];
|
||||
let AltOrders = [(add (sequence "R%u", 1, 20))];
|
||||
let AltOrderSelect = [{
|
||||
return 1;
|
||||
}];
|
||||
}
|
||||
def GPRI32 : RegisterClass<"AMDIL", [i32], 32,
|
||||
(add (sequence "R%u", 1, 767), RA, SP, T1, T2, T3, T4, T5, SDP, R1010, R1011, R1001, R1002, R1003, R1004, R1005, R1006, R1007, R1008, MEM, R1012)>
|
||||
(add (sequence "R%u", 1, 20), RA, SP, T1, T2, T3, T4, T5, SDP, R1010, R1011, R1001, R1002, R1003, R1004, R1005, R1006, R1007, R1008, MEM, R1012)>
|
||||
{
|
||||
let AltOrders = [(add (sequence "R%u", 1, 767))];
|
||||
let AltOrders = [(add (sequence "R%u", 1, 20))];
|
||||
let AltOrderSelect = [{
|
||||
return 1;
|
||||
}];
|
||||
}
|
||||
def GPRF32 : RegisterClass<"AMDIL", [f32], 32,
|
||||
(add (sequence "R%u", 1, 767), RA, SP, T1, T2, T3, T4, T5, SDP, R1010, R1011, R1001, R1002, R1003, R1004, R1005, R1006, R1007, R1008, MEM, R1012)>
|
||||
(add (sequence "R%u", 1, 20), RA, SP, T1, T2, T3, T4, T5, SDP, R1010, R1011, R1001, R1002, R1003, R1004, R1005, R1006, R1007, R1008, MEM, R1012)>
|
||||
{
|
||||
let AltOrders = [(add (sequence "R%u", 1, 767))];
|
||||
let AltOrders = [(add (sequence "R%u", 1, 20))];
|
||||
let AltOrderSelect = [{
|
||||
return 1;
|
||||
}];
|
||||
}
|
||||
// For 64 bit integer emulation, the lower 32 bits are in x
|
||||
// and the upper 32 bits are in y
|
||||
def GPRI64 : RegisterClass<"AMDIL", [i64], 64,
|
||||
(add (sequence "R%u", 1, 767), RA, SP, T1, T2, T3, T4, T5, SDP, R1010, R1011, R1001, R1002, R1003, R1004, R1005, R1006, R1007, R1008, MEM, R1012)>
|
||||
{
|
||||
let AltOrders = [(add (sequence "R%u", 1, 767))];
|
||||
let AltOrderSelect = [{
|
||||
return 1;
|
||||
}];
|
||||
}
|
||||
def GPRF64 : RegisterClass<"AMDIL", [f64], 64,
|
||||
(add (sequence "R%u", 1, 767), RA, SP, T1, T2, T3, T4, T5, SDP, R1010, R1011, R1001, R1002, R1003, R1004, R1005, R1006, R1007, R1008, MEM, R1012)>
|
||||
{
|
||||
let AltOrders = [(add (sequence "R%u", 1, 767))];
|
||||
let AltOrderSelect = [{
|
||||
return 1;
|
||||
}];
|
||||
}
|
||||
def GPRV4F32 : RegisterClass<"AMDIL", [v4f32], 128,
|
||||
(add (sequence "R%u", 1, 767), RA, SP, T1, T2, T3, T4, T5, SDP, R1010, R1011, R1001, R1002, R1003, R1004, R1005, R1006, R1007, R1008, MEM, R1012)>
|
||||
{
|
||||
let AltOrders = [(add (sequence "R%u", 1, 767))];
|
||||
let AltOrderSelect = [{
|
||||
return 1;
|
||||
}];
|
||||
}
|
||||
def GPRV4I32 : RegisterClass<"AMDIL", [v4i32], 128,
|
||||
(add (sequence "R%u", 1, 767), RA, SP, T1, T2, T3, T4, T5, SDP, R1010, R1011, R1001, R1002, R1003, R1004, R1005, R1006, R1007, R1008, MEM, R1012)>
|
||||
{
|
||||
let AltOrders = [(add (sequence "R%u", 1, 767))];
|
||||
let AltOrderSelect = [{
|
||||
return 1;
|
||||
}];
|
||||
}
|
||||
def GPRV2I32 : RegisterClass<"AMDIL", [v2i32], 64,
|
||||
(add (sequence "R%u", 1, 767), RA, SP, T1, T2, T3, T4, T5, SDP, R1010, R1011, R1001, R1002, R1003, R1004, R1005, R1006, R1007, R1008, MEM, R1012)>
|
||||
{
|
||||
let AltOrders = [(add (sequence "R%u", 1, 767))];
|
||||
let AltOrderSelect = [{
|
||||
return 1;
|
||||
}];
|
||||
}
|
||||
def GPRV2F32 : RegisterClass<"AMDIL", [v2f32], 64,
|
||||
(add (sequence "R%u", 1, 767), RA, SP, T1, T2, T3, T4, T5, SDP, R1010, R1011, R1001, R1002, R1003, R1004, R1005, R1006, R1007, R1008, MEM, R1012)>
|
||||
{
|
||||
let AltOrders = [(add (sequence "R%u", 1, 767))];
|
||||
let AltOrderSelect = [{
|
||||
return 1;
|
||||
}];
|
||||
}
|
||||
def GPRV2I64 : RegisterClass<"AMDIL", [v2i64], 128,
|
||||
(add (sequence "R%u", 1, 767), RA, SP, T1, T2, T3, T4, T5, SDP, R1010, R1011, R1001, R1002, R1003, R1004, R1005, R1006, R1007, R1008, MEM, R1012)>
|
||||
{
|
||||
let AltOrders = [(add (sequence "R%u", 1, 767))];
|
||||
let AltOrderSelect = [{
|
||||
return 1;
|
||||
}];
|
||||
}
|
||||
def GPRV2F64 : RegisterClass<"AMDIL", [v2f64], 128,
|
||||
(add (sequence "R%u", 1, 767), RA, SP, T1, T2, T3, T4, T5, SDP, R1010, R1011, R1001, R1002, R1003, R1004, R1005, R1006, R1007, R1008, MEM, R1012)>
|
||||
{
|
||||
let AltOrders = [(add (sequence "R%u", 1, 767))];
|
||||
let AltOrderSelect = [{
|
||||
return 1;
|
||||
}];
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -16,31 +16,20 @@
|
|||
// Macros that are used to help with switch statements for various data types
|
||||
// However, these macro's do not return anything unlike the second set below.
|
||||
#define ExpandCaseTo32bitIntTypes(Instr) \
|
||||
case Instr##_i8: \
|
||||
case Instr##_i16: \
|
||||
case Instr##_i32:
|
||||
|
||||
#define ExpandCaseTo32bitIntTruncTypes(Instr) \
|
||||
case Instr##_i16i8: \
|
||||
case Instr##_i32i8: \
|
||||
case Instr##_i32i16:
|
||||
|
||||
#define ExpandCaseToIntTypes(Instr) \
|
||||
ExpandCaseTo32bitIntTypes(Instr) \
|
||||
case Instr##_i64:
|
||||
ExpandCaseTo32bitIntTypes(Instr)
|
||||
|
||||
#define ExpandCaseToIntTruncTypes(Instr) \
|
||||
ExpandCaseTo32bitIntTruncTypes(Instr) \
|
||||
case Instr##_i64i8:\
|
||||
case Instr##_i64i16:\
|
||||
case Instr##_i64i32:\
|
||||
ExpandCaseTo32bitIntTruncTypes(Instr)
|
||||
|
||||
#define ExpandCaseToFloatTypes(Instr) \
|
||||
case Instr##_f32: \
|
||||
case Instr##_f64:
|
||||
|
||||
#define ExpandCaseToFloatTruncTypes(Instr) \
|
||||
case Instr##_f64f32:
|
||||
case Instr##_f32:
|
||||
|
||||
#define ExpandCaseTo32bitScalarTypes(Instr) \
|
||||
ExpandCaseTo32bitIntTypes(Instr) \
|
||||
|
|
@ -54,80 +43,21 @@ ExpandCaseToIntTypes(Instr)
|
|||
ExpandCaseToFloatTruncTypes(Instr) \
|
||||
ExpandCaseToIntTruncTypes(Instr)
|
||||
|
||||
// Vector versions of above macros
|
||||
#define ExpandCaseToVectorIntTypes(Instr) \
|
||||
case Instr##_v2i8: \
|
||||
case Instr##_v4i8: \
|
||||
case Instr##_v2i16: \
|
||||
case Instr##_v4i16: \
|
||||
case Instr##_v2i32: \
|
||||
case Instr##_v4i32: \
|
||||
case Instr##_v2i64:
|
||||
|
||||
#define ExpandCaseToVectorIntTruncTypes(Instr) \
|
||||
case Instr##_v2i16i8: \
|
||||
case Instr##_v4i16i8: \
|
||||
case Instr##_v2i32i8: \
|
||||
case Instr##_v4i32i8: \
|
||||
case Instr##_v2i32i16: \
|
||||
case Instr##_v4i32i16: \
|
||||
case Instr##_v2i64i8: \
|
||||
case Instr##_v2i64i16: \
|
||||
case Instr##_v2i64i32:
|
||||
|
||||
#define ExpandCaseToVectorFloatTypes(Instr) \
|
||||
case Instr##_v2f32: \
|
||||
case Instr##_v4f32: \
|
||||
case Instr##_v2f64:
|
||||
|
||||
#define ExpandCaseToVectorFloatTruncTypes(Instr) \
|
||||
case Instr##_v2f64f32:
|
||||
|
||||
#define ExpandCaseToVectorByteTypes(Instr) \
|
||||
case Instr##_v4i8:\
|
||||
case Instr##_v2i16: \
|
||||
case Instr##_v4i16:
|
||||
|
||||
#define ExpandCaseToAllVectorTypes(Instr) \
|
||||
ExpandCaseToVectorFloatTypes(Instr) \
|
||||
ExpandCaseToVectorIntTypes(Instr)
|
||||
|
||||
#define ExpandCaseToAllVectorTruncTypes(Instr) \
|
||||
ExpandCaseToVectorFloatTruncTypes(Instr) \
|
||||
ExpandCaseToVectorIntTruncTypes(Instr)
|
||||
|
||||
#define ExpandCaseToAllTypes(Instr) \
|
||||
ExpandCaseToAllVectorTypes(Instr) \
|
||||
ExpandCaseToAllScalarTypes(Instr)
|
||||
|
||||
#define ExpandCaseToAllTruncTypes(Instr) \
|
||||
ExpandCaseToAllVectorTruncTypes(Instr) \
|
||||
ExpandCaseToAllScalarTruncTypes(Instr)
|
||||
|
||||
#define ExpandCaseToPackedTypes(Instr) \
|
||||
case Instr##_v2i8: \
|
||||
case Instr##_v4i8: \
|
||||
case Instr##_v2i16: \
|
||||
case Instr##_v4i16:
|
||||
|
||||
#define ExpandCaseToByteShortTypes(Instr) \
|
||||
case Instr##_i8: \
|
||||
case Instr##_i16: \
|
||||
ExpandCaseToPackedTypes(Instr)
|
||||
|
||||
// Macros that expand into case statements with return values
|
||||
// Macros that expand into statements with return values
|
||||
#define ExpandCaseTo32bitIntReturn(Instr, Return) \
|
||||
case Instr##_i8: return Return##_i8;\
|
||||
case Instr##_i16: return Return##_i16;\
|
||||
case Instr##_i32: return Return##_i32;
|
||||
|
||||
#define ExpandCaseToIntReturn(Instr, Return) \
|
||||
ExpandCaseTo32bitIntReturn(Instr, Return) \
|
||||
case Instr##_i64: return Return##_i64;
|
||||
ExpandCaseTo32bitIntReturn(Instr, Return)
|
||||
|
||||
#define ExpandCaseToFloatReturn(Instr, Return) \
|
||||
case Instr##_f32: return Return##_f32;\
|
||||
case Instr##_f64: return Return##_f64;
|
||||
|
||||
#define ExpandCaseToAllScalarReturn(Instr, Return) \
|
||||
ExpandCaseToFloatReturn(Instr, Return) \
|
||||
|
|
@ -135,44 +65,11 @@ ExpandCaseToIntReturn(Instr, Return)
|
|||
|
||||
// These macros expand to common groupings of RegClass ID's
|
||||
#define ExpandCaseTo1CompRegID \
|
||||
case AMDIL::GPRI8RegClassID: \
|
||||
case AMDIL::GPRI16RegClassID: \
|
||||
case AMDIL::GPRI32RegClassID: \
|
||||
case AMDIL::GPRF32RegClassID:
|
||||
|
||||
#define ExpandCaseTo2CompRegID \
|
||||
case AMDIL::GPRI64RegClassID: \
|
||||
case AMDIL::GPRF64RegClassID: \
|
||||
case AMDIL::GPRV2I8RegClassID: \
|
||||
case AMDIL::GPRV2I16RegClassID: \
|
||||
case AMDIL::GPRV2I32RegClassID: \
|
||||
case AMDIL::GPRV2F32RegClassID:
|
||||
|
||||
// Macros that expand to case statements for specific bitlengths
|
||||
#define ExpandCaseTo8BitType(Instr) \
|
||||
case Instr##_i8:
|
||||
|
||||
#define ExpandCaseTo16BitType(Instr) \
|
||||
case Instr##_v2i8: \
|
||||
case Instr##_i16:
|
||||
|
||||
#define ExpandCaseTo32BitType(Instr) \
|
||||
case Instr##_v4i8: \
|
||||
case Instr##_v2i16: \
|
||||
case Instr##_i32: \
|
||||
case Instr##_f32:
|
||||
|
||||
#define ExpandCaseTo64BitType(Instr) \
|
||||
case Instr##_v4i16: \
|
||||
case Instr##_v2i32: \
|
||||
case Instr##_v2f32: \
|
||||
case Instr##_i64: \
|
||||
case Instr##_f64:
|
||||
|
||||
#define ExpandCaseTo128BitType(Instr) \
|
||||
case Instr##_v4i32: \
|
||||
case Instr##_v4f32: \
|
||||
case Instr##_v2i64: \
|
||||
case Instr##_v2f64:
|
||||
|
||||
#endif // AMDILUTILITYFUNCTIONS_H_
|
||||
|
|
|
|||
|
|
@ -55,21 +55,4 @@ def BARRIER_REGION : BinaryOpNoRet<IL_OP_BARRIER_REGION, (outs),
|
|||
(ins GPRI32:$flag, GPRI32:$id),
|
||||
"fence_threads_gds",
|
||||
[(int_AMDIL_barrier_region GPRI32:$flag, GPRI32:$id)]>;
|
||||
|
||||
def GET_REGION_ID : ILFormat<IL_OP_MOV, (outs GPRV4I32:$dst),
|
||||
(ins), !strconcat(IL_OP_MOV.Text, " $dst, r1022.xyz0"),
|
||||
[(set GPRV4I32:$dst, (int_AMDIL_get_region_id))]>;
|
||||
|
||||
def GET_REGION_LOCAL_ID : ILFormat<IL_OP_MOV, (outs GPRV4I32:$dst),
|
||||
(ins), !strconcat(IL_OP_MOV.Text, " $dst, r1022.xyz0"),
|
||||
[(set GPRV4I32:$dst, (int_AMDIL_get_region_local_id))]>;
|
||||
|
||||
def GET_REGION_SIZE : ILFormat<IL_OP_MOV, (outs GPRV4I32:$dst),
|
||||
(ins), !strconcat(IL_OP_MOV.Text, " $dst, cb0[10].xyz0"),
|
||||
[(set GPRV4I32:$dst, (int_AMDIL_get_region_size))]>;
|
||||
|
||||
def GET_NUM_REGIONS : ILFormat<IL_OP_MOV, (outs GPRV4I32:$dst),
|
||||
(ins), !strconcat(IL_OP_MOV.Text, " $dst, cb0[11].xyz0"),
|
||||
[(set GPRV4I32:$dst, (int_AMDIL_get_num_regions))]>;
|
||||
|
||||
}
|
||||
|
|
|
|||
|
|
@ -55,9 +55,6 @@ const TargetRegisterClass *
|
|||
R600RegisterInfo::getISARegClass(const TargetRegisterClass * rc) const
|
||||
{
|
||||
switch (rc->getID()) {
|
||||
case AMDIL::GPRV4F32RegClassID:
|
||||
case AMDIL::GPRV4I32RegClassID:
|
||||
return &AMDIL::R600_Reg128RegClass;
|
||||
case AMDIL::GPRF32RegClassID:
|
||||
case AMDIL::GPRI32RegClassID:
|
||||
return &AMDIL::R600_Reg32RegClass;
|
||||
|
|
|
|||
|
|
@ -66,11 +66,10 @@ class SGPR_32 <bits<8> num, string name> : SIReg<name> {
|
|||
}
|
||||
|
||||
|
||||
class VGPR_32 <bits<9> num, string name, Register gprf32_alias> : SIReg<name> {
|
||||
class VGPR_32 <bits<9> num, string name> : SIReg<name> {
|
||||
field bits<9> Num;
|
||||
|
||||
let Num = num;
|
||||
let Aliases = [gprf32_alias];
|
||||
}
|
||||
|
||||
class SGPR_64 <bits<8> num, string name, list<Register> subregs> :
|
||||
|
|
@ -132,13 +131,9 @@ for (my $i = 0; $i < $SGPR_COUNT; $i++) {
|
|||
}
|
||||
|
||||
my @VGPR;
|
||||
my @GPRF32;
|
||||
for (my $i = 0; $i < $VGPR_COUNT; $i++) {
|
||||
my $gprf32_num = $i + 1;
|
||||
my $gprf32_name = "R$gprf32_num";
|
||||
print "def VGPR$i : VGPR_32 <$i, \"VGPR$i\", $gprf32_name>;\n";
|
||||
print "def VGPR$i : VGPR_32 <$i, \"VGPR$i\">;\n";
|
||||
$VGPR[$i] = "VGPR$i";
|
||||
$GPRF32[$i] = $gprf32_name;
|
||||
}
|
||||
|
||||
print <<STRING;
|
||||
|
|
@ -169,9 +164,7 @@ def VReg_32 : RegisterClass<"AMDIL", [f32, i32], 32,
|
|||
>;
|
||||
|
||||
def AllReg_32 : RegisterClass<"AMDIL", [f32, i32], 32,
|
||||
(add VReg_32,
|
||||
SReg_32,
|
||||
(sequence "R%u", 1, $VGPR_COUNT))
|
||||
(add VReg_32, SReg_32)
|
||||
>;
|
||||
|
||||
def CCReg : RegisterClass<"AMDIL", [f32], 32, (add VCC, SCC)>;
|
||||
|
|
|
|||
|
|
@ -46,9 +46,6 @@ SIRegisterInfo::getISARegClass(const TargetRegisterClass * rc) const
|
|||
switch (rc->getID()) {
|
||||
case AMDIL::GPRF32RegClassID:
|
||||
return &AMDIL::VReg_32RegClass;
|
||||
case AMDIL::GPRV4F32RegClassID:
|
||||
case AMDIL::GPRV4I32RegClassID:
|
||||
return &AMDIL::VReg_128RegClass;
|
||||
default: return rc;
|
||||
}
|
||||
}
|
||||
|
|
|
|||
Loading…
Add table
Reference in a new issue