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radv: emit the PS epilog after the graphics pipeline

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Otherwise, SPI_SHADER_PGM_RSRC1_PS is overwritten when the graphics
pipeline is emitted.

Fixes: 5c362cde33 ("radv: update PS num_vgprs in case of epilogs rather than overallocating VGPRs")
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22310>
This commit is contained in:
Samuel Pitoiset 2023-04-05 12:05:10 +02:00 • committed by Marge Bot
parent 368a6f2330
commit 981f512037
1 changed files with 4 additions and 5 deletions
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9
src/amd/vulkan/radv_cmd_buffer.c
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@ -8870,11 +8870,10 @@ radv_emit_all_graphics_states(struct radv_cmd_buffer *cmd_buffer, const struct r
bool pipeline_is_dirty)
{
const struct radv_device *device = cmd_buffer->device;
struct radv_shader_part *ps_epilog = NULL;
bool late_scissor_emission;
if (cmd_buffer->state.shaders[MESA_SHADER_FRAGMENT]->info.ps.has_epilog) {
struct radv_shader_part *ps_epilog = NULL;
if (cmd_buffer->state.graphics_pipeline->ps_epilog) {
ps_epilog = cmd_buffer->state.graphics_pipeline->ps_epilog;
} else if ((cmd_buffer->state.emitted_graphics_pipeline != cmd_buffer->state.graphics_pipeline ||
@ -8895,9 +8894,6 @@ radv_emit_all_graphics_states(struct radv_cmd_buffer *cmd_buffer, const struct r
if (device->physical_device->rad_info.rbplus_allowed)
cmd_buffer->state.dirty |= RADV_CMD_DIRTY_RBPLUS;
}
if (ps_epilog)
radv_emit_ps_epilog_state(cmd_buffer, ps_epilog, pipeline_is_dirty);
}
if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_RBPLUS)
@ -8925,6 +8921,9 @@ radv_emit_all_graphics_states(struct radv_cmd_buffer *cmd_buffer, const struct r
if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_PIPELINE)
radv_emit_graphics_pipeline(cmd_buffer);
if (ps_epilog)
radv_emit_ps_epilog_state(cmd_buffer, ps_epilog, pipeline_is_dirty);
/* This should be before the cmd_buffer->state.dirty is cleared
* (excluding RADV_CMD_DIRTY_PIPELINE) and after
* cmd_buffer->state.context_roll_without_scissor_emitted is set. */