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anv: Embed isl_surf into anv_surface
This reduces struct anv_surface to just two members: an offset and the embedded isl_surf.
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parent
594e673fcc
commit
981ef2f02d
8 changed files with 39 additions and 61 deletions
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@ -147,7 +147,7 @@ anv_image_make_surface(const struct anv_device *dev,
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const struct anv_format *format,
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uint64_t *inout_image_size,
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uint32_t *inout_image_alignment,
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struct anv_surface *out_surface)
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struct anv_surface *out_anv_surf)
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{
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const VkImageCreateInfo *vk_info = anv_info->vk_info;
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@ -157,8 +157,7 @@ anv_image_make_surface(const struct anv_device *dev,
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[VK_IMAGE_TYPE_3D] = ISL_SURF_DIM_3D,
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};
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struct isl_surf isl_surf;
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isl_surf_init(&dev->isl_dev, &isl_surf,
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isl_surf_init(&dev->isl_dev, &out_anv_surf->isl,
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.dim = vk_to_isl_surf_dim[vk_info->imageType],
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.format = format->surface_format,
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.width = vk_info->extent.width,
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@ -172,17 +171,12 @@ anv_image_make_surface(const struct anv_device *dev,
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.usage = choose_isl_surf_usage(anv_info, format),
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.tiling_flags = choose_isl_tiling_flags(anv_info));
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*out_surface = (struct anv_surface) {
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.offset = align_u32(*inout_image_size, isl_surf.alignment),
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.stride = isl_surf.row_pitch,
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.tiling = isl_surf.tiling,
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.qpitch = isl_surf_get_array_pitch_sa_rows(&isl_surf),
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.h_align = isl_surf_get_lod_alignment_sa(&isl_surf).width,
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.v_align = isl_surf_get_lod_alignment_sa(&isl_surf).height,
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};
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out_anv_surf->offset = align_u32(*inout_image_size,
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out_anv_surf->isl.alignment);
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*inout_image_size = out_surface->offset + isl_surf.size;
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*inout_image_alignment = MAX(*inout_image_alignment, isl_surf.alignment);
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*inout_image_size = out_anv_surf->offset + out_anv_surf->isl.size;
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*inout_image_alignment = MAX(*inout_image_alignment,
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out_anv_surf->isl.alignment);
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return VK_SUCCESS;
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}
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@ -325,16 +319,9 @@ anv_surface_get_subresource_layout(struct anv_image *image,
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anv_assert(subresource->arrayLayer == 0);
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layout->offset = surface->offset;
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layout->rowPitch = surface->stride;
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/* Anvil's qpitch is in units of rows. Vulkan's depthPitch is in bytes. */
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layout->depthPitch = surface->qpitch * surface->stride;
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/* FINISHME: We really shouldn't be doing this calculation here */
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if (image->array_size > 1)
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layout->size = surface->qpitch * image->array_size;
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else
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layout->size = surface->stride * image->extent.height;
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layout->rowPitch = surface->isl.row_pitch;
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layout->depthPitch = isl_surf_get_array_pitch(&surface->isl);
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layout->size = surface->isl.size;
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}
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void anv_GetImageSubresourceLayout(
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@ -1372,30 +1372,15 @@ struct anv_image_view_info
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anv_image_view_info_for_vk_image_view_type(VkImageViewType type);
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/**
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* A proxy for the color surfaces, depth surfaces, and stencil surfaces.
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* Subsurface of an anv_image.
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*/
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struct anv_surface {
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struct isl_surf isl;
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/**
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* Offset from VkImage's base address, as bound by vkBindImageMemory().
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*/
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uint32_t offset;
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uint32_t stride; /**< RENDER_SURFACE_STATE.SurfacePitch */
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uint16_t qpitch; /**< RENDER_SURFACE_STATE.QPitch */
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/**
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* \name Alignment of miptree images, in units of pixels.
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*
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* These fields contain the real alignment values, not the values to be
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* given to the GPU. For example, if h_align is 4, then program the GPU
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* with HALIGN_4.
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* \{
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*/
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uint8_t h_align; /**< RENDER_SURFACE_STATE.SurfaceHorizontalAlignment */
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uint8_t v_align; /**< RENDER_SURFACE_STATE.SurfaceVerticalAlignment */
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/** \} */
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enum isl_tiling tiling;
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};
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struct anv_image {
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@ -678,7 +678,7 @@ wsi_wl_image_init(struct wsi_wl_swapchain *chain, struct wsi_wl_image *image,
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int ret = anv_gem_set_tiling(chain->base.device,
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image->memory->bo.gem_handle,
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surface->stride, I915_TILING_X);
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surface->isl.row_pitch, I915_TILING_X);
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if (ret) {
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/* FINISHME: Choose a better error. */
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result = vk_error(VK_ERROR_OUT_OF_DEVICE_MEMORY);
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@ -699,7 +699,7 @@ wsi_wl_image_init(struct wsi_wl_swapchain *chain, struct wsi_wl_image *image,
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chain->extent.height,
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chain->drm_format,
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surface->offset,
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surface->stride,
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surface->isl.row_pitch,
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0, 0, 0, 0 /* unused */);
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wl_display_roundtrip(chain->display->display);
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close(fd);
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@ -388,7 +388,7 @@ x11_surface_create_swapchain(struct anv_wsi_surface *wsi_surface,
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memory_h, 0);
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int ret = anv_gem_set_tiling(device, memory->bo.gem_handle,
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surface->stride, I915_TILING_X);
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surface->isl.row_pitch, I915_TILING_X);
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if (ret) {
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/* FINISHME: Choose a better error. */
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result = vk_errorf(VK_ERROR_OUT_OF_DEVICE_MEMORY,
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@ -415,7 +415,7 @@ x11_surface_create_swapchain(struct anv_wsi_surface *wsi_surface,
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image->size,
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pCreateInfo->imageExtent.width,
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pCreateInfo->imageExtent.height,
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surface->stride,
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surface->isl.row_pitch,
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depth, bpp, fd);
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chain->images[i].image = image;
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@ -707,7 +707,7 @@ cmd_buffer_emit_depth_stencil(struct anv_cmd_buffer *cmd_buffer)
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.StencilWriteEnable = has_stencil,
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.HierarchicalDepthBufferEnable = false,
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.SurfaceFormat = iview->format->depth_format,
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.SurfacePitch = image->depth_surface.stride - 1,
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.SurfacePitch = image->depth_surface.isl.row_pitch - 1,
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.SurfaceBaseAddress = {
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.bo = image->bo,
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.offset = image->depth_surface.offset,
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@ -758,7 +758,7 @@ cmd_buffer_emit_depth_stencil(struct anv_cmd_buffer *cmd_buffer)
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* The pitch must be set to 2x the value computed based on width,
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* as the stencil buffer is stored with two rows interleaved.
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*/
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.SurfacePitch = 2 * image->stencil_surface.stride - 1,
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.SurfacePitch = 2 * image->stencil_surface.isl.row_pitch - 1,
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.SurfaceBaseAddress = {
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.bo = image->bo,
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@ -238,18 +238,21 @@ genX(image_view_init)(struct anv_image_view *iview,
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depth = image->extent.depth;
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}
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const struct isl_extent3d lod_align_sa =
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isl_surf_get_lod_alignment_sa(&surface->isl);
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struct GENX(RENDER_SURFACE_STATE) surface_state = {
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.SurfaceType = image->surface_type,
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.SurfaceArray = image->array_size > 1,
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.SurfaceFormat = format->surface_format,
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.SurfaceVerticalAlignment = anv_valign[surface->v_align],
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.SurfaceHorizontalAlignment = anv_halign[surface->h_align],
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.SurfaceVerticalAlignment = anv_valign[lod_align_sa.height],
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.SurfaceHorizontalAlignment = anv_halign[lod_align_sa.width],
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/* From bspec (DevSNB, DevIVB): "Set Tile Walk to TILEWALK_XMAJOR if
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* Tiled Surface is False."
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*/
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.TiledSurface = surface->tiling != ISL_TILING_LINEAR,
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.TileWalk = surface->tiling == ISL_TILING_Y0 ?
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.TiledSurface = surface->isl.tiling != ISL_TILING_LINEAR,
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.TileWalk = surface->isl.tiling == ISL_TILING_Y0 ?
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TILEWALK_YMAJOR : TILEWALK_XMAJOR,
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.VerticalLineStride = 0,
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@ -260,7 +263,7 @@ genX(image_view_init)(struct anv_image_view *iview,
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.Height = image->extent.height - 1,
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.Width = image->extent.width - 1,
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.Depth = depth - 1,
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.SurfacePitch = surface->stride - 1,
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.SurfacePitch = surface->isl.row_pitch - 1,
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.MinimumArrayElement = range->baseArrayLayer,
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.NumberofMultisamples = MULTISAMPLECOUNT_1,
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.XOffset = 0,
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@ -659,7 +659,7 @@ cmd_buffer_emit_depth_stencil(struct anv_cmd_buffer *cmd_buffer)
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.StencilWriteEnable = has_stencil,
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.HierarchicalDepthBufferEnable = false,
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.SurfaceFormat = iview->format->depth_format,
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.SurfacePitch = image->depth_surface.stride - 1,
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.SurfacePitch = image->depth_surface.isl.row_pitch - 1,
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.SurfaceBaseAddress = {
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.bo = image->bo,
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.offset = image->depth_surface.offset,
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@ -671,7 +671,7 @@ cmd_buffer_emit_depth_stencil(struct anv_cmd_buffer *cmd_buffer)
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.MinimumArrayElement = 0,
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.DepthBufferObjectControlState = GENX(MOCS),
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.RenderTargetViewExtent = 1 - 1,
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.SurfaceQPitch = image->depth_surface.qpitch >> 2);
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.SurfaceQPitch = isl_surf_get_array_pitch_el_rows(&image->depth_surface.isl) >> 2);
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} else {
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/* Even when no depth buffer is present, the hardware requires that
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* 3DSTATE_DEPTH_BUFFER be programmed correctly. The Broadwell PRM says:
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@ -709,13 +709,13 @@ cmd_buffer_emit_depth_stencil(struct anv_cmd_buffer *cmd_buffer)
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* The pitch must be set to 2x the value computed based on width,
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* as the stencil buffer is stored with two rows interleaved.
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*/
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.SurfacePitch = 2 * image->stencil_surface.stride - 1,
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.SurfacePitch = 2 * image->stencil_surface.isl.row_pitch - 1,
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.SurfaceBaseAddress = {
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.bo = image->bo,
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.offset = image->offset + image->stencil_surface.offset,
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},
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.SurfaceQPitch = image->stencil_surface.stride >> 2);
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.SurfaceQPitch = isl_surf_get_array_pitch_el_rows(&image->stencil_surface.isl) >> 2);
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} else {
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anv_batch_emit(&cmd_buffer->batch, GENX(3DSTATE_STENCIL_BUFFER));
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}
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@ -183,13 +183,16 @@ genX(image_view_init)(struct anv_image_view *iview,
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[ISL_TILING_W] = WMAJOR,
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};
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const struct isl_extent3d lod_align_sa =
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isl_surf_get_lod_alignment_sa(&surface->isl);
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struct GENX(RENDER_SURFACE_STATE) surface_state = {
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.SurfaceType = image->surface_type,
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.SurfaceArray = image->array_size > 1,
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.SurfaceFormat = format_info->surface_format,
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.SurfaceVerticalAlignment = anv_valign[surface->v_align],
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.SurfaceHorizontalAlignment = anv_halign[surface->h_align],
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.TileMode = isl_to_gen_tiling[surface->tiling],
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.SurfaceVerticalAlignment = anv_valign[lod_align_sa.height],
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.SurfaceHorizontalAlignment = anv_halign[lod_align_sa.width],
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.TileMode = isl_to_gen_tiling[surface->isl.tiling],
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.VerticalLineStride = 0,
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.VerticalLineStrideOffset = 0,
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.SamplerL2BypassModeDisable = true,
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@ -202,11 +205,11 @@ genX(image_view_init)(struct anv_image_view *iview,
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*/
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.BaseMipLevel = 0.0,
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.SurfaceQPitch = surface->qpitch >> 2,
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.SurfaceQPitch = isl_surf_get_array_pitch_el_rows(&surface->isl) >> 2,
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.Height = image->extent.height - 1,
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.Width = image->extent.width - 1,
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.Depth = depth - 1,
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.SurfacePitch = surface->stride - 1,
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.SurfacePitch = surface->isl.row_pitch - 1,
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.RenderTargetViewExtent = rt_view_extent - 1,
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.MinimumArrayElement = range->baseArrayLayer,
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.NumberofMultisamples = MULTISAMPLECOUNT_1,
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