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freedreno/a6xx: Add stencilref register info

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Found by guessing.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5936>
This commit is contained in:
Connor Abbott 2020-07-16 15:48:41 +02:00 • committed by Marge Bot
parent 40b99bb79e
commit 981608ad04
1 changed files with 2 additions and 1 deletions
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3
src/freedreno/registers/a6xx.xml
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@ -2211,7 +2211,7 @@ to upconvert to 32b float internally?
<bitfield name="DUAL_COLOR_IN_ENABLE" pos="0" type="boolean"/>
<bitfield name="FRAG_WRITES_Z" pos="1" type="boolean"/>
<bitfield name="FRAG_WRITES_SAMPMASK" pos="2" type="boolean"/>
<bitfield name="UNK3" pos="3" type="boolean"/>
<bitfield name="FRAG_WRITES_STENCILREF" pos="3" type="boolean"/>
</reg32>
<reg32 offset="0x880c" name="RB_FS_OUTPUT_CNTL1">
<bitfield name="MRT" low="0" high="3" type="uint"/>
@ -3203,6 +3203,7 @@ to upconvert to 32b float internally?
<bitfield name="DUAL_COLOR_IN_ENABLE" pos="0" type="boolean"/>
<bitfield name="DEPTH_REGID" low="8" high="15" type="a3xx_regid"/>
<bitfield name="SAMPMASK_REGID" low="16" high="23" type="a3xx_regid"/>
<bitfield name="STENCILREF_REGID" low="24" high="31" type="a3xx_regid"/>
</reg32>
<reg32 offset="0xa98d" name="SP_FS_OUTPUT_CNTL1">
<bitfield name="MRT" low="0" high="3" type="uint"/>