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nvc0: implement support for maxwell texture headers
Adds support for the new TIC layout that's present on Maxwell GPUs, heavily based on the code for the existing layout. This code is required for GM20x support. While GM10x supports the older layout still, this commit switches it to use the updated version instead. Piglit testing shows zero regressions on GM107. Signed-off-by: Ben Skeggs <bskeggs@redhat.com> Acked-by: Ilia Mirkin <imirkin@alum.mit.edu>
This commit is contained in:
Ben Skeggs
parent
7333b0c20c
commit
97fc3fd559
3 changed files with 203 additions and 6 deletions
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@ -993,6 +993,14 @@ nvc0_screen_create(struct nouveau_device *dev)
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PUSH_DATAh(push, screen->txc->offset);
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PUSH_DATA (push, screen->txc->offset);
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PUSH_DATA (push, NVC0_TIC_MAX_ENTRIES - 1);
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if (screen->eng3d->oclass >= GM107_3D_CLASS) {
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screen->tic.maxwell = true;
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if (screen->eng3d->oclass == GM107_3D_CLASS) {
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screen->tic.maxwell =
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debug_get_bool_option("NOUVEAU_MAXWELL_TIC", true);
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IMMED_NVC0(push, SUBC_3D(0x0f10), screen->tic.maxwell);
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}
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}
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BEGIN_NVC0(push, NVC0_3D(TSC_ADDRESS_HIGH), 3);
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PUSH_DATAh(push, screen->txc->offset + 65536);
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@ -83,6 +83,7 @@ struct nvc0_screen {
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void **entries;
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int next;
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uint32_t lock[NVC0_TIC_MAX_ENTRIES / 32];
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bool maxwell;
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} tic;
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struct {
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@ -22,6 +22,7 @@
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#include "nvc0/nvc0_context.h"
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#include "nvc0/nvc0_resource.h"
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#include "nvc0/gm107_texture.xml.h"
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#include "nv50/g80_texture.xml.h"
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#include "nv50/g80_defs.xml.h"
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@ -59,12 +60,187 @@ nvc0_create_sampler_view(struct pipe_context *pipe,
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return nvc0_create_texture_view(pipe, res, templ, flags, templ->target);
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}
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struct pipe_sampler_view *
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nvc0_create_texture_view(struct pipe_context *pipe,
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struct pipe_resource *texture,
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const struct pipe_sampler_view *templ,
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uint32_t flags,
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enum pipe_texture_target target)
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static struct pipe_sampler_view *
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gm107_create_texture_view(struct pipe_context *pipe,
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struct pipe_resource *texture,
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const struct pipe_sampler_view *templ,
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uint32_t flags,
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enum pipe_texture_target target)
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{
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const struct util_format_description *desc;
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const struct nvc0_format *fmt;
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uint64_t address;
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uint32_t *tic;
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uint32_t swz[4];
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uint32_t width, height;
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uint32_t depth;
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struct nv50_tic_entry *view;
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struct nv50_miptree *mt;
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bool tex_int;
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view = MALLOC_STRUCT(nv50_tic_entry);
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if (!view)
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return NULL;
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mt = nv50_miptree(texture);
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view->pipe = *templ;
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view->pipe.reference.count = 1;
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view->pipe.texture = NULL;
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view->pipe.context = pipe;
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view->id = -1;
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pipe_resource_reference(&view->pipe.texture, texture);
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tic = &view->tic[0];
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desc = util_format_description(view->pipe.format);
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tex_int = util_format_is_pure_integer(view->pipe.format);
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fmt = &nvc0_format_table[view->pipe.format];
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swz[0] = nv50_tic_swizzle(fmt, view->pipe.swizzle_r, tex_int);
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swz[1] = nv50_tic_swizzle(fmt, view->pipe.swizzle_g, tex_int);
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swz[2] = nv50_tic_swizzle(fmt, view->pipe.swizzle_b, tex_int);
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swz[3] = nv50_tic_swizzle(fmt, view->pipe.swizzle_a, tex_int);
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tic[0] = fmt->tic.format << GM107_TIC2_0_COMPONENTS_SIZES__SHIFT;
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tic[0] |= fmt->tic.type_r << GM107_TIC2_0_R_DATA_TYPE__SHIFT;
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tic[0] |= fmt->tic.type_g << GM107_TIC2_0_G_DATA_TYPE__SHIFT;
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tic[0] |= fmt->tic.type_b << GM107_TIC2_0_B_DATA_TYPE__SHIFT;
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tic[0] |= fmt->tic.type_a << GM107_TIC2_0_A_DATA_TYPE__SHIFT;
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tic[0] |= swz[0] << GM107_TIC2_0_X_SOURCE__SHIFT;
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tic[0] |= swz[1] << GM107_TIC2_0_Y_SOURCE__SHIFT;
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tic[0] |= swz[2] << GM107_TIC2_0_Z_SOURCE__SHIFT;
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tic[0] |= swz[3] << GM107_TIC2_0_W_SOURCE__SHIFT;
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address = mt->base.address;
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tic[3] = GM107_TIC2_3_LOD_ANISO_QUALITY_2;
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tic[4] = GM107_TIC2_4_SECTOR_PROMOTION_PROMOTE_TO_2_V;
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tic[4] |= GM107_TIC2_4_BORDER_SIZE_SAMPLER_COLOR;
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if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB)
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tic[4] |= GM107_TIC2_4_SRGB_CONVERSION;
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if (!(flags & NV50_TEXVIEW_SCALED_COORDS))
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tic[5] = GM107_TIC2_5_NORMALIZED_COORDS;
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else
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tic[5] = 0;
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/* check for linear storage type */
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if (unlikely(!nouveau_bo_memtype(nv04_resource(texture)->bo))) {
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if (texture->target == PIPE_BUFFER) {
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assert(!(tic[5] & GM107_TIC2_5_NORMALIZED_COORDS));
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width = view->pipe.u.buf.last_element - view->pipe.u.buf.first_element;
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address +=
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view->pipe.u.buf.first_element * desc->block.bits / 8;
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tic[2] = GM107_TIC2_2_HEADER_VERSION_ONE_D_BUFFER;
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tic[3] |= width >> 16;
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tic[4] |= GM107_TIC2_4_TEXTURE_TYPE_ONE_D_BUFFER;
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tic[4] |= width & 0xffff;
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} else {
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assert(!(mt->level[0].pitch & 0x1f));
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/* must be 2D texture without mip maps */
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tic[2] = GM107_TIC2_2_HEADER_VERSION_PITCH;
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tic[4] |= GM107_TIC2_4_TEXTURE_TYPE_TWO_D_NO_MIPMAP;
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tic[3] |= mt->level[0].pitch >> 5;
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tic[4] |= mt->base.base.width0 - 1;
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tic[5] |= 0 << GM107_TIC2_5_DEPTH_MINUS_ONE__SHIFT;
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tic[5] |= mt->base.base.height0 - 1;
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}
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tic[1] = address;
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tic[2] |= address >> 32;
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tic[6] = 0;
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tic[7] = 0;
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return &view->pipe;
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}
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tic[2] = GM107_TIC2_2_HEADER_VERSION_BLOCKLINEAR;
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tic[3] |=
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((mt->level[0].tile_mode & 0x0f0) >> 4 << 3) |
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((mt->level[0].tile_mode & 0xf00) >> 8 << 6);
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depth = MAX2(mt->base.base.array_size, mt->base.base.depth0);
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if (mt->base.base.array_size > 1) {
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/* there doesn't seem to be a base layer field in TIC */
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address += view->pipe.u.tex.first_layer * mt->layer_stride;
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depth = view->pipe.u.tex.last_layer - view->pipe.u.tex.first_layer + 1;
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}
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tic[1] = address;
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tic[2] |= address >> 32;
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switch (target) {
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case PIPE_TEXTURE_1D:
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tic[4] |= GM107_TIC2_4_TEXTURE_TYPE_ONE_D;
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break;
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case PIPE_TEXTURE_2D:
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tic[4] |= GM107_TIC2_4_TEXTURE_TYPE_TWO_D;
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break;
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case PIPE_TEXTURE_RECT:
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tic[4] |= GM107_TIC2_4_TEXTURE_TYPE_TWO_D;
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break;
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case PIPE_TEXTURE_3D:
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tic[4] |= GM107_TIC2_4_TEXTURE_TYPE_THREE_D;
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break;
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case PIPE_TEXTURE_CUBE:
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depth /= 6;
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tic[4] |= GM107_TIC2_4_TEXTURE_TYPE_CUBEMAP;
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break;
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case PIPE_TEXTURE_1D_ARRAY:
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tic[4] |= GM107_TIC2_4_TEXTURE_TYPE_ONE_D_ARRAY;
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break;
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case PIPE_TEXTURE_2D_ARRAY:
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tic[4] |= GM107_TIC2_4_TEXTURE_TYPE_TWO_D_ARRAY;
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break;
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case PIPE_TEXTURE_CUBE_ARRAY:
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depth /= 6;
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tic[4] |= GM107_TIC2_4_TEXTURE_TYPE_CUBE_ARRAY;
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break;
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default:
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unreachable("unexpected/invalid texture target");
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}
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tic[3] |= (flags & NV50_TEXVIEW_FILTER_MSAA8) ?
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GM107_TIC2_3_USE_HEADER_OPT_CONTROL :
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GM107_TIC2_3_LOD_ANISO_QUALITY_HIGH |
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GM107_TIC2_3_LOD_ISO_QUALITY_HIGH;
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if (flags & NV50_TEXVIEW_ACCESS_RESOLVE) {
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width = mt->base.base.width0 << mt->ms_x;
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height = mt->base.base.height0 << mt->ms_y;
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} else {
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width = mt->base.base.width0;
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height = mt->base.base.height0;
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}
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tic[4] |= width - 1;
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tic[5] |= (height - 1) & 0xffff;
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tic[5] |= (depth - 1) << GM107_TIC2_5_DEPTH_MINUS_ONE__SHIFT;
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tic[3] |= mt->base.base.last_level << GM107_TIC2_3_MAX_MIP_LEVEL__SHIFT;
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/* sampling points: (?) */
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if ((flags & NV50_TEXVIEW_ACCESS_RESOLVE) && mt->ms_x > 1) {
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tic[6] = GM107_TIC2_6_ANISO_FINE_SPREAD_MODIFIER_CONST_TWO;
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tic[6] |= GM107_TIC2_6_MAX_ANISOTROPY_2_TO_1;
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} else {
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tic[6] = GM107_TIC2_6_ANISO_FINE_SPREAD_FUNC_TWO;
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tic[6] |= GM107_TIC2_6_ANISO_COARSE_SPREAD_FUNC_ONE;
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}
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tic[7] = (view->pipe.u.tex.last_level << 4) | view->pipe.u.tex.first_level;
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tic[7] |= mt->ms_mode << GM107_TIC2_7_MULTI_SAMPLE_COUNT__SHIFT;
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return &view->pipe;
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}
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static struct pipe_sampler_view *
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gf100_create_texture_view(struct pipe_context *pipe,
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struct pipe_resource *texture,
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const struct pipe_sampler_view *templ,
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uint32_t flags,
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enum pipe_texture_target target)
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{
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const struct util_format_description *desc;
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const struct nvc0_format *fmt;
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@ -221,6 +397,18 @@ nvc0_create_texture_view(struct pipe_context *pipe,
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return &view->pipe;
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}
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struct pipe_sampler_view *
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nvc0_create_texture_view(struct pipe_context *pipe,
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struct pipe_resource *texture,
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const struct pipe_sampler_view *templ,
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uint32_t flags,
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enum pipe_texture_target target)
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{
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if (nvc0_context(pipe)->screen->tic.maxwell)
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return gm107_create_texture_view(pipe, texture, templ, flags, target);
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return gf100_create_texture_view(pipe, texture, templ, flags, target);
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}
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static void
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nvc0_update_tic(struct nvc0_context *nvc0, struct nv50_tic_entry *tic,
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struct nv04_resource *res)
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