anv: add restrictions for 3DSTATE_RASTER::AntiAliasingEnable

Field must be disabled if any render targets have integer
format, additionally for Gfx12+ field must be disabled when
num multisamples > 1 or forced multisample count > 1.

Cc: mesa-stable
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20671>
(cherry picked from commit 9b37ef40f8)

.pick_status.json

@@ -40,7 +40,7 @@
         "description": "anv: add restrictions for 3DSTATE_RASTER::AntiAliasingEnable",
         "nominated": true,
         "nomination_type": 0,
-        "resolution": 0,
+        "resolution": 1,
         "main_sha": null,
         "because_sha": null
     },

src/intel/vulkan/anv_private.h

@@ -76,6 +76,7 @@
 #include "vk_device.h"
 #include "vk_drm_syncobj.h"
 #include "vk_enum_defines.h"
+#include "vk_format.h"
 #include "vk_framebuffer.h"
 #include "vk_graphics_state.h"
 #include "vk_image.h"
@@ -2530,6 +2531,7 @@ struct anv_cmd_graphics_state {
    struct vk_sample_locations_state sample_locations;
 
    bool object_preemption;
+   bool has_uint_rt;
 };
 
 enum anv_depth_reg_mode {
@@ -3179,6 +3181,18 @@ anv_cmd_buffer_all_color_write_masked(const struct anv_cmd_buffer *cmd_buffer)
    return true;
 }
 
+static inline void
+anv_cmd_graphic_state_update_has_uint_rt(struct anv_cmd_graphics_state *state)
+{
+   state->has_uint_rt = false;
+   for (unsigned a = 0; a < state->color_att_count; a++) {
+      if (vk_format_is_int(state->color_att[a].vk_format)) {
+         state->has_uint_rt = true;
+         break;
+      }
+   }
+}
+
 #define ANV_DECL_GET_GRAPHICS_PROG_DATA_FUNC(prefix, stage)             \
 static inline const struct brw_##prefix##_prog_data *                   \
 get_##prefix##_prog_data(const struct anv_graphics_pipeline *pipeline)  \

src/intel/vulkan/genX_cmd_buffer.c

@@ -3619,6 +3619,8 @@ genX(BeginCommandBuffer)(
          gfx->stencil_att.vk_format =
             inheritance_info->stencilAttachmentFormat;
 
+         anv_cmd_graphic_state_update_has_uint_rt(gfx);
+
          cmd_buffer->state.gfx.dirty |= ANV_CMD_DIRTY_RENDER_TARGETS;
       }
    }
@@ -7095,6 +7097,8 @@ void genX(CmdBeginRendering)(
       }
    }
 
+   anv_cmd_graphic_state_update_has_uint_rt(gfx);
+
    const struct anv_image_view *fsr_iview = NULL;
    const VkRenderingFragmentShadingRateAttachmentInfoKHR *fsr_att =
       vk_find_struct_const(pRenderingInfo->pNext,

src/intel/vulkan/gfx8_cmd_buffer.c

@@ -449,8 +449,21 @@ genX(cmd_buffer_flush_dynamic_state)(struct anv_cmd_buffer *cmd_buffer)
                                line_mode, dyn->rs.line.width,
                                &api_mode, &msaa_raster_enable);
 
-      bool aa_enable = anv_rasterization_aa_mode(dynamic_raster_mode,
-                                                 line_mode);
+     /* From the Browadwell PRM, Volume 2, documentation for
+      * 3DSTATE_RASTER, "Antialiasing Enable":
+      *
+      * "This field must be disabled if any of the render targets
+      * have integer (UINT or SINT) surface format."
+      *
+      * Additionally internal documentation for Gfx12+ states:
+      *
+      * "This bit MUST not be set when NUM_MULTISAMPLES > 1 OR
+      *  FORCED_SAMPLE_COUNT > 1."
+      */
+      bool aa_enable =
+         anv_rasterization_aa_mode(dynamic_raster_mode, line_mode) &&
+         !cmd_buffer->state.gfx.has_uint_rt &&
+         !(GFX_VER >= 12 && cmd_buffer->state.gfx.samples > 1);
 
       bool depth_clip_enable =
          vk_rasterization_state_depth_clip_enable(&dyn->rs);