fdo-mirrors/mesa
1
0
Fork 0
mirror of https://gitlab.freedesktop.org/mesa/mesa.git synced 2026-05-05 05:18:08 +02:00
Code Issues Projects Releases Packages Wiki Activity Actions 2

r600g: don't use register mask for PA_CL_VS_OUT_CNTL

Browse source 
Reviewed-by: Dave Airlie <airlied@redhat.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Marek Olšák 2012-01-29 06:31:47 +01:00
parent 121940ecc7
commit 97acf2ca59
4 changed files with 15 additions and 30 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

16
src/gallium/drivers/r600/evergreen_state.c
View file

@ -2446,17 +2446,11 @@ void evergreen_pipe_shader_vs(struct pipe_context *ctx, struct r600_pipe_shader
R_03A200_SQ_LOOP_CONST_0 + (32 * 4), 0x01000FFF,
0xFFFFFFFF, NULL, 0);
r600_pipe_state_add_reg(rstate,
R_02881C_PA_CL_VS_OUT_CNTL,
S_02881C_VS_OUT_CCDIST0_VEC_ENA((rshader->clip_dist_write & 0x0F) != 0) |
S_02881C_VS_OUT_CCDIST1_VEC_ENA((rshader->clip_dist_write & 0xF0) != 0) |
S_02881C_VS_OUT_MISC_VEC_ENA(rshader->vs_out_misc_write) |
S_02881C_USE_VTX_POINT_SIZE(rshader->vs_out_point_size),
S_02881C_VS_OUT_CCDIST0_VEC_ENA(1) |
S_02881C_VS_OUT_CCDIST1_VEC_ENA(1) |
S_02881C_VS_OUT_MISC_VEC_ENA(1) |
S_02881C_USE_VTX_POINT_SIZE(1),
NULL, 0);
shader->pa_cl_vs_out_cntl =
S_02881C_VS_OUT_CCDIST0_VEC_ENA((rshader->clip_dist_write & 0x0F) != 0) |
S_02881C_VS_OUT_CCDIST1_VEC_ENA((rshader->clip_dist_write & 0xF0) != 0) |
S_02881C_VS_OUT_MISC_VEC_ENA(rshader->vs_out_misc_write) |
S_02881C_USE_VTX_POINT_SIZE(rshader->vs_out_point_size);
}
void evergreen_fetch_shader(struct pipe_context *ctx,

2
src/gallium/drivers/r600/r600_pipe.h
View file

@ -152,6 +152,7 @@ struct r600_pipe_shader {
struct tgsi_token *tokens;
unsigned sprite_coord_enable;
unsigned flatshade;
unsigned pa_cl_vs_out_cntl;
struct pipe_stream_output_info so;
};
@ -234,7 +235,6 @@ struct r600_pipe_context {
/* shader information */
boolean two_side;
unsigned user_clip_plane_enable;
unsigned clip_dist_enable;
unsigned sprite_coord_enable;
boolean export_16bpc;
unsigned alpha_ref;

16
src/gallium/drivers/r600/r600_state.c
View file

@ -2226,17 +2226,11 @@ void r600_pipe_shader_vs(struct pipe_context *ctx, struct r600_pipe_shader *shad
R_03E200_SQ_LOOP_CONST_0 + (32 * 4), 0x01000FFF,
0xFFFFFFFF, NULL, 0);
r600_pipe_state_add_reg(rstate,
R_02881C_PA_CL_VS_OUT_CNTL,
S_02881C_VS_OUT_CCDIST0_VEC_ENA((rshader->clip_dist_write & 0x0F) != 0) |
S_02881C_VS_OUT_CCDIST1_VEC_ENA((rshader->clip_dist_write & 0xF0) != 0) |
S_02881C_VS_OUT_MISC_VEC_ENA(rshader->vs_out_misc_write) |
S_02881C_USE_VTX_POINT_SIZE(rshader->vs_out_point_size),
S_02881C_VS_OUT_CCDIST0_VEC_ENA(1) |
S_02881C_VS_OUT_CCDIST1_VEC_ENA(1) |
S_02881C_VS_OUT_MISC_VEC_ENA(1) |
S_02881C_USE_VTX_POINT_SIZE(1),
NULL, 0);
shader->pa_cl_vs_out_cntl =
S_02881C_VS_OUT_CCDIST0_VEC_ENA((rshader->clip_dist_write & 0x0F) != 0) |
S_02881C_VS_OUT_CCDIST1_VEC_ENA((rshader->clip_dist_write & 0xF0) != 0) |
S_02881C_VS_OUT_MISC_VEC_ENA(rshader->vs_out_misc_write) |
S_02881C_USE_VTX_POINT_SIZE(rshader->vs_out_point_size);
}
void r600_fetch_shader(struct pipe_context *ctx,

11
src/gallium/drivers/r600/r600_state_common.c
View file

@ -623,14 +623,12 @@ static void r600_update_derived_state(struct r600_pipe_context *rctx)
struct pipe_context * ctx = (struct pipe_context*)rctx;
struct r600_pipe_state rstate;
unsigned user_clip_plane_enable;
unsigned clip_dist_enable;
if (rctx->vs_shader->shader.clip_dist_write || rctx->vs_shader->shader.vs_prohibit_ucps)
user_clip_plane_enable = 0;
else
user_clip_plane_enable = rctx->rasterizer->clip_plane_enable & 0x3F;
clip_dist_enable = rctx->rasterizer->clip_plane_enable & rctx->vs_shader->shader.clip_dist_write;
rstate.nregs = 0;
if (user_clip_plane_enable != rctx->user_clip_plane_enable) {
@ -638,11 +636,6 @@ static void r600_update_derived_state(struct r600_pipe_context *rctx)
rctx->user_clip_plane_enable = user_clip_plane_enable;
}
if (clip_dist_enable != rctx->clip_dist_enable) {
r600_pipe_state_add_reg(&rstate, R_02881C_PA_CL_VS_OUT_CNTL, clip_dist_enable, 0xFF, NULL, 0);
rctx->clip_dist_enable = clip_dist_enable;
}
if (rstate.nregs)
r600_context_pipe_state_set(&rctx->ctx, &rstate);
@ -758,6 +751,7 @@ void r600_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *dinfo)
r600_pipe_state_add_reg(&rctx->vgt, R_028814_PA_SU_SC_MODE_CNTL, 0, 0xFFFFFFFF, NULL, 0);
if (rctx->chip_class <= R700)
r600_pipe_state_add_reg(&rctx->vgt, R_028808_CB_COLOR_CONTROL, rctx->cb_color_control, 0xFFFFFFFF, NULL, 0);
r600_pipe_state_add_reg(&rctx->vgt, R_02881C_PA_CL_VS_OUT_CNTL, 0, 0xFFFFFFFF, NULL, 0);
}
rctx->vgt.nregs = 0;
@ -784,6 +778,9 @@ void r600_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *dinfo)
}
if (rctx->chip_class <= R700)
r600_pipe_state_mod_reg(&rctx->vgt, rctx->cb_color_control);
r600_pipe_state_mod_reg(&rctx->vgt,
rctx->vs_shader->pa_cl_vs_out_cntl |
(rctx->rasterizer->clip_plane_enable & rctx->vs_shader->shader.clip_dist_write));
r600_context_pipe_state_set(&rctx->ctx, &rctx->vgt);