diff --git a/src/gallium/drivers/asahi/agx_batch.c b/src/gallium/drivers/asahi/agx_batch.c
index 0c4083caef3..caf61cdfb28 100644
--- a/src/gallium/drivers/asahi/agx_batch.c
+++ b/src/gallium/drivers/asahi/agx_batch.c
@@ -8,6 +8,7 @@
 #include "asahi/lib/decode.h"
 #include "util/bitset.h"
 #include "util/u_dynarray.h"
+#include "util/u_range.h"
 #include "agx_state.h"
 
 #define foreach_active(ctx, idx)                                               \
@@ -479,9 +480,9 @@ agx_batch_reads(struct agx_batch *batch, struct agx_resource *rsrc)
                            false);
 }
 
-void
-agx_batch_writes(struct agx_batch *batch, struct agx_resource *rsrc,
-                 unsigned level)
+static void
+agx_batch_writes_internal(struct agx_batch *batch, struct agx_resource *rsrc,
+                          unsigned level)
 {
    struct agx_context *ctx = batch->ctx;
    struct agx_batch *writer = agx_writer_get(ctx, rsrc->bo->handle);
@@ -511,6 +512,13 @@ agx_batch_writes(struct agx_batch *batch, struct agx_resource *rsrc,
     */
    agx_writer_remove(ctx, rsrc->bo->handle);
    agx_writer_add(ctx, agx_batch_idx(batch), rsrc->bo->handle);
+}
+
+void
+agx_batch_writes(struct agx_batch *batch, struct agx_resource *rsrc,
+                 unsigned level)
+{
+   agx_batch_writes_internal(batch, rsrc, level);
 
    if (rsrc->base.target == PIPE_BUFFER) {
       /* Assume BOs written by the GPU are fully valid */
@@ -519,6 +527,16 @@ agx_batch_writes(struct agx_batch *batch, struct agx_resource *rsrc,
    }
 }
 
+void
+agx_batch_writes_range(struct agx_batch *batch, struct agx_resource *rsrc,
+                       unsigned offset, unsigned size)
+{
+   assert(rsrc->base.target == PIPE_BUFFER);
+   agx_batch_writes_internal(batch, rsrc, 0);
+   util_range_add(&rsrc->base, &rsrc->valid_buffer_range, offset,
+                  offset + size);
+}
+
 static int
 agx_get_in_sync(struct agx_context *ctx)
 {
diff --git a/src/gallium/drivers/asahi/agx_pipe.c b/src/gallium/drivers/asahi/agx_pipe.c
index 0a350faa26d..d624651bea1 100644
--- a/src/gallium/drivers/asahi/agx_pipe.c
+++ b/src/gallium/drivers/asahi/agx_pipe.c
@@ -663,14 +663,11 @@ agx_batch_track_image(struct agx_batch *batch, struct pipe_image_view *image)
    struct agx_resource *rsrc = agx_resource(image->resource);
 
    if (image->shader_access & PIPE_IMAGE_ACCESS_WRITE) {
-      bool is_buffer = rsrc->base.target == PIPE_BUFFER;
-      unsigned level = is_buffer ? 0 : image->u.tex.level;
-
-      agx_batch_writes(batch, rsrc, level);
-
-      if (is_buffer) {
-         util_range_add(&rsrc->base, &rsrc->valid_buffer_range, 0,
-                        rsrc->base.width0);
+      if (rsrc->base.target == PIPE_BUFFER) {
+         agx_batch_writes_range(batch, rsrc, image->u.buf.offset,
+                                image->u.buf.size);
+      } else {
+         agx_batch_writes(batch, rsrc, image->u.tex.level);
       }
    } else {
       agx_batch_reads(batch, rsrc);
diff --git a/src/gallium/drivers/asahi/agx_state.h b/src/gallium/drivers/asahi/agx_state.h
index 9ded768d23c..c6543e41195 100644
--- a/src/gallium/drivers/asahi/agx_state.h
+++ b/src/gallium/drivers/asahi/agx_state.h
@@ -1015,6 +1015,8 @@ void agx_sync_batch_for_reason(struct agx_context *ctx, struct agx_batch *batch,
 void agx_batch_reads(struct agx_batch *batch, struct agx_resource *rsrc);
 void agx_batch_writes(struct agx_batch *batch, struct agx_resource *rsrc,
                       unsigned level);
+void agx_batch_writes_range(struct agx_batch *batch, struct agx_resource *rsrc,
+                            unsigned offset, unsigned size);
 void agx_batch_track_image(struct agx_batch *batch,
                            struct pipe_image_view *image);
 
diff --git a/src/gallium/drivers/asahi/agx_streamout.c b/src/gallium/drivers/asahi/agx_streamout.c
index aec2d3a6bd6..1b03aea388f 100644
--- a/src/gallium/drivers/asahi/agx_streamout.c
+++ b/src/gallium/drivers/asahi/agx_streamout.c
@@ -111,7 +111,8 @@ agx_batch_get_so_address(struct agx_batch *batch, unsigned buffer,
 
    /* Otherwise, write the target */
    struct agx_resource *rsrc = agx_resource(target->buffer);
-   agx_batch_writes(batch, rsrc, 0);
+   agx_batch_writes_range(batch, rsrc, target->buffer_offset,
+                          target->buffer_size);
 
    *size = target->buffer_size;
    return rsrc->bo->ptr.gpu + target->buffer_offset;
diff --git a/src/gallium/drivers/asahi/agx_uniforms.c b/src/gallium/drivers/asahi/agx_uniforms.c
index 27e2b49bcd2..e2d64810de5 100644
--- a/src/gallium/drivers/asahi/agx_uniforms.c
+++ b/src/gallium/drivers/asahi/agx_uniforms.c
@@ -156,7 +156,8 @@ agx_upload_stage_uniforms(struct agx_batch *batch, uint64_t textures,
          struct agx_resource *rsrc = agx_resource(sb->buffer);
 
          /* Assume SSBOs are written. TODO: Optimize read-only SSBOs */
-         agx_batch_writes(batch, rsrc, 0);
+         agx_batch_writes_range(batch, rsrc, sb->buffer_offset,
+                                sb->buffer_size);
 
          uniforms.ssbo_base[cb] = rsrc->bo->ptr.gpu + sb->buffer_offset;
          uniforms.ssbo_size[cb] = st->ssbo[cb].buffer_size;