diff --git a/src/nouveau/compiler/nak/opt_instr_sched_postpass.rs b/src/nouveau/compiler/nak/opt_instr_sched_postpass.rs
index 1e1909d11a0..8f5ce6be000 100644
--- a/src/nouveau/compiler/nak/opt_instr_sched_postpass.rs
+++ b/src/nouveau/compiler/nak/opt_instr_sched_postpass.rs
@@ -211,8 +211,7 @@ fn sched_buffer(
     let (new_order, cycle_count) = generate_order(&mut g, init_ready_list);
 
     // Apply the new instruction order
-    let mut instrs: Vec<Option<Instr>> =
-        instrs.into_iter().map(|instr| Some(instr)).collect();
+    let mut instrs: Vec<Option<Instr>> = instrs.into_iter().map(Some).collect();
     let instrs = new_order.into_iter().rev().map(move |i| {
         std::mem::take(&mut instrs[i]).expect("Instruction scheduled twice")
     });
diff --git a/src/nouveau/compiler/nak/sm32.rs b/src/nouveau/compiler/nak/sm32.rs
index 27a2c6a5563..4543c7edc18 100644
--- a/src/nouveau/compiler/nak/sm32.rs
+++ b/src/nouveau/compiler/nak/sm32.rs
@@ -358,7 +358,7 @@ impl SM32Encoder<'_> {
             RRR,
         }
         let src1 = AluSrc::from_src(src1);
-        let src2 = src2.map(|s| AluSrc::from_src(s));
+        let src2 = src2.map(AluSrc::from_src);
 
         if let Some(dst) = dst {
             self.set_dst(dst);