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ac/nir/mem_access_bit_sizes: split unaligned vec3 lds access to allow more read2/write2

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Foz-DB Navi21:
Totals from 77 (0.10% of 79377) affected shaders:
Instrs: 69787 -> 68745 (-1.49%); split: -1.51%, +0.02%
CodeSize: 367256 -> 360060 (-1.96%); split: -1.97%, +0.01%
VGPRs: 3896 -> 3880 (-0.41%)
Latency: 335403 -> 335297 (-0.03%); split: -0.11%, +0.08%
InvThroughput: 102766 -> 102931 (+0.16%); split: -0.09%, +0.25%
VClause: 1645 -> 1643 (-0.12%); split: -0.18%, +0.06%
SClause: 1434 -> 1433 (-0.07%)
Copies: 4280 -> 4283 (+0.07%); split: -0.56%, +0.63%
PreVGPRs: 2408 -> 2421 (+0.54%); split: -0.08%, +0.62%
VALU: 45557 -> 45646 (+0.20%); split: -0.10%, +0.29%
SALU: 6458 -> 6474 (+0.25%)

Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33448>
This commit is contained in:
Georg Lehmann 2025-02-07 16:24:05 +01:00 • committed by Marge Bot
parent 8b2b3e5704
commit 975be7ac5d
1 changed files with 6 additions and 0 deletions
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6
src/amd/common/nir/ac_nir_lower_mem_access_bit_sizes.c
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@ -74,6 +74,12 @@ lower_mem_access_cb(nir_intrinsic_op intrin, uint8_t bytes, uint8_t bit_size, ui
res.align = MIN2(bit_size / 8, 4); /* 64-bit access only requires 4 byte alignment. */
res.shift = nir_mem_access_shift_method_shift64;
if ((intrin == nir_intrinsic_load_shared || intrin == nir_intrinsic_store_shared)) {
/* Split unaligned shared access to create more read2/write2. */
if (combined_align < 16 && bytes < 16)
res.num_components = MIN2(res.num_components, 64 / bit_size);
}
if (!is_load)
return res;