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panfrost: remove panfrost_get_param and panfrost_get_paramf

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Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32955>
This commit is contained in:
Qiang Yu 2025-01-07 17:15:32 +08:00 • committed by Marge Bot
parent ced577b32e
commit 971645b558
1 changed files with 0 additions and 330 deletions
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330
src/gallium/drivers/panfrost/pan_screen.c
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@ -120,297 +120,6 @@ from_kmod_group_allow_priority_flags(
return flags;
}
static int
panfrost_get_param(struct pipe_screen *screen, enum pipe_cap param)
{
struct panfrost_device *dev = pan_device(screen);
/* Our GL 3.x implementation is WIP */
bool is_gl3 = dev->debug & PAN_DBG_GL3;
/* Native MRT is introduced with v5 */
bool has_mrt = (dev->arch >= 5);
switch (param) {
case PIPE_CAP_NPOT_TEXTURES:
case PIPE_CAP_MIXED_COLOR_DEPTH_BITS:
case PIPE_CAP_FRAGMENT_SHADER_TEXTURE_LOD:
case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
case PIPE_CAP_DEPTH_CLIP_DISABLE:
case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
case PIPE_CAP_FRONTEND_NOOP:
case PIPE_CAP_SAMPLE_SHADING:
case PIPE_CAP_FRAGMENT_SHADER_DERIVATIVES:
case PIPE_CAP_FRAMEBUFFER_NO_ATTACHMENT:
case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
case PIPE_CAP_SHADER_PACK_HALF_FLOAT:
case PIPE_CAP_HAS_CONST_BW:
return 1;
/* Removed in v9 (Valhall) */
case PIPE_CAP_DEPTH_CLIP_DISABLE_SEPARATE:
return dev->arch < 9;
case PIPE_CAP_MAX_RENDER_TARGETS:
case PIPE_CAP_FBFETCH:
case PIPE_CAP_FBFETCH_COHERENT:
return has_mrt ? 8 : 1;
case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
return 1;
case PIPE_CAP_OCCLUSION_QUERY:
case PIPE_CAP_PRIMITIVE_RESTART:
case PIPE_CAP_PRIMITIVE_RESTART_FIXED_INDEX:
return true;
case PIPE_CAP_ANISOTROPIC_FILTER:
return panfrost_device_gpu_rev(dev) >= dev->model->min_rev_anisotropic;
/* Compile side is done for Bifrost, Midgard TODO. Needs some kernel
* work to turn on, since CYCLE_COUNT_START needs to be issued. In
* kbase, userspace requests this via BASE_JD_REQ_PERMON. There is not
* yet way to request this with mainline TODO */
case PIPE_CAP_SHADER_CLOCK:
return 0;
case PIPE_CAP_VS_INSTANCEID:
case PIPE_CAP_TEXTURE_MULTISAMPLE:
case PIPE_CAP_SURFACE_SAMPLE_COUNT:
return true;
case PIPE_CAP_SAMPLER_VIEW_TARGET:
case PIPE_CAP_CLIP_HALFZ:
case PIPE_CAP_POLYGON_OFFSET_CLAMP:
case PIPE_CAP_TEXTURE_SWIZZLE:
case PIPE_CAP_TEXTURE_MIRROR_CLAMP_TO_EDGE:
case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
case PIPE_CAP_BLEND_EQUATION_SEPARATE:
case PIPE_CAP_INDEP_BLEND_ENABLE:
case PIPE_CAP_INDEP_BLEND_FUNC:
case PIPE_CAP_GENERATE_MIPMAP:
case PIPE_CAP_ACCELERATED:
case PIPE_CAP_UMA:
case PIPE_CAP_TEXTURE_FLOAT_LINEAR:
case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR:
case PIPE_CAP_SHADER_ARRAY_COMPONENTS:
case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
case PIPE_CAP_PACKED_UNIFORMS:
case PIPE_CAP_IMAGE_LOAD_FORMATTED:
case PIPE_CAP_CUBE_MAP_ARRAY:
case PIPE_CAP_COMPUTE:
case PIPE_CAP_INT64:
return 1;
case PIPE_CAP_COPY_BETWEEN_COMPRESSED_AND_PLAIN_FORMATS:
return 1;
case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
return PIPE_MAX_SO_BUFFERS;
case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
return PIPE_MAX_SO_OUTPUTS;
case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
case PIPE_CAP_STREAM_OUTPUT_INTERLEAVE_BUFFERS:
return 1;
case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
return 2048;
case PIPE_CAP_GLSL_FEATURE_LEVEL:
case PIPE_CAP_GLSL_FEATURE_LEVEL_COMPATIBILITY:
return is_gl3 ? 330 : 140;
case PIPE_CAP_ESSL_FEATURE_LEVEL:
return dev->arch >= 6 ? 320 : 310;
case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
return 16;
/* v7 (only) restricts component orders with AFBC. To workaround, we
* compose format swizzles with texture swizzles. pan_texture.c motsly
* handles this but we need to fix up the border colour.
*/
case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK:
if (dev->arch == 7 || dev->arch >= 10)
return PIPE_QUIRK_TEXTURE_BORDER_COLOR_SWIZZLE_FREEDRENO;
else
return 0;
case PIPE_CAP_MAX_TEXEL_BUFFER_ELEMENTS_UINT:
return PAN_MAX_TEXEL_BUFFER_ELEMENTS;
/* Must be at least 64 for correct behaviour */
case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
return 64;
case PIPE_CAP_QUERY_TIME_ELAPSED:
case PIPE_CAP_QUERY_TIMESTAMP:
return dev->kmod.props.gpu_can_query_timestamp &&
dev->kmod.props.timestamp_frequency != 0;
case PIPE_CAP_TIMER_RESOLUTION:
return pan_gpu_time_to_ns(dev, 1);
/* The hardware requires element alignment for data conversion to work
* as expected. If data conversion is not required, this restriction is
* lifted on Midgard at a performance penalty. We conservatively
* require element alignment for vertex buffers, using u_vbuf to
* translate to match the hardware requirement.
*
* This is less heavy-handed than PIPE_VERTEX_INPUT_ALIGNMENT_4BYTE, which
* would needlessly require alignment even for 8-bit formats.
*/
case PIPE_CAP_VERTEX_INPUT_ALIGNMENT:
return PIPE_VERTEX_INPUT_ALIGNMENT_ELEMENT;
case PIPE_CAP_MAX_TEXTURE_2D_SIZE:
return 1 << (PAN_MAX_MIP_LEVELS - 1);
case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
return PAN_MAX_MIP_LEVELS;
/* pixel coord is in integer sysval on bifrost. */
case PIPE_CAP_FS_COORD_PIXEL_CENTER_INTEGER:
return dev->arch >= 6;
case PIPE_CAP_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
return dev->arch < 6;
case PIPE_CAP_FS_COORD_ORIGIN_LOWER_LEFT:
/* Hardware is upper left */
return 0;
case PIPE_CAP_FS_COORD_ORIGIN_UPPER_LEFT:
case PIPE_CAP_TGSI_TEXCOORD:
return 1;
/* We would prefer varyings on Midgard, but proper sysvals on Bifrost */
case PIPE_CAP_FS_FACE_IS_INTEGER_SYSVAL:
case PIPE_CAP_FS_POSITION_IS_SYSVAL:
case PIPE_CAP_FS_POINT_IS_SYSVAL:
return dev->arch >= 6;
case PIPE_CAP_SEAMLESS_CUBE_MAP:
case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
return true;
case PIPE_CAP_MAX_VERTEX_ELEMENT_SRC_OFFSET:
return 0xffff;
case PIPE_CAP_TEXTURE_TRANSFER_MODES:
return 0;
case PIPE_CAP_ENDIANNESS:
return PIPE_ENDIAN_NATIVE;
case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS:
return 4;
case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET:
return -8;
case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET:
return 7;
case PIPE_CAP_VIDEO_MEMORY: {
uint64_t system_memory;
if (!os_get_total_physical_memory(&system_memory))
return 0;
return (int)(system_memory >> 20);
}
case PIPE_CAP_SHADER_STENCIL_EXPORT:
case PIPE_CAP_CONDITIONAL_RENDER:
case PIPE_CAP_CONDITIONAL_RENDER_INVERTED:
return true;
case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT:
return 4;
case PIPE_CAP_MAX_VARYINGS:
return dev->arch >= 9 ? 16 : 32;
/* Removed in v6 (Bifrost) */
case PIPE_CAP_GL_CLAMP:
case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
case PIPE_CAP_ALPHA_TEST:
return dev->arch <= 5;
/* Removed in v9 (Valhall). PRIMTIIVE_RESTART_FIXED_INDEX is of course
* still supported as it is core GLES3.0 functionality
*/
case PIPE_CAP_EMULATE_NONFIXED_PRIMITIVE_RESTART:
return dev->arch >= 9;
case PIPE_CAP_FLATSHADE:
case PIPE_CAP_TWO_SIDED_COLOR:
case PIPE_CAP_CLIP_PLANES:
return 0;
case PIPE_CAP_PACKED_STREAM_OUTPUT:
return 0;
case PIPE_CAP_VIEWPORT_TRANSFORM_LOWERED:
case PIPE_CAP_PSIZ_CLAMPED:
return 1;
case PIPE_CAP_NIR_IMAGES_AS_DEREF:
return 0;
case PIPE_CAP_DRAW_INDIRECT:
return 1;
case PIPE_CAP_MULTI_DRAW_INDIRECT:
return dev->arch >= 10;
case PIPE_CAP_START_INSTANCE:
case PIPE_CAP_DRAW_PARAMETERS:
return pan_is_bifrost(dev);
case PIPE_CAP_SUPPORTED_PRIM_MODES:
case PIPE_CAP_SUPPORTED_PRIM_MODES_WITH_RESTART: {
/* Mali supports GLES and QUADS. Midgard and v6 Bifrost
* support more */
uint32_t modes = BITFIELD_MASK(MESA_PRIM_QUADS + 1);
if (dev->arch <= 6) {
modes |= BITFIELD_BIT(MESA_PRIM_QUAD_STRIP);
modes |= BITFIELD_BIT(MESA_PRIM_POLYGON);
}
if (dev->arch >= 9) {
/* Although Valhall is supposed to support quads, they
* don't seem to work correctly. Disable to fix
* arb-provoking-vertex-render.
*/
modes &= ~BITFIELD_BIT(MESA_PRIM_QUADS);
}
return modes;
}
case PIPE_CAP_IMAGE_STORE_FORMATTED:
return 1;
case PIPE_CAP_NATIVE_FENCE_FD:
return 1;
case PIPE_CAP_CONTEXT_PRIORITY_MASK:
return from_kmod_group_allow_priority_flags(
dev->kmod.props.allowed_group_priorities_mask);
case PIPE_CAP_ASTC_DECODE_MODE:
return dev->arch >= 9 && (dev->compressed_formats & (1 << 30));
default:
return u_pipe_screen_get_param_defaults(screen, param);
}
}
static int
panfrost_get_shader_param(struct pipe_screen *screen,
enum pipe_shader_type shader,
@ -525,43 +234,6 @@ panfrost_get_shader_param(struct pipe_screen *screen,
return 0;
}
static float
panfrost_get_paramf(struct pipe_screen *screen, enum pipe_capf param)
{
switch (param) {
case PIPE_CAPF_MIN_LINE_WIDTH:
case PIPE_CAPF_MIN_LINE_WIDTH_AA:
case PIPE_CAPF_MIN_POINT_SIZE:
case PIPE_CAPF_MIN_POINT_SIZE_AA:
return 1;
case PIPE_CAPF_POINT_SIZE_GRANULARITY:
case PIPE_CAPF_LINE_WIDTH_GRANULARITY:
return 0.0625;
case PIPE_CAPF_MAX_LINE_WIDTH:
case PIPE_CAPF_MAX_LINE_WIDTH_AA:
case PIPE_CAPF_MAX_POINT_SIZE:
case PIPE_CAPF_MAX_POINT_SIZE_AA:
return 4095.9375;
case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
return 16.0;
case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
return 16.0; /* arbitrary */
case PIPE_CAPF_MIN_CONSERVATIVE_RASTER_DILATE:
case PIPE_CAPF_MAX_CONSERVATIVE_RASTER_DILATE:
case PIPE_CAPF_CONSERVATIVE_RASTER_DILATE_GRANULARITY:
return 0.0f;
default:
debug_printf("Unexpected PIPE_CAPF %d query\n", param);
return 0.0;
}
}
static uint32_t
pipe_to_pan_bind_flags(uint32_t pipe_bind_flags)
{
@ -1263,10 +935,8 @@ panfrost_create_screen(int fd, const struct pipe_screen_config *config,
screen->base.get_vendor = panfrost_get_vendor;
screen->base.get_device_vendor = panfrost_get_device_vendor;
screen->base.get_driver_query_info = panfrost_get_driver_query_info;
screen->base.get_param = panfrost_get_param;
screen->base.get_shader_param = panfrost_get_shader_param;
screen->base.get_compute_param = panfrost_get_compute_param;
screen->base.get_paramf = panfrost_get_paramf;
screen->base.get_timestamp = panfrost_get_timestamp;
screen->base.is_format_supported = panfrost_is_format_supported;
screen->base.query_dmabuf_modifiers = panfrost_query_dmabuf_modifiers;