diff --git a/src/gallium/drivers/d3d12/d3d12_compiler.cpp b/src/gallium/drivers/d3d12/d3d12_compiler.cpp
index 3fe15b06cf6..377a38bc623 100644
--- a/src/gallium/drivers/d3d12/d3d12_compiler.cpp
+++ b/src/gallium/drivers/d3d12/d3d12_compiler.cpp
@@ -1584,11 +1584,10 @@ d3d12_create_shader(struct d3d12_context *ctx,
    NIR_PASS_V(nir, d3d12_split_needed_varyings);
 
    if (nir->info.stage != MESA_SHADER_VERTEX) {
-      nir->info.inputs_read =
       dxil_reassign_driver_locations(nir, nir_var_shader_in,
                                      prev ? prev->current->nir->info.outputs_written : 0);
    } else {
-      nir->info.inputs_read = dxil_sort_by_driver_location(nir, nir_var_shader_in);
+      dxil_sort_by_driver_location(nir, nir_var_shader_in);
 
       uint32_t driver_loc = 0;
       nir_foreach_variable_with_modes(var, nir, nir_var_shader_in) {
@@ -1598,9 +1597,8 @@ d3d12_create_shader(struct d3d12_context *ctx,
    }
 
    if (nir->info.stage != MESA_SHADER_FRAGMENT) {
-      nir->info.outputs_written =
-            dxil_reassign_driver_locations(nir, nir_var_shader_out,
-                                            next ? next->current->nir->info.inputs_read : 0);
+      dxil_reassign_driver_locations(nir, nir_var_shader_out,
+                                     next ? next->current->nir->info.inputs_read : 0);
    } else {
       NIR_PASS_V(nir, nir_lower_fragcoord_wtrans);
       NIR_PASS_V(nir, dxil_nir_lower_sample_pos);
diff --git a/src/microsoft/compiler/dxil_nir.c b/src/microsoft/compiler/dxil_nir.c
index 6e484446376..a61c2773038 100644
--- a/src/microsoft/compiler/dxil_nir.c
+++ b/src/microsoft/compiler/dxil_nir.c
@@ -1533,16 +1533,10 @@ variable_location_cmp(const nir_variable* a, const nir_variable* b)
 }
 
 /* Order varyings according to driver location */
-uint64_t
+void
 dxil_sort_by_driver_location(nir_shader* s, nir_variable_mode modes)
 {
    nir_sort_variables_with_modes(s, variable_location_cmp, modes);
-
-   uint64_t result = 0;
-   nir_foreach_variable_with_modes(var, s, modes) {
-      result |= 1ull << var->data.location;
-   }
-   return result;
 }
 
 /* Sort PS outputs so that color outputs come first */
@@ -1618,7 +1612,7 @@ nir_var_to_dxil_sysvalue_type(nir_variable *var, uint64_t other_stage_mask)
 /* Order between stage values so that normal varyings come first,
  * then sysvalues and then system generated values.
  */
-uint64_t
+void
 dxil_reassign_driver_locations(nir_shader* s, nir_variable_mode modes,
    uint64_t other_stage_mask)
 {
@@ -1631,16 +1625,12 @@ dxil_reassign_driver_locations(nir_shader* s, nir_variable_mode modes,
 
    nir_sort_variables_with_modes(s, variable_location_cmp, modes);
 
-   uint64_t result = 0;
    unsigned driver_loc = 0, driver_patch_loc = 0;
    nir_foreach_variable_with_modes(var, s, modes) {
-      if (var->data.location < 64)
-         result |= 1ull << var->data.location;
       /* Overlap patches with non-patch */
       var->data.driver_location = var->data.patch ?
          driver_patch_loc++ : driver_loc++;
    }
-   return result;
 }
 
 static bool
diff --git a/src/microsoft/compiler/dxil_nir.h b/src/microsoft/compiler/dxil_nir.h
index edea4585add..1d77c29b729 100644
--- a/src/microsoft/compiler/dxil_nir.h
+++ b/src/microsoft/compiler/dxil_nir.h
@@ -59,13 +59,13 @@ bool dxil_nir_split_typed_samplers(nir_shader *shader);
 bool dxil_nir_lower_sysval_to_load_input(nir_shader *s, nir_variable **sysval_vars);
 bool dxil_nir_lower_vs_vertex_conversion(nir_shader *s, enum pipe_format target_formats[]);
 
-uint64_t
+void
 dxil_sort_by_driver_location(nir_shader* s, nir_variable_mode modes);
 
 void
 dxil_sort_ps_outputs(nir_shader* s);
 
-uint64_t
+void
 dxil_reassign_driver_locations(nir_shader* s, nir_variable_mode modes,
    uint64_t other_stage_mask);
 
diff --git a/src/microsoft/spirv_to_dxil/dxil_spirv_nir.c b/src/microsoft/spirv_to_dxil/dxil_spirv_nir.c
index 39c95cbda11..d386eee6130 100644
--- a/src/microsoft/spirv_to_dxil/dxil_spirv_nir.c
+++ b/src/microsoft/spirv_to_dxil/dxil_spirv_nir.c
@@ -772,13 +772,8 @@ dxil_spirv_nir_link(nir_shader *nir, nir_shader *prev_stage_nir,
       NIR_PASS_V(nir, dxil_nir_kill_undefined_varyings, prev_stage_nir->info.outputs_written, prev_stage_nir->info.patch_outputs_written);
       NIR_PASS_V(prev_stage_nir, dxil_nir_kill_unused_outputs, nir->info.inputs_read, nir->info.patch_inputs_read);
 
-      nir->info.inputs_read =
-         dxil_reassign_driver_locations(nir, nir_var_shader_in,
-                                        prev_stage_nir->info.outputs_written);
-
-      prev_stage_nir->info.outputs_written =
-         dxil_reassign_driver_locations(prev_stage_nir, nir_var_shader_out,
-                                        nir->info.inputs_read);
+      dxil_reassign_driver_locations(nir, nir_var_shader_in, prev_stage_nir->info.outputs_written);
+      dxil_reassign_driver_locations(prev_stage_nir, nir_var_shader_out, nir->info.inputs_read);
 
       if (nir->info.stage == MESA_SHADER_TESS_EVAL) {
          assert(prev_stage_nir->info.stage == MESA_SHADER_TESS_CTRL);
@@ -1104,8 +1099,7 @@ dxil_spirv_nir_passes(nir_shader *nir,
        * assigned even if there's just a single vertex shader in the
        * pipeline. The real linking happens in dxil_spirv_nir_link().
        */
-      nir->info.outputs_written =
-         dxil_reassign_driver_locations(nir, nir_var_shader_out, 0);
+      dxil_reassign_driver_locations(nir, nir_var_shader_out, 0);
    }
 
    if (nir->info.stage == MESA_SHADER_VERTEX) {
@@ -1115,11 +1109,9 @@ dxil_spirv_nir_passes(nir_shader *nir,
          var->data.driver_location = var->data.location - VERT_ATTRIB_GENERIC0;
       }
 
-      nir->info.inputs_read =
-         dxil_sort_by_driver_location(nir, nir_var_shader_in);
+      dxil_sort_by_driver_location(nir, nir_var_shader_in);
    } else {
-      nir->info.inputs_read =
-         dxil_reassign_driver_locations(nir, nir_var_shader_in, 0);
+      dxil_reassign_driver_locations(nir, nir_var_shader_in, 0);
    }
 
    nir_shader_gather_info(nir, nir_shader_get_entrypoint(nir));