fdo-mirrors/mesa
1
0
Fork 0
mirror of https://gitlab.freedesktop.org/mesa/mesa.git synced 2026-05-05 13:58:04 +02:00
Code Issues Projects Releases Packages Wiki Activity Actions 2

radv/gfx10: set cache control registers

Browse source 
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
This commit is contained in:
Samuel Pitoiset 2019-06-25 11:59:53 +02:00 • committed by Bas Nieuwenhuizen
parent 9a01eded0c
commit 96cd24588b
1 changed files with 21 additions and 0 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

21
src/amd/vulkan/si_cmd_buffer.c
View file

@ -299,6 +299,27 @@ si_emit_graphics(struct radv_physical_device *physical_device,
S_00B01C_CU_EN(0xffff) | S_00B01C_WAVE_LIMIT(0x3F));
}
if (physical_device->rad_info.chip_class >= GFX10) {
radeon_set_context_reg(cs, R_02807C_DB_RMI_L2_CACHE_CONTROL,
S_02807C_Z_WR_POLICY(V_02807C_CACHE_STREAM_WR) |
S_02807C_S_WR_POLICY(V_02807C_CACHE_STREAM_WR) |
S_02807C_HTILE_WR_POLICY(V_02807C_CACHE_STREAM_WR) |
S_02807C_ZPCPSD_WR_POLICY(V_02807C_CACHE_STREAM_WR) |
S_02807C_Z_RD_POLICY(V_02807C_CACHE_NOA_RD) |
S_02807C_S_RD_POLICY(V_02807C_CACHE_NOA_RD) |
S_02807C_HTILE_RD_POLICY(V_02807C_CACHE_NOA_RD));
radeon_set_context_reg(cs, R_028410_CB_RMI_GL2_CACHE_CONTROL,
S_028410_CMASK_WR_POLICY(V_028410_CACHE_STREAM_WR) |
S_028410_FMASK_WR_POLICY(V_028410_CACHE_STREAM_WR) |
S_028410_DCC_WR_POLICY(V_028410_CACHE_STREAM_WR) |
S_028410_COLOR_WR_POLICY(V_028410_CACHE_STREAM_WR) |
S_028410_CMASK_RD_POLICY(V_028410_CACHE_NOA_RD) |
S_028410_FMASK_RD_POLICY(V_028410_CACHE_NOA_RD) |
S_028410_DCC_RD_POLICY(V_028410_CACHE_NOA_RD) |
S_028410_COLOR_RD_POLICY(V_028410_CACHE_NOA_RD));
}
if (physical_device->rad_info.chip_class >= GFX8) {
uint32_t vgt_tess_distribution;