From 96b9f695d4945639d6291bc1697df369212545de Mon Sep 17 00:00:00 2001 From: Georg Lehmann Date: Wed, 18 Sep 2024 18:57:34 +0200 Subject: [PATCH] aco/isel: use upper bound for v_mul_u32_u24 The optimizer can use this. Foz-DB Navi31: Totals from 577 (0.73% of 79395) affected shaders: Instrs: 4209237 -> 4206859 (-0.06%); split: -0.06%, +0.00% CodeSize: 21511192 -> 21511984 (+0.00%); split: -0.02%, +0.02% SpillSGPRs: 679 -> 671 (-1.18%) Latency: 28448559 -> 28443863 (-0.02%); split: -0.04%, +0.03% InvThroughput: 5221932 -> 5218443 (-0.07%); split: -0.09%, +0.02% Copies: 297965 -> 298076 (+0.04%); split: -0.01%, +0.05% VALU: 2385304 -> 2383500 (-0.08%) SALU: 485553 -> 485533 (-0.00%); split: -0.01%, +0.00% Reviewed-by: Rhys Perry Part-of: --- src/amd/compiler/aco_instruction_selection.cpp | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/amd/compiler/aco_instruction_selection.cpp b/src/amd/compiler/aco_instruction_selection.cpp index 74dec748d65..a043f8f3af4 100644 --- a/src/amd/compiler/aco_instruction_selection.cpp +++ b/src/amd/compiler/aco_instruction_selection.cpp @@ -2262,7 +2262,7 @@ visit_alu_instr(isel_context* ctx, nir_alu_instr* instr) if (src0_ub <= 0xffffff && src1_ub <= 0xffffff) { bool nuw_16bit = src0_ub <= 0xffff && src1_ub <= 0xffff && src0_ub * src1_ub <= 0xffff; emit_vop2_instruction(ctx, instr, aco_opcode::v_mul_u32_u24, dst, - true /* commutative */, false, false, nuw_16bit); + true /* commutative */, false, false, nuw_16bit, 0x3); } else if (nir_src_is_const(instr->src[0].src)) { bld.v_mul_imm(Definition(dst), get_alu_src(ctx, instr->src[1]), nir_src_as_uint(instr->src[0].src), false);