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intel/brw: Delete old local common subexpression elimination pass
We no longer use this older pass, so there's no need to keep it. Reviewed-by: Caio Oliveira <caio.oliveira@intel.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28666>
This commit is contained in:
Kenneth Graunke
Marge Bot
parent
8f09c58ddc
commit
9690bd369d
2 changed files with 1 additions and 209 deletions
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@ -671,7 +671,6 @@ bool brw_fs_opt_cmod_propagation(fs_visitor &s);
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bool brw_fs_opt_combine_constants(fs_visitor &s);
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bool brw_fs_opt_compact_virtual_grfs(fs_visitor &s);
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bool brw_fs_opt_copy_propagation(fs_visitor &s);
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bool brw_fs_opt_cse(fs_visitor &s);
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bool brw_fs_opt_cse_defs(fs_visitor &s);
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bool brw_fs_opt_dead_code_eliminate(fs_visitor &s);
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bool brw_fs_opt_dead_control_flow_eliminate(fs_visitor &s);
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@ -30,24 +30,11 @@
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/** @file brw_fs_cse.cpp
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*
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* Support for local common subexpression elimination.
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*
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* See Muchnick's Advanced Compiler Design and Implementation, section
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* 13.1 (p378).
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* Support for SSA-based global Common Subexpression Elimination (CSE).
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*/
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using namespace brw;
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namespace {
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struct aeb_entry : public exec_node {
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/** The instruction that generates the expression value. */
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fs_inst *generator;
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/** The temporary where the value is stored. */
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fs_reg tmp;
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};
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}
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static bool
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is_expression(const fs_visitor *v, const fs_inst *const inst)
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{
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@ -251,200 +238,6 @@ instructions_match(fs_inst *a, fs_inst *b, bool *negate)
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operands_match(a, b, negate);
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}
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static void
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create_copy_instr(const fs_builder &bld, fs_inst *inst, fs_reg src, bool negate)
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{
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unsigned written = regs_written(inst);
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unsigned dst_width =
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DIV_ROUND_UP(inst->dst.component_size(inst->exec_size), REG_SIZE);
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fs_inst *copy;
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if (inst->opcode == SHADER_OPCODE_LOAD_PAYLOAD) {
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assert(src.file == VGRF);
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fs_reg *payload = ralloc_array(bld.shader->mem_ctx, fs_reg,
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inst->sources);
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for (int i = 0; i < inst->header_size; i++) {
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payload[i] = src;
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src.offset += REG_SIZE;
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}
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for (int i = inst->header_size; i < inst->sources; i++) {
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src.type = inst->src[i].type;
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payload[i] = src;
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src = offset(src, bld, 1);
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}
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copy = bld.LOAD_PAYLOAD(inst->dst, payload, inst->sources,
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inst->header_size);
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} else if (written != dst_width) {
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assert(src.file == VGRF);
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assert(written % dst_width == 0);
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const int sources = written / dst_width;
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fs_reg *payload = ralloc_array(bld.shader->mem_ctx, fs_reg, sources);
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for (int i = 0; i < sources; i++) {
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payload[i] = src;
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src = offset(src, bld, 1);
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}
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copy = bld.LOAD_PAYLOAD(inst->dst, payload, sources, 0);
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} else {
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copy = bld.MOV(inst->dst, src);
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copy->group = inst->group;
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copy->force_writemask_all = inst->force_writemask_all;
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copy->src[0].negate = negate;
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}
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assert(regs_written(copy) == written);
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}
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static bool
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brw_fs_opt_cse_local(fs_visitor &s, const fs_live_variables &live, bblock_t *block, int &ip)
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{
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const intel_device_info *devinfo = s.devinfo;
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bool progress = false;
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exec_list aeb;
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void *cse_ctx = ralloc_context(NULL);
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foreach_inst_in_block(fs_inst, inst, block) {
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/* Skip some cases. */
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if (is_expression(&s, inst) && !inst->is_partial_write() &&
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((inst->dst.file != ARF && inst->dst.file != FIXED_GRF) ||
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inst->dst.is_null()))
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{
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bool found = false;
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bool negate = false;
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foreach_in_list_use_after(aeb_entry, entry, &aeb) {
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/* Match current instruction's expression against those in AEB. */
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if (!(entry->generator->dst.is_null() && !inst->dst.is_null()) &&
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instructions_match(inst, entry->generator, &negate)) {
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found = true;
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progress = true;
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break;
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}
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}
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if (!found) {
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if (inst->opcode != BRW_OPCODE_MOV ||
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(inst->opcode == BRW_OPCODE_MOV &&
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inst->src[0].file == IMM &&
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inst->src[0].type == BRW_TYPE_VF)) {
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/* Our first sighting of this expression. Create an entry. */
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aeb_entry *entry = ralloc(cse_ctx, aeb_entry);
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entry->tmp = reg_undef;
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entry->generator = inst;
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aeb.push_tail(entry);
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}
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} else {
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/* This is at least our second sighting of this expression.
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* If we don't have a temporary already, make one.
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*/
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bool no_existing_temp = entry->tmp.file == BAD_FILE;
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if (no_existing_temp && !entry->generator->dst.is_null()) {
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const fs_builder ibld = fs_builder(&s, block, entry->generator)
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.at(block, entry->generator->next);
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int written = regs_written(entry->generator);
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entry->tmp = fs_reg(VGRF, s.alloc.allocate(written),
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entry->generator->dst.type);
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create_copy_instr(ibld, entry->generator, entry->tmp, false);
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entry->generator->dst = entry->tmp;
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}
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/* dest <- temp */
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if (!inst->dst.is_null()) {
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assert(inst->size_written == entry->generator->size_written);
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assert(inst->dst.type == entry->tmp.type);
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const fs_builder ibld(&s, block, inst);
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create_copy_instr(ibld, inst, entry->tmp, negate);
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}
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/* Set our iterator so that next time through the loop inst->next
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* will get the instruction in the basic block after the one we've
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* removed.
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*/
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fs_inst *prev = (fs_inst *)inst->prev;
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inst->remove(block);
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inst = prev;
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}
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}
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/* Discard jumps aren't represented in the CFG unfortunately, so we need
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* to make sure that they behave as a CSE barrier, since we lack global
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* dataflow information. This is particularly likely to cause problems
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* with instructions dependent on the current execution mask like
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* SHADER_OPCODE_FIND_LIVE_CHANNEL.
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*/
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if (inst->opcode == BRW_OPCODE_HALT ||
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inst->opcode == SHADER_OPCODE_HALT_TARGET)
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aeb.make_empty();
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foreach_in_list_safe(aeb_entry, entry, &aeb) {
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/* Kill all AEB entries that write a different value to or read from
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* the flag register if we just wrote it.
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*/
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if (inst->flags_written(devinfo)) {
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bool negate; /* dummy */
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if (entry->generator->flags_read(devinfo) ||
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(entry->generator->flags_written(devinfo) &&
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!instructions_match(inst, entry->generator, &negate))) {
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entry->remove();
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ralloc_free(entry);
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continue;
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}
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}
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for (int i = 0; i < entry->generator->sources; i++) {
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fs_reg *src_reg = &entry->generator->src[i];
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/* Kill all AEB entries that use the destination we just
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* overwrote.
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*/
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if (regions_overlap(inst->dst, inst->size_written,
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entry->generator->src[i],
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entry->generator->size_read(i))) {
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entry->remove();
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ralloc_free(entry);
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break;
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}
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/* Kill any AEB entries using registers that don't get reused any
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* more -- a sure sign they'll fail operands_match().
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*/
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if (src_reg->file == VGRF && live.vgrf_end[src_reg->nr] < ip) {
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entry->remove();
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ralloc_free(entry);
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break;
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}
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}
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}
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ip++;
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}
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ralloc_free(cse_ctx);
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return progress;
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}
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bool
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brw_fs_opt_cse(fs_visitor &s)
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{
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const fs_live_variables &live = s.live_analysis.require();
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bool progress = false;
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int ip = 0;
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foreach_block (block, s.cfg) {
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progress = brw_fs_opt_cse_local(s, live, block, ip) || progress;
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}
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if (progress)
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s.invalidate_analysis(DEPENDENCY_INSTRUCTIONS | DEPENDENCY_VARIABLES);
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return progress;
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}
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/* -------------------------------------------------------------------- */
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#define HASH(hash, data) XXH32(&(data), sizeof(data), hash)
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