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radv: do not re-emit the index buffer for every draw call

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It can only be changed when CmdBindIndexBuffer() is called
or when a secondary buffer is used. Though not always, but
let's re-emit the packets in this situation for now.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
This commit is contained in:
Samuel Pitoiset 2017-10-18 14:17:23 +02:00
parent e5480be0d1
commit 966d66f28f
1 changed files with 28 additions and 29 deletions
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57
src/amd/vulkan/radv_cmd_buffer.c
View file

@ -1400,6 +1400,27 @@ radv_emit_framebuffer_state(struct radv_cmd_buffer *cmd_buffer)
} }
} }
static void
radv_emit_index_buffer(struct radv_cmd_buffer *cmd_buffer)
{
struct radeon_winsys_cs *cs = cmd_buffer->cs;
if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
radeon_set_uconfig_reg_idx(cs, R_03090C_VGT_INDEX_TYPE,
2, cmd_buffer->state.index_type);
} else {
radeon_emit(cs, PKT3(PKT3_INDEX_TYPE, 0, 0));
radeon_emit(cs, cmd_buffer->state.index_type);
}
radeon_emit(cs, PKT3(PKT3_INDEX_BASE, 1, 0));
radeon_emit(cs, cmd_buffer->state.index_va);
radeon_emit(cs, cmd_buffer->state.index_va >> 32);
radeon_emit(cs, PKT3(PKT3_INDEX_BUFFER_SIZE, 0, 0));
radeon_emit(cs, cmd_buffer->state.max_index_count);
}
void radv_set_db_count_control(struct radv_cmd_buffer *cmd_buffer) void radv_set_db_count_control(struct radv_cmd_buffer *cmd_buffer)
{ {
uint32_t db_count_control; uint32_t db_count_control;
@ -1743,6 +1764,9 @@ radv_cmd_buffer_flush_state(struct radv_cmd_buffer *cmd_buffer,
if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_RENDER_TARGETS) if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_RENDER_TARGETS)
radv_emit_framebuffer_state(cmd_buffer); radv_emit_framebuffer_state(cmd_buffer);
if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_INDEX_BUFFER)
radv_emit_index_buffer(cmd_buffer);
ia_multi_vgt_param = si_get_ia_multi_vgt_param(cmd_buffer, instanced_draw, indirect_draw, draw_vertex_count); ia_multi_vgt_param = si_get_ia_multi_vgt_param(cmd_buffer, instanced_draw, indirect_draw, draw_vertex_count);
if (cmd_buffer->state.last_ia_multi_vgt_param != ia_multi_vgt_param) { if (cmd_buffer->state.last_ia_multi_vgt_param != ia_multi_vgt_param) {
if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9)
@ -2689,8 +2713,9 @@ void radv_CmdExecuteCommands(
/* After executing commands from secondary buffers we have to dirty /* After executing commands from secondary buffers we have to dirty
* some states. * some states.
*/ */
primary->state.dirty |= RADV_CMD_DIRTY_PIPELINE; primary->state.dirty |= RADV_CMD_DIRTY_PIPELINE |
primary->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_ALL; RADV_CMD_DIRTY_INDEX_BUFFER |
RADV_CMD_DIRTY_DYNAMIC_ALL;
radv_mark_descriptor_sets_dirty(primary); radv_mark_descriptor_sets_dirty(primary);
} }
@ -2926,14 +2951,6 @@ void radv_CmdDrawIndexed(
MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 26 * MAX_VIEWS); MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 26 * MAX_VIEWS);
if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
radeon_set_uconfig_reg_idx(cmd_buffer->cs, R_03090C_VGT_INDEX_TYPE,
2, cmd_buffer->state.index_type);
} else {
radeon_emit(cmd_buffer->cs, PKT3(PKT3_INDEX_TYPE, 0, 0));
radeon_emit(cmd_buffer->cs, cmd_buffer->state.index_type);
}
assert(cmd_buffer->state.pipeline->graphics.vtx_base_sgpr); assert(cmd_buffer->state.pipeline->graphics.vtx_base_sgpr);
radeon_set_sh_reg_seq(cmd_buffer->cs, cmd_buffer->state.pipeline->graphics.vtx_base_sgpr, radeon_set_sh_reg_seq(cmd_buffer->cs, cmd_buffer->state.pipeline->graphics.vtx_base_sgpr,
cmd_buffer->state.pipeline->graphics.vtx_emit_num); cmd_buffer->state.pipeline->graphics.vtx_emit_num);
@ -3081,29 +3098,11 @@ radv_cmd_draw_indexed_indirect_count(
uint32_t stride) uint32_t stride)
{ {
RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer); RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
uint64_t index_va;
radv_cmd_buffer_flush_state(cmd_buffer, true, false, true, 0); radv_cmd_buffer_flush_state(cmd_buffer, true, false, true, 0);
index_va = cmd_buffer->state.index_va;
MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 31 * MAX_VIEWS); MAYBE_UNUSED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 31 * MAX_VIEWS);
if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {
radeon_set_uconfig_reg_idx(cmd_buffer->cs,
R_03090C_VGT_INDEX_TYPE,
2, cmd_buffer->state.index_type);
} else {
radeon_emit(cmd_buffer->cs, PKT3(PKT3_INDEX_TYPE, 0, 0));
radeon_emit(cmd_buffer->cs, cmd_buffer->state.index_type);
}
radeon_emit(cmd_buffer->cs, PKT3(PKT3_INDEX_BASE, 1, 0));
radeon_emit(cmd_buffer->cs, index_va);
radeon_emit(cmd_buffer->cs, index_va >> 32);
radeon_emit(cmd_buffer->cs, PKT3(PKT3_INDEX_BUFFER_SIZE, 0, 0));
radeon_emit(cmd_buffer->cs, cmd_buffer->state.max_index_count);
radv_emit_indirect_draw(cmd_buffer, buffer, offset, radv_emit_indirect_draw(cmd_buffer, buffer, offset,
countBuffer, countBufferOffset, maxDrawCount, stride, true); countBuffer, countBufferOffset, maxDrawCount, stride, true);