diff --git a/src/amd/common/ac_descriptors.h b/src/amd/common/ac_descriptors.h index d5431f7bcfa..50ff47c156c 100644 --- a/src/amd/common/ac_descriptors.h +++ b/src/amd/common/ac_descriptors.h @@ -67,7 +67,7 @@ ac_build_fmask_descriptor(const enum amd_gfx_level gfx_level, uint32_t desc[8]); struct ac_texture_state { - struct radeon_surf *surf; + const struct radeon_surf *surf; enum pipe_format format; enum pipe_format img_format; uint32_t width : 17; @@ -305,7 +305,7 @@ ac_set_mutable_cb_surface_fields(const struct radeon_info *info, const struct ac struct ac_cb_surface *cb); struct ac_gfx12_hiz_state { - struct radeon_surf *surf; + const struct radeon_surf *surf; uint64_t va; uint32_t type : 4; uint32_t num_samples : 5; diff --git a/src/amd/common/ac_surface.c b/src/amd/common/ac_surface.c index 8da1f58fa84..e3f2e0808e0 100644 --- a/src/amd/common/ac_surface.c +++ b/src/amd/common/ac_surface.c @@ -3965,7 +3965,7 @@ void ac_surface_apply_bo_metadata(enum amd_gfx_level gfx_level, struct radeon_su surf->flags &= ~RADEON_SURF_SCANOUT; } -void ac_surface_compute_bo_metadata(const struct radeon_info *info, struct radeon_surf *surf, +void ac_surface_compute_bo_metadata(const struct radeon_info *info, const struct radeon_surf *surf, uint64_t *tiling_flags) { *tiling_flags = 0; @@ -4123,7 +4123,7 @@ bool ac_surface_apply_umd_metadata(const struct radeon_info *info, struct radeon return true; } -void ac_surface_compute_umd_metadata(const struct radeon_info *info, struct radeon_surf *surf, +void ac_surface_compute_umd_metadata(const struct radeon_info *info, const struct radeon_surf *surf, unsigned num_mipmap_levels, uint32_t desc[8], unsigned *size_metadata, uint32_t metadata[64], bool include_tool_md) diff --git a/src/amd/common/ac_surface.h b/src/amd/common/ac_surface.h index 0900c3db10b..001c259da98 100644 --- a/src/amd/common/ac_surface.h +++ b/src/amd/common/ac_surface.h @@ -451,13 +451,13 @@ unsigned ac_pipe_config_to_num_pipes(unsigned pipe_config); #define AC_SURF_METADATA_FLAG_FAMILY_OVERRIDEN_BIT 1 void ac_surface_apply_bo_metadata(enum amd_gfx_level gfx_level, struct radeon_surf *surf, uint64_t tiling_flags, enum radeon_surf_mode *mode); -void ac_surface_compute_bo_metadata(const struct radeon_info *info, struct radeon_surf *surf, +void ac_surface_compute_bo_metadata(const struct radeon_info *info, const struct radeon_surf *surf, uint64_t *tiling_flags); bool ac_surface_apply_umd_metadata(const struct radeon_info *info, struct radeon_surf *surf, unsigned num_storage_samples, unsigned num_mipmap_levels, unsigned size_metadata, const uint32_t metadata[64]); -void ac_surface_compute_umd_metadata(const struct radeon_info *info, struct radeon_surf *surf, +void ac_surface_compute_umd_metadata(const struct radeon_info *info, const struct radeon_surf *surf, unsigned num_mipmap_levels, uint32_t desc[8], unsigned *size_metadata, uint32_t metadata[64], bool include_tool_md); diff --git a/src/amd/common/nir/ac_nir_meta.h b/src/amd/common/nir/ac_nir_meta.h index 0b1aa55d56c..94a528f38e3 100644 --- a/src/amd/common/nir/ac_nir_meta.h +++ b/src/amd/common/nir/ac_nir_meta.h @@ -98,7 +98,7 @@ struct ac_cs_blit_options { struct ac_cs_blit_description { struct { - struct radeon_surf *surf; + const struct radeon_surf *surf; uint8_t dim; /* 1 = 1D texture, 2 = 2D texture, 3 = 3D texture */ bool is_array; /* array or cube texture */ unsigned width0; /* level 0 width */ diff --git a/src/amd/vulkan/nir/radv_meta_nir.c b/src/amd/vulkan/nir/radv_meta_nir.c index 44392373b38..a5b4455179d 100644 --- a/src/amd/vulkan/nir/radv_meta_nir.c +++ b/src/amd/vulkan/nir/radv_meta_nir.c @@ -942,7 +942,7 @@ radv_meta_nir_build_clear_dcc_comp_to_single_shader(struct radv_device *dev, boo } nir_shader * -radv_meta_nir_build_copy_vrs_htile_shader(struct radv_device *device, struct radeon_surf *surf) +radv_meta_nir_build_copy_vrs_htile_shader(struct radv_device *device, const struct radeon_surf *surf) { const struct radv_physical_device *pdev = radv_device_physical(device); nir_builder b = radv_meta_nir_init_shader(device, MESA_SHADER_COMPUTE, "meta_copy_vrs_htile"); @@ -1024,7 +1024,7 @@ radv_meta_nir_build_copy_vrs_htile_shader(struct radv_device *device, struct rad } nir_shader * -radv_meta_nir_build_dcc_retile_compute_shader(struct radv_device *dev, struct radeon_surf *surf) +radv_meta_nir_build_dcc_retile_compute_shader(struct radv_device *dev, const struct radeon_surf *surf) { const struct radv_physical_device *pdev = radv_device_physical(dev); enum glsl_sampler_dim dim = GLSL_SAMPLER_DIM_BUF; diff --git a/src/amd/vulkan/nir/radv_meta_nir.h b/src/amd/vulkan/nir/radv_meta_nir.h index b193eee18e1..16e9137ccc8 100644 --- a/src/amd/vulkan/nir/radv_meta_nir.h +++ b/src/amd/vulkan/nir/radv_meta_nir.h @@ -72,9 +72,9 @@ void radv_meta_nir_build_clear_depthstencil_shaders(struct radv_device *dev, str nir_shader *radv_meta_nir_build_clear_htile_mask_shader(struct radv_device *dev); nir_shader *radv_meta_nir_build_clear_dcc_comp_to_single_shader(struct radv_device *dev, bool is_msaa); -nir_shader *radv_meta_nir_build_copy_vrs_htile_shader(struct radv_device *device, struct radeon_surf *surf); +nir_shader *radv_meta_nir_build_copy_vrs_htile_shader(struct radv_device *device, const struct radeon_surf *surf); -nir_shader *radv_meta_nir_build_dcc_retile_compute_shader(struct radv_device *dev, struct radeon_surf *surf); +nir_shader *radv_meta_nir_build_dcc_retile_compute_shader(struct radv_device *dev, const struct radeon_surf *surf); nir_shader *radv_meta_nir_build_expand_depth_stencil_compute_shader(struct radv_device *dev); diff --git a/src/amd/vulkan/radv_image.c b/src/amd/vulkan/radv_image.c index 1380df1c87b..377b30a43fd 100644 --- a/src/amd/vulkan/radv_image.c +++ b/src/amd/vulkan/radv_image.c @@ -792,7 +792,7 @@ radv_image_bo_set_metadata(struct radv_device *device, struct radv_image *image, const VkFormat plane_format = radv_image_get_plane_format(pdev, image, plane_id); const unsigned plane_width = vk_format_get_plane_width(image->vk.format, plane_id, image->vk.extent.width); const unsigned plane_height = vk_format_get_plane_height(image->vk.format, plane_id, image->vk.extent.height); - struct radeon_surf *surface = &image->planes[plane_id].surface; + const struct radeon_surf *surface = &image->planes[plane_id].surface; const struct legacy_surf_level *base_level_info = pdev->info.gfx_level <= GFX8 ? &surface->u.legacy.level[0] : NULL; struct radeon_bo_metadata md; uint32_t desc[8]; @@ -1895,7 +1895,7 @@ radv_GetImageSubresourceLayout2(VkDevice _device, VkImage _image, const VkImageS plane_id = radv_plane_from_aspect(pSubresource->imageSubresource.aspectMask); struct radv_image_plane *plane = &image->planes[plane_id]; - struct radeon_surf *surface = &plane->surface; + const struct radeon_surf *surface = &plane->surface; if (image->vk.tiling == VK_IMAGE_TILING_DRM_FORMAT_MODIFIER_EXT && plane_count == 1) { unsigned mem_plane_id = radv_plane_from_aspect(pSubresource->imageSubresource.aspectMask); diff --git a/src/amd/vulkan/radv_queue.c b/src/amd/vulkan/radv_queue.c index f9f92b2b1e1..6343a219304 100644 --- a/src/amd/vulkan/radv_queue.c +++ b/src/amd/vulkan/radv_queue.c @@ -108,7 +108,7 @@ radv_sparse_image_bind_memory(struct radv_device *device, const VkSparseImageMem { VK_FROM_HANDLE(radv_image, image, bind->image); const struct radv_physical_device *pdev = radv_device_physical(device); - struct radeon_surf *surface = &image->planes[0].surface; + const struct radeon_surf *surface = &image->planes[0].surface; uint32_t bs = vk_format_get_blocksize(image->vk.format); VkResult result; diff --git a/src/amd/vulkan/radv_video.c b/src/amd/vulkan/radv_video.c index 4afb622d19e..5db7c0c7691 100644 --- a/src/amd/vulkan/radv_video.c +++ b/src/amd/vulkan/radv_video.c @@ -3025,7 +3025,7 @@ get_uvd_h265_msg(struct radv_device *device, struct radv_video_session *vid, str } static unsigned -texture_offset_legacy(struct radeon_surf *surface, unsigned layer) +texture_offset_legacy(const struct radeon_surf *surface, unsigned layer) { return (uint64_t)surface->u.legacy.level[0].offset_256B * 256 + layer * (uint64_t)surface->u.legacy.level[0].slice_size_dw * 4; diff --git a/src/gallium/drivers/radeonsi/radeon_uvd.c b/src/gallium/drivers/radeonsi/radeon_uvd.c index 11e43c20d25..83d984df252 100644 --- a/src/gallium/drivers/radeonsi/radeon_uvd.c +++ b/src/gallium/drivers/radeonsi/radeon_uvd.c @@ -1363,7 +1363,7 @@ error: } /* calculate top/bottom offset */ -static unsigned texture_offset(struct radeon_surf *surface, unsigned layer, +static unsigned texture_offset(const struct radeon_surf *surface, unsigned layer, enum ruvd_surface_type type) { switch (type) { @@ -1371,10 +1371,8 @@ static unsigned texture_offset(struct radeon_surf *surface, unsigned layer, case RUVD_SURFACE_TYPE_LEGACY: return (uint64_t)surface->u.legacy.level[0].offset_256B * 256 + layer * (uint64_t)surface->u.legacy.level[0].slice_size_dw * 4; - break; case RUVD_SURFACE_TYPE_GFX9: return surface->u.gfx9.surf_offset + layer * surface->u.gfx9.surf_slice_size; - break; } } @@ -1423,8 +1421,8 @@ static unsigned bank_wh(unsigned bankwh) /** * fill decoding target field from the luma and chroma surfaces */ -void si_uvd_set_dt_surfaces(struct ruvd_msg *msg, struct radeon_surf *luma, - struct radeon_surf *chroma, enum ruvd_surface_type type) +void si_uvd_set_dt_surfaces(struct ruvd_msg *msg, const struct radeon_surf *luma, + const struct radeon_surf *chroma, enum ruvd_surface_type type) { switch (type) { default: diff --git a/src/gallium/drivers/radeonsi/radeon_uvd.h b/src/gallium/drivers/radeonsi/radeon_uvd.h index d535314d822..a0527cc9310 100644 --- a/src/gallium/drivers/radeonsi/radeon_uvd.h +++ b/src/gallium/drivers/radeonsi/radeon_uvd.h @@ -23,6 +23,6 @@ struct pipe_video_codec *si_common_uvd_create_decoder(struct pipe_context *conte ruvd_set_dtb set_dtb); /* fill decoding target field from the luma and chroma surfaces */ -void si_uvd_set_dt_surfaces(struct ruvd_msg *msg, struct radeon_surf *luma, - struct radeon_surf *chroma, enum ruvd_surface_type type); +void si_uvd_set_dt_surfaces(struct ruvd_msg *msg, const struct radeon_surf *luma, + const struct radeon_surf *chroma, enum ruvd_surface_type type); #endif diff --git a/src/gallium/drivers/radeonsi/si_pipe.h b/src/gallium/drivers/radeonsi/si_pipe.h index 707f053f872..c3aab10c457 100644 --- a/src/gallium/drivers/radeonsi/si_pipe.h +++ b/src/gallium/drivers/radeonsi/si_pipe.h @@ -1653,7 +1653,7 @@ void si_resume_queries(struct si_context *sctx); /* si_shaderlib_nir.c */ void *si_create_shader_state(struct si_context *sctx, struct nir_shader *nir); -void *si_create_dcc_retile_cs(struct si_context *sctx, struct radeon_surf *surf); +void *si_create_dcc_retile_cs(struct si_context *sctx, const struct radeon_surf *surf); void *gfx9_create_clear_dcc_msaa_cs(struct si_context *sctx, struct si_texture *tex); void *si_create_passthrough_tcs(struct si_context *sctx); void *si_clear_image_dcc_single_shader(struct si_context *sctx, bool is_msaa, unsigned wg_dim); diff --git a/src/gallium/drivers/radeonsi/si_shaderlib_nir.c b/src/gallium/drivers/radeonsi/si_shaderlib_nir.c index fdaeab6463c..2335837fc62 100644 --- a/src/gallium/drivers/radeonsi/si_shaderlib_nir.c +++ b/src/gallium/drivers/radeonsi/si_shaderlib_nir.c @@ -38,7 +38,7 @@ static void unpack_2x16(nir_builder *b, nir_def *src, nir_def **x, nir_def **y) *y = nir_ushr_imm(b, src, 16); } -void *si_create_dcc_retile_cs(struct si_context *sctx, struct radeon_surf *surf) +void *si_create_dcc_retile_cs(struct si_context *sctx, const struct radeon_surf *surf) { nir_builder b = nir_builder_init_simple_shader(MESA_SHADER_COMPUTE, sctx->screen->nir_options, "dcc_retile"); diff --git a/src/gallium/drivers/radeonsi/si_texture.c b/src/gallium/drivers/radeonsi/si_texture.c index b1a714f5625..c7c0a29a836 100644 --- a/src/gallium/drivers/radeonsi/si_texture.c +++ b/src/gallium/drivers/radeonsi/si_texture.c @@ -1540,7 +1540,7 @@ bool si_texture_commit(struct si_context *ctx, struct si_resource *res, unsigned struct pipe_box *box, bool commit) { struct si_texture *tex = (struct si_texture *)res; - struct radeon_surf *surface = &tex->surface; + const struct radeon_surf *surface = &tex->surface; enum pipe_format format = res->b.b.format; unsigned blks = util_format_get_blocksize(format); unsigned samples = MAX2(1, res->b.b.nr_samples); diff --git a/src/gallium/include/winsys/radeon_winsys.h b/src/gallium/include/winsys/radeon_winsys.h index 2ec0b544b69..da6f9cd6aa7 100644 --- a/src/gallium/include/winsys/radeon_winsys.h +++ b/src/gallium/include/winsys/radeon_winsys.h @@ -398,7 +398,7 @@ struct radeon_winsys { * \param md Metadata */ void (*buffer_set_metadata)(struct radeon_winsys *ws, struct pb_buffer_lean *buf, - struct radeon_bo_metadata *md, struct radeon_surf *surf); + struct radeon_bo_metadata *md, const struct radeon_surf *surf); /** * Get a winsys buffer from a winsys handle. The internal structure diff --git a/src/gallium/winsys/amdgpu/drm/amdgpu_bo.c b/src/gallium/winsys/amdgpu/drm/amdgpu_bo.c index ce4e9f67659..2da06e838b9 100644 --- a/src/gallium/winsys/amdgpu/drm/amdgpu_bo.c +++ b/src/gallium/winsys/amdgpu/drm/amdgpu_bo.c @@ -1441,7 +1441,7 @@ static void amdgpu_buffer_get_metadata(struct radeon_winsys *rws, static void amdgpu_buffer_set_metadata(struct radeon_winsys *rws, struct pb_buffer_lean *_buf, struct radeon_bo_metadata *md, - struct radeon_surf *surf) + const struct radeon_surf *surf) { struct amdgpu_winsys *aws = amdgpu_winsys(rws); struct amdgpu_winsys_bo *bo = amdgpu_winsys_bo(_buf); diff --git a/src/gallium/winsys/radeon/drm/radeon_drm_bo.c b/src/gallium/winsys/radeon/drm/radeon_drm_bo.c index 8bfe69adbb0..50a08c8fa3d 100644 --- a/src/gallium/winsys/radeon/drm/radeon_drm_bo.c +++ b/src/gallium/winsys/radeon/drm/radeon_drm_bo.c @@ -901,7 +901,7 @@ static void radeon_bo_get_metadata(struct radeon_winsys *rws, static void radeon_bo_set_metadata(struct radeon_winsys *rws, struct pb_buffer_lean *_buf, struct radeon_bo_metadata *md, - struct radeon_surf *surf) + const struct radeon_surf *surf) { struct radeon_bo *bo = radeon_bo(_buf); struct drm_radeon_gem_set_tiling args; diff --git a/src/gallium/winsys/radeon/drm/radeon_drm_surface.c b/src/gallium/winsys/radeon/drm/radeon_drm_surface.c index cc5ebca45e5..1421cc386e5 100644 --- a/src/gallium/winsys/radeon/drm/radeon_drm_surface.c +++ b/src/gallium/winsys/radeon/drm/radeon_drm_surface.c @@ -8,7 +8,7 @@ #include "util/format/u_format.h" #include -static unsigned cik_get_macro_tile_index(struct radeon_surf *surf) +static unsigned cik_get_macro_tile_index(const struct radeon_surf *surf) { unsigned index, tileb;