From 965072437098090100c8b149cacf8e5196875b43 Mon Sep 17 00:00:00 2001
From: Georg Lehmann <dadschoorse@gmail.com>
Date: Tue, 21 Mar 2023 13:26:19 +0100
Subject: [PATCH] aco/gfx11: allow opsel for VOP12C

Foz-DB GFX1100:
Totals from 515 (0.38% of 134864) affected shaders:
CodeSize: 2768228 -> 2761076 (-0.26%)
Instrs: 520301 -> 518523 (-0.34%)
Latency: 5190860 -> 5187254 (-0.07%)
InvThroughput: 2120844 -> 2119447 (-0.07%)
Copies: 57238 -> 56101 (-1.99%)

Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22069>
---
 src/amd/compiler/aco_ir.cpp | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/src/amd/compiler/aco_ir.cpp b/src/amd/compiler/aco_ir.cpp
index e746c666f78..f592cb6e65d 100644
--- a/src/amd/compiler/aco_ir.cpp
+++ b/src/amd/compiler/aco_ir.cpp
@@ -471,7 +471,8 @@ can_use_opsel(amd_gfx_level gfx_level, aco_opcode op, int idx)
    case aco_opcode::v_interp_p10_rtz_f16_f32_inreg: return idx == 0 || idx == 2;
    case aco_opcode::v_interp_p2_f16_f32_inreg:
    case aco_opcode::v_interp_p2_rtz_f16_f32_inreg: return idx == -1 || idx == 0;
-   default: return false;
+   default:
+      return gfx_level >= GFX11 && (get_gfx11_true16_mask(op) & BITFIELD_BIT(idx == -1 ? 3 : idx));
    }
 }
 
@@ -537,7 +538,6 @@ instr_is_16bit(amd_gfx_level gfx_level, aco_opcode op)
 /* On GFX11, for some instructions, bit 7 of the destination/operand vgpr is opsel and the field
  * only supports v0-v127.
  */
-// TODO: take advantage of this functionality in the RA and assembler
 uint8_t
 get_gfx11_true16_mask(aco_opcode op)
 {