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asahi: refactor prolog lowering

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combine 2 passes and get something less silly as the result.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30382>
This commit is contained in:
Alyssa Rosenzweig 2024-07-17 13:55:22 -04:00 • committed by Marge Bot
parent 0bd897989e
commit 96306a8b21
4 changed files with 19 additions and 42 deletions
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25
src/asahi/lib/agx_nir_lower_gs.c
View file

@ -339,31 +339,6 @@ lower_gs_count_instr(nir_builder *b, nir_intrinsic_instr *intr, void *data)
}
}
static bool
lower_prolog_id(nir_builder *b, nir_intrinsic_instr *intr, void *data)
{
b->cursor = nir_before_instr(&intr->instr);
nir_def *id;
if (intr->intrinsic == nir_intrinsic_load_primitive_id)
id = load_primitive_id(b);
else if (intr->intrinsic == nir_intrinsic_load_instance_id)
id = load_instance_id(b);
else
return false;
b->cursor = nir_instr_remove(&intr->instr);
nir_def_rewrite_uses(&intr->def, id);
return true;
}
bool
agx_nir_lower_sw_vs_id(nir_shader *s)
{
return nir_shader_intrinsics_pass(s, lower_prolog_id,
nir_metadata_control_flow, NULL);
}
static bool
lower_id(nir_builder *b, nir_intrinsic_instr *intr, void *data)
{

4
src/asahi/lib/agx_nir_lower_gs.h
View file

@ -24,9 +24,7 @@ struct nir_def *agx_load_per_vertex_input(struct nir_builder *b,
nir_intrinsic_instr *intr,
struct nir_def *vertex);
bool agx_nir_lower_index_buffer(struct nir_shader *s, unsigned index_size_B);
bool agx_nir_lower_sw_vs_id(nir_shader *s);
bool agx_nir_lower_sw_vs(struct nir_shader *s, unsigned index_size_B);
bool agx_nir_lower_vs_before_gs(struct nir_shader *vs,
const struct nir_shader *libagx,

29
src/asahi/lib/agx_nir_lower_ia.c
View file

@ -22,7 +22,7 @@
static nir_def *
load_vertex_id(nir_builder *b, unsigned index_size_B)
{
nir_def *id = nir_load_primitive_id(b);
nir_def *id = nir_channel(b, nir_load_global_invocation_id(b, 32), 0);
/* If drawing with an index buffer, pull the vertex ID. Otherwise, the
* vertex ID is just the index as-is.
@ -43,21 +43,26 @@ load_vertex_id(nir_builder *b, unsigned index_size_B)
}
static bool
lower_vertex_id(nir_builder *b, nir_intrinsic_instr *intr, void *data)
lower(nir_builder *b, nir_intrinsic_instr *intr, void *data)
{
if (intr->intrinsic != nir_intrinsic_load_vertex_id)
return false;
unsigned *index_size_B = data;
b->cursor = nir_instr_remove(&intr->instr);
assert(intr->def.bit_size == 32);
nir_def_rewrite_uses(&intr->def, load_vertex_id(b, *index_size_B));
return true;
b->cursor = nir_before_instr(&intr->instr);
if (intr->intrinsic == nir_intrinsic_load_vertex_id) {
nir_def_replace(&intr->def, load_vertex_id(b, *index_size_B));
return true;
} else if (intr->intrinsic == nir_intrinsic_load_instance_id) {
nir_def_replace(&intr->def,
nir_channel(b, nir_load_global_invocation_id(b, 32), 1));
return true;
}
return false;
}
bool
agx_nir_lower_index_buffer(nir_shader *s, unsigned index_size_B)
agx_nir_lower_sw_vs(nir_shader *s, unsigned index_size_B)
{
return nir_shader_intrinsics_pass(s, lower_vertex_id,
nir_metadata_control_flow, &index_size_B);
return nir_shader_intrinsics_pass(s, lower, nir_metadata_control_flow,
&index_size_B);
}

3
src/asahi/lib/agx_nir_prolog_epilog.c
View file

@ -169,8 +169,7 @@ agx_nir_vs_prolog(nir_builder *b, const void *key_)
lower_vbo(b->shader, key->attribs, key->robustness);
if (!key->hw) {
agx_nir_lower_index_buffer(b->shader, key->sw_index_size_B);
agx_nir_lower_sw_vs_id(b->shader);
agx_nir_lower_sw_vs(b->shader, key->sw_index_size_B);
}
/* Finally, lower uniforms according to our ABI */