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radv: remove useless radv_blend_state::single_cb_enable field

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This was only used for meta operations. DCC/FMASK/FCE pipelines
only declare one color attachment and the color writemask of the
second color attachment is 0 for the HW CB resolve.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14650>
This commit is contained in:
Samuel Pitoiset 2021-10-28 14:50:10 +02:00 • committed by Marge Bot
parent 8347d3dfd7
commit 959e8586aa
1 changed files with 1 additions and 4 deletions
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5
src/amd/vulkan/radv_pipeline.c
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@ -64,7 +64,6 @@ struct radv_blend_state {
uint32_t commutative_4bit;
bool single_cb_enable;
bool mrt0_is_dual_src;
};
@ -541,8 +540,7 @@ radv_pipeline_compute_spi_color_formats(const struct radv_pipeline *pipeline,
unsigned num_targets;
if (render_create_info) {
for (unsigned i = 0;
i < (blend->single_cb_enable ? 1 : render_create_info->colorAttachmentCount); ++i) {
for (unsigned i = 0; i < render_create_info->colorAttachmentCount; ++i) {
unsigned cf;
VkFormat fmt = render_create_info->pColorAttachmentFormats[i];
@ -682,7 +680,6 @@ radv_pipeline_init_blend_state(struct radv_pipeline *pipeline,
int i;
if (extra && extra->custom_blend_mode) {
blend.single_cb_enable = true;
mode = extra->custom_blend_mode;
}