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i965/hsw+: Add support for copying a register

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Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
This commit is contained in:
Jordan Justen 2016-04-19 09:34:40 -07:00
parent aad14a22cb
commit 959e1e9e66
3 changed files with 18 additions and 0 deletions
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2
src/mesa/drivers/dri/i965/brw_context.h
View file

@ -1452,6 +1452,8 @@ void brw_store_register_mem32(struct brw_context *brw,
drm_intel_bo *bo, uint32_t reg, uint32_t offset);
void brw_store_register_mem64(struct brw_context *brw,
drm_intel_bo *bo, uint32_t reg, uint32_t offset);
void brw_load_register_reg(struct brw_context *brw, uint32_t src,
uint32_t dest);
void brw_store_data_imm32(struct brw_context *brw, drm_intel_bo *bo,
uint32_t offset, uint32_t imm);
void brw_store_data_imm64(struct brw_context *brw, drm_intel_bo *bo,

15
src/mesa/drivers/dri/i965/intel_batchbuffer.c
View file

@ -601,6 +601,21 @@ brw_store_register_mem64(struct brw_context *brw,
}
}
/*
* Copies a 32-bit register.
*/
void
brw_load_register_reg(struct brw_context *brw, uint32_t src, uint32_t dest)
{
assert(brw->gen >= 8 || brw->is_haswell);
BEGIN_BATCH(3);
OUT_BATCH(MI_LOAD_REGISTER_REG | (3 - 2));
OUT_BATCH(src);
OUT_BATCH(dest);
ADVANCE_BATCH();
}
/*
* Write 32-bits of immediate data to a GPU memory buffer.
*/

1
src/mesa/drivers/dri/i965/intel_reg.h
View file

@ -37,6 +37,7 @@
#define MI_STORE_DATA_IMM (CMD_MI | (0x20 << 23))
#define MI_LOAD_REGISTER_IMM (CMD_MI | (0x22 << 23))
#define MI_LOAD_REGISTER_REG (CMD_MI | (0x2A << 23))
#define MI_FLUSH_DW (CMD_MI | (0x26 << 23) | 2)