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intel/isl: Drop unnecessary check on 16bpp depth format

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Drop unnecessary check which allows enabling of lossless write through
compression (HiZ + CCS) for D16_UNORM format on Gen12+.

We had misleading HSD information previously which used to claim that
compression can not be supported for 16bpp format. Although BSpec does
not have any restriction for D16_UNORM format.

Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Acked-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6485>
This commit is contained in:
Sagar Ghuge 2020-08-26 22:24:19 -07:00 • committed by Marge Bot
parent 829699ba63
commit 959539fbbd
1 changed files with 0 additions and 14 deletions
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14
src/intel/isl/isl.c
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@ -1972,20 +1972,6 @@ isl_surf_supports_ccs(const struct isl_device *dev,
if (isl_surf_usage_is_stencil(surf->usage) && surf->samples > 1)
return false;
/* [TGL+] CCS can only be added to a non-D16-formatted depth buffer if
* it has HiZ. If not for GEN:BUG:1406512483 "deprecate compression
* enable states", D16 would be supported. Supporting D16 requires being
* able to specify that the control surface is present and
* simultaneously disabling compression. The above bug makes it so that
* it's not possible to specify this configuration.
*
* Note: ISL Doesn't currently support depth CCS without HiZ at all.
*/
if (isl_surf_usage_is_depth(surf->usage) &&
surf->format == ISL_FORMAT_R16_UNORM) {
return false;
}
/* On Gen12, 8BPP surfaces cannot be compressed if any level is not
* 32Bx4row-aligned. For now, just reject the cases where alignment
* matters.