diff --git a/src/intel/compiler/brw_compiler.c b/src/intel/compiler/brw_compiler.c
index d663ecfc3dd..116bb0f8b5d 100644
--- a/src/intel/compiler/brw_compiler.c
+++ b/src/intel/compiler/brw_compiler.c
@@ -367,31 +367,6 @@ brw_write_shader_relocs(const struct brw_isa_info *isa,
    }
 }
 
-void
-brw_stage_prog_data_add_printf(struct brw_stage_prog_data *prog_data,
-                               void *mem_ctx,
-                               const u_printf_info *print)
-{
-   prog_data->printf_info_count++;
-   prog_data->printf_info = reralloc(mem_ctx, prog_data->printf_info,
-                                     u_printf_info,
-                                     prog_data->printf_info_count);
-
-   prog_data->printf_info[prog_data->printf_info_count - 1] = *print;
-   if (print->string_size > 0) {
-      prog_data->printf_info[prog_data->printf_info_count - 1].strings =
-         ralloc_size(mem_ctx, print->string_size);
-      memcpy(prog_data->printf_info[prog_data->printf_info_count - 1].strings,
-             print->strings, print->string_size);
-   }
-   if (print->num_args > 0) {
-      prog_data->printf_info[prog_data->printf_info_count - 1].arg_sizes =
-         ralloc_array(mem_ctx, __typeof__(*print->arg_sizes), print->num_args);
-      memcpy(prog_data->printf_info[prog_data->printf_info_count - 1].arg_sizes,
-             print->arg_sizes, sizeof(print->arg_sizes[0]) *print->num_args);
-   }
-}
-
 unsigned
 ptl_register_blocks(unsigned grf_used)
 {
diff --git a/src/intel/compiler/brw_compiler.h b/src/intel/compiler/brw_compiler.h
index bcac8075250..5227360785e 100644
--- a/src/intel/compiler/brw_compiler.h
+++ b/src/intel/compiler/brw_compiler.h
@@ -32,7 +32,6 @@
 #include "util/enum_operators.h"
 #include "util/ralloc.h"
 #include "util/u_math.h"
-#include "util/u_printf.h"
 #include "brw_isa_info.h"
 #include "intel_shader_enums.h"
 #include "nir_shader_compiler_options.h"
@@ -684,10 +683,6 @@ struct brw_stage_prog_data {
 
    /* Whether shader uses atomic operations. */
    bool uses_atomic_load_store;
-
-   /* Printf descriptions contained by the shader */
-   uint32_t printf_info_count;
-   u_printf_info *printf_info;
 };
 
 /**
@@ -696,11 +691,6 @@ struct brw_stage_prog_data {
  */
 unsigned ptl_register_blocks(unsigned grf_used);
 
-void
-brw_stage_prog_data_add_printf(struct brw_stage_prog_data *prog_data,
-                               void *mem_ctx,
-                               const u_printf_info *print);
-
 enum brw_pixel_shader_computed_depth_mode {
    BRW_PSCDEPTH_OFF   = 0, /* PS does not compute depth */
    BRW_PSCDEPTH_ON    = 1, /* PS computes depth; no guarantee about value */
diff --git a/src/intel/compiler/brw_from_nir.cpp b/src/intel/compiler/brw_from_nir.cpp
index c260e61ac99..9a4bfe87c2f 100644
--- a/src/intel/compiler/brw_from_nir.cpp
+++ b/src/intel/compiler/brw_from_nir.cpp
@@ -8040,12 +8040,6 @@ brw_from_nir(brw_shader *s)
    if (ENABLE_TEST_DISPATCH_PACKING)
       brw_test_dispatch_packing(ntb.bld);
 
-   for (unsigned i = 0; i < s->nir->printf_info_count; i++) {
-      brw_stage_prog_data_add_printf(s->prog_data,
-                                     s->mem_ctx,
-                                     &s->nir->printf_info[i]);
-   }
-
    emit_shader_float_controls_execution_mode(ntb);
 
    /* emit the arrays used for inputs and outputs - load/store intrinsics will