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radeonsi: add support for Sienna Cichlid

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Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5383>
This commit is contained in:
Marek Olšák 2020-03-26 22:08:18 -04:00 • committed by Marge Bot
parent 789cdab3b6
commit 9538b9a68e
6 changed files with 19 additions and 2 deletions
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2
src/amd/addrlib/src/amdgpu_asic_addr.h
View file

@ -97,6 +97,7 @@
#define AMDGPU_NAVI10_RANGE 0x01, 0x0A #define AMDGPU_NAVI10_RANGE 0x01, 0x0A
#define AMDGPU_NAVI12_RANGE 0x0A, 0x14 #define AMDGPU_NAVI12_RANGE 0x0A, 0x14
#define AMDGPU_NAVI14_RANGE 0x14, 0x28 #define AMDGPU_NAVI14_RANGE 0x14, 0x28
#define AMDGPU_SIENNA_RANGE 0x28, 0x32
#define AMDGPU_EXPAND_FIX(x) x #define AMDGPU_EXPAND_FIX(x) x
#define AMDGPU_RANGE_HELPER(val, min, max) ((val >= min) && (val < max)) #define AMDGPU_RANGE_HELPER(val, min, max) ((val >= min) && (val < max))
@ -144,5 +145,6 @@
#define ASICREV_IS_NAVI10_P(r) ASICREV_IS(r, NAVI10) #define ASICREV_IS_NAVI10_P(r) ASICREV_IS(r, NAVI10)
#define ASICREV_IS_NAVI12(r) ASICREV_IS(r, NAVI12) #define ASICREV_IS_NAVI12(r) ASICREV_IS(r, NAVI12)
#define ASICREV_IS_NAVI14(r) ASICREV_IS(r, NAVI14) #define ASICREV_IS_NAVI14(r) ASICREV_IS(r, NAVI14)
#define ASICREV_IS_SIENNA_M(r) ASICREV_IS(r, SIENNA)
#endif // _AMDGPU_ASIC_ADDR_H #endif // _AMDGPU_ASIC_ADDR_H

6
src/amd/addrlib/src/gfx10/gfx10addrlib.cpp
View file

@ -943,6 +943,12 @@ ChipFamily Gfx10Lib::HwlConvertChipFamily(
{ {
case FAMILY_NV: case FAMILY_NV:
m_settings.isDcn2 = 1; m_settings.isDcn2 = 1;
if (ASICREV_IS_SIENNA_M(chipRevision))
{
m_settings.supportRbPlus = 1;
m_settings.dccUnsup3DSwDis = 0;
}
break; break;
default: default:
ADDR_ASSERT(!"Unknown chip family"); ADDR_ASSERT(!"Unknown chip family");

6
src/amd/common/ac_gpu_info.c
View file

@ -401,6 +401,7 @@ bool ac_query_gpu_info(int fd, void *dev_p,
identify_chip(NAVI10); identify_chip(NAVI10);
identify_chip(NAVI12); identify_chip(NAVI12);
identify_chip(NAVI14); identify_chip(NAVI14);
identify_chip(SIENNA);
break; break;
} }
@ -410,7 +411,9 @@ bool ac_query_gpu_info(int fd, void *dev_p,
return false; return false;
} }
if (info->family >= CHIP_NAVI10) if (info->family >= CHIP_SIENNA)
info->chip_class = GFX10_3;
else if (info->family >= CHIP_NAVI10)
info->chip_class = GFX10; info->chip_class = GFX10;
else if (info->family >= CHIP_VEGA10) else if (info->family >= CHIP_VEGA10)
info->chip_class = GFX9; info->chip_class = GFX9;
@ -712,6 +715,7 @@ bool ac_query_gpu_info(int fd, void *dev_p,
case CHIP_RENOIR: case CHIP_RENOIR:
case CHIP_NAVI10: case CHIP_NAVI10:
case CHIP_NAVI12: case CHIP_NAVI12:
case CHIP_SIENNA:
pc_lines = 1024; pc_lines = 1024;
break; break;
case CHIP_NAVI14: case CHIP_NAVI14:

1
src/amd/common/amd_family.h
View file

@ -102,6 +102,7 @@ enum radeon_family {
CHIP_NAVI10, CHIP_NAVI10,
CHIP_NAVI12, CHIP_NAVI12,
CHIP_NAVI14, CHIP_NAVI14,
CHIP_SIENNA,
CHIP_LAST, CHIP_LAST,
}; };

2
src/amd/llvm/ac_llvm_util.c
View file

@ -157,6 +157,8 @@ const char *ac_get_llvm_processor_name(enum radeon_family family)
return "gfx1011"; return "gfx1011";
case CHIP_NAVI14: case CHIP_NAVI14:
return "gfx1012"; return "gfx1012";
case CHIP_SIENNA:
return "gfx1030";
default: default:
return ""; return "";
} }

4
src/gallium/winsys/amdgpu/drm/amdgpu_winsys.c
View file

@ -63,7 +63,9 @@ static void handle_env_var_force_family(struct amdgpu_winsys *ws)
ws->info.family = i; ws->info.family = i;
ws->info.name = "GCN-NOOP"; ws->info.name = "GCN-NOOP";
if (i >= CHIP_NAVI10) if (i >= CHIP_SIENNA)
ws->info.chip_class = GFX10_3;
else if (i >= CHIP_NAVI10)
ws->info.chip_class = GFX10; ws->info.chip_class = GFX10;
else if (i >= CHIP_VEGA10) else if (i >= CHIP_VEGA10)
ws->info.chip_class = GFX9; ws->info.chip_class = GFX9;