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brw: Make indirect_ubos_use_sampler a static inline bool taking devinfo

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Having the named field allowed us to indicate that our code conditions
are referring to the specific decision about how we handle indirect
UBOs, rather than some other arbitrary hardware change.

Still, there's no need to store this in a singleton struct - we can
easily have a static inline bool that does the devinfo check for us.

Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/39839>
This commit is contained in:
Kenneth Graunke 2026-02-02 17:40:50 -08:00 • committed by Marge Bot
parent de03b38daa
commit 9531c6b89e
11 changed files with 24 additions and 29 deletions
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1
src/gallium/drivers/iris/iris_context.h
View file

@ -1368,7 +1368,6 @@ uint32_t
iris_fs_barycentric_modes(const struct iris_compiled_shader *shader,
enum intel_fs_config pushed_fs_config);
bool iris_use_tcs_multi_patch(struct iris_screen *screen);
bool iris_indirect_ubos_use_sampler(struct iris_screen *screen);
const struct nir_shader_compiler_options *
iris_get_compiler_options(struct pipe_screen *pscreen,
mesa_shader_stage pstage);

2
src/gallium/drivers/iris/iris_pipe_control.c
View file

@ -193,7 +193,7 @@ iris_emit_buffer_barrier_for(struct iris_batch *batch,
[IRIS_DOMAIN_VF_READ] = PIPE_CONTROL_VF_CACHE_INVALIDATE,
[IRIS_DOMAIN_SAMPLER_READ] = PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE,
[IRIS_DOMAIN_PULL_CONSTANT_READ] = PIPE_CONTROL_CONST_CACHE_INVALIDATE |
(iris_indirect_ubos_use_sampler(batch->screen) ?
(intel_indirect_ubos_use_sampler(devinfo) ?
PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE :
PIPE_CONTROL_DATA_CACHE_FLUSH),
};

9
src/gallium/drivers/iris/iris_program.c
View file

@ -690,7 +690,8 @@ iris_upload_ubo_ssbo_surf_state(struct iris_context *ice,
struct iris_bo *surf_bo = iris_resource_bo(surf_state->res);
surf_state->offset += iris_bo_offset_from_base_address(surf_bo);
const bool dataport = ssbo || !iris_indirect_ubos_use_sampler(screen);
const bool dataport =
ssbo || !intel_indirect_ubos_use_sampler(screen->devinfo);
isl_buffer_fill_state(&screen->isl_dev, map,
.address = res->bo->address + res->offset +
@ -4048,12 +4049,6 @@ iris_use_tcs_multi_patch(struct iris_screen *screen)
return screen->brw && screen->brw->use_tcs_multi_patch;
}
bool
iris_indirect_ubos_use_sampler(struct iris_screen *screen)
{
return screen->brw && screen->brw->indirect_ubos_use_sampler;
}
static void
iris_shader_debug_log(void *data, unsigned *id, const char *fmt, ...)
{

2
src/gallium/drivers/iris/iris_state.c
View file

@ -9862,7 +9862,7 @@ batch_mark_sync_for_pipe_control(struct iris_batch *batch, uint32_t flags)
/* Technically, to invalidate IRIS_DOMAIN_PULL_CONSTANT_READ, we need
* both "Constant Cache Invalidate" and either "Texture Cache Invalidate"
* or "Data Cache Flush" set, depending on the setting of
* iris_indirect_ubos_use_sampler().
* intel_indirect_ubos_use_sampler().
*
* However, "Data Cache Flush" and "Constant Cache Invalidate" will never
* appear in the same PIPE_CONTROL command, because one is bottom-of-pipe

2
src/intel/compiler/brw/brw_compiler.c
View file

@ -94,8 +94,6 @@ brw_compiler_create(void *mem_ctx, const struct intel_device_info *devinfo)
compiler->extended_bindless_surface_offset = devinfo->verx10 >= 125;
compiler->use_tcs_multi_patch = devinfo->ver >= 12;
compiler->indirect_ubos_use_sampler = devinfo->ver < 12;
compiler->lower_dpas = !devinfo->has_systolic ||
debug_get_bool_option("INTEL_LOWER_DPAS", false);

8
src/intel/compiler/brw/brw_compiler.h
View file

@ -74,14 +74,6 @@ struct brw_compiler {
*/
bool precise_trig;
/**
* Whether indirect UBO loads should use the sampler or go through the
* data/constant cache. For the sampler, UBO surface states have to be set
* up with VK_FORMAT_R32G32B32A32_FLOAT whereas if it's going through the
* constant or data cache, UBOs must use VK_FORMAT_RAW.
*/
bool indirect_ubos_use_sampler;
/**
* Gfx12.5+ has a bit in the SEND instruction extending the bindless
* surface offset range from 20 to 26 bits, effectively giving us 4Gb of

8
src/intel/compiler/brw/brw_lower_logical_sends.cpp
View file

@ -1674,7 +1674,6 @@ lower_lsc_varying_pull_constant_logical_send(const brw_builder &bld,
brw_inst *inst)
{
const intel_device_info *devinfo = bld.shader->devinfo;
ASSERTED const brw_compiler *compiler = bld.shader->compiler;
assert(inst->src[PULL_VARYING_CONSTANT_SRC_BINDING_TYPE].file == IMM);
enum lsc_addr_surface_type surf_type =
@ -1699,7 +1698,7 @@ lower_lsc_varying_pull_constant_logical_send(const brw_builder &bld,
send->sfid = BRW_SFID_UGM;
assert(!compiler->indirect_ubos_use_sampler);
assert(!intel_indirect_ubos_use_sampler(devinfo));
send->src[SEND_SRC_DESC] = brw_imm_ud(0);
send->src[SEND_SRC_EX_DESC] = brw_imm_ud(0);
@ -1746,7 +1745,6 @@ static void
lower_varying_pull_constant_logical_send(const brw_builder &bld, brw_inst *inst)
{
const intel_device_info *devinfo = bld.shader->devinfo;
const brw_compiler *compiler = bld.shader->compiler;
assert(inst->src[PULL_VARYING_CONSTANT_SRC_BINDING_TYPE].file == IMM);
enum lsc_addr_surface_type surf_type =
@ -1777,7 +1775,7 @@ lower_varying_pull_constant_logical_send(const brw_builder &bld, brw_inst *inst)
send->src[SEND_SRC_PAYLOAD1] = ubo_offset;
send->src[SEND_SRC_PAYLOAD2] = brw_reg();
if (compiler->indirect_ubos_use_sampler) {
if (intel_indirect_ubos_use_sampler(devinfo)) {
const unsigned simd_mode =
send->exec_size <= 8 ? BRW_SAMPLER_SIMD_MODE_SIMD8 :
BRW_SAMPLER_SIMD_MODE_SIMD16;
@ -2314,7 +2312,7 @@ brw_lower_logical_sends(brw_shader &s)
}
case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_LOGICAL:
if (devinfo->has_lsc && !s.compiler->indirect_ubos_use_sampler)
if (devinfo->has_lsc)
lower_lsc_varying_pull_constant_logical_send(ibld, inst);
else
lower_varying_pull_constant_logical_send(ibld, inst);

12
src/intel/dev/intel_device_info.h
View file

@ -214,6 +214,18 @@ enum intel_wa_steppings intel_device_info_wa_stepping(struct intel_device_info *
uint32_t intel_device_info_get_max_slm_size(const struct intel_device_info *devinfo);
uint32_t intel_device_info_get_max_preferred_slm_size(const struct intel_device_info *devinfo);
/**
* Whether indirect UBO loads should use the sampler or go through the
* data/constant cache. For the sampler, UBO surface states have to be set
* up with VK_FORMAT_R32G32B32A32_FLOAT whereas if it's going through the
* constant or data cache, UBOs must use VK_FORMAT_RAW.
*/
static inline bool
intel_indirect_ubos_use_sampler(const struct intel_device_info *devinfo)
{
return devinfo->ver < 12;
}
#ifdef __cplusplus
}
#endif

2
src/intel/vulkan/anv_cmd_buffer.c
View file

@ -995,7 +995,7 @@ anv_isl_format_for_descriptor_type(const struct anv_device *device,
switch (type) {
case VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER:
case VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC:
return device->physical->compiler->indirect_ubos_use_sampler ?
return intel_indirect_ubos_use_sampler(device->info) ?
ISL_FORMAT_R32G32B32A32_FLOAT : ISL_FORMAT_RAW;
case VK_DESCRIPTOR_TYPE_STORAGE_BUFFER:

3
src/intel/vulkan/anv_physical_device.c
View file

@ -1325,7 +1325,8 @@ get_properties(const struct anv_physical_device *pdevice,
.maxImageDimensionCube = (1 << 14),
.maxImageArrayLayers = (1 << 11),
.maxTexelBufferElements = 128 * 1024 * 1024,
.maxUniformBufferRange = pdevice->compiler->indirect_ubos_use_sampler ? (1u << 27) : (1u << 30),
.maxUniformBufferRange = intel_indirect_ubos_use_sampler(devinfo) ? (1u << 27) : (1u << 30),
.maxStorageBufferRange = MIN3(pdevice->isl_dev.max_buffer_size, max_heap_size, UINT32_MAX),
.maxPushConstantsSize = MAX_PUSH_CONSTANTS_SIZE,
.maxMemoryAllocationCount = UINT32_MAX,

4
src/intel/vulkan/genX_cmd_buffer.c
View file

@ -4477,7 +4477,7 @@ anv_pipe_invalidate_bits_for_access_flags(struct anv_cmd_buffer *cmd_buffer,
* port) to avoid stale data.
*/
pipe_bits |= ANV_PIPE_CONSTANT_CACHE_INVALIDATE_BIT;
if (device->physical->compiler->indirect_ubos_use_sampler) {
if (intel_indirect_ubos_use_sampler(device->info)) {
pipe_bits |= ANV_PIPE_TEXTURE_CACHE_INVALIDATE_BIT;
} else {
pipe_bits |= ANV_PIPE_HDC_PIPELINE_FLUSH_BIT;
@ -4498,7 +4498,7 @@ anv_pipe_invalidate_bits_for_access_flags(struct anv_cmd_buffer *cmd_buffer,
*/
pipe_bits |= ANV_PIPE_CONSTANT_CACHE_INVALIDATE_BIT |
ANV_PIPE_TEXTURE_CACHE_INVALIDATE_BIT;
if (!device->physical->compiler->indirect_ubos_use_sampler) {
if (!intel_indirect_ubos_use_sampler(device->info)) {
pipe_bits |= ANV_PIPE_HDC_PIPELINE_FLUSH_BIT;
pipe_bits |= ANV_PIPE_UNTYPED_DATAPORT_CACHE_FLUSH_BIT;
}