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r600g: Add FC_NATIVE instruction

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This is a pseudo instruction that enables the LLVM backend to encode
instructions and pass it through r600_bytecode_build()

Signed-off-by: Tom Stellard <thomas.stellard@amd.com>
This commit is contained in:
Tom Stellard 2012-02-27 15:42:48 -05:00
parent 4a26454e97
commit 94a6a36379
3 changed files with 20 additions and 0 deletions
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4
src/gallium/drivers/r600/eg_asm.c
View file

@ -133,6 +133,10 @@ int eg_bytecode_cf_build(struct r600_bytecode *bc, struct r600_bytecode_cf *cf)
S_SQ_CF_WORD1_COND(cf->cond) |
S_SQ_CF_WORD1_POP_COUNT(cf->pop_count);
break;
case CF_NATIVE:
bc->bytecode[id++] = cf->isa[0];
bc->bytecode[id++] = cf->isa[1];
break;
default:
R600_ERR("unsupported CF instruction (0x%X)\n", cf->inst);
return -EINVAL;

7
src/gallium/drivers/r600/r600_asm.c
View file

@ -1927,6 +1927,7 @@ int r600_bytecode_build(struct r600_bytecode *bc)
case EG_V_SQ_CF_WORD1_SQ_CF_INST_CALL_FS:
case EG_V_SQ_CF_WORD1_SQ_CF_INST_RETURN:
case CM_V_SQ_CF_WORD1_SQ_CF_INST_END:
case CF_NATIVE:
break;
default:
R600_ERR("unsupported CF instruction (0x%X)\n", cf->inst);
@ -2069,6 +2070,8 @@ int r600_bytecode_build(struct r600_bytecode *bc)
case EG_V_SQ_CF_WORD1_SQ_CF_INST_RETURN:
case CM_V_SQ_CF_WORD1_SQ_CF_INST_END:
break;
case CF_NATIVE:
break;
default:
R600_ERR("unsupported CF instruction (0x%X)\n", cf->inst);
return -EINVAL;
@ -2341,6 +2344,10 @@ void r600_bytecode_dump(struct r600_bytecode *bc)
fprintf(stderr, "COND:%X ", cf->cond);
fprintf(stderr, "POP_COUNT:%X\n", cf->pop_count);
break;
case CF_NATIVE:
fprintf(stderr, "%04d %08X CF NATIVE\n", id, bc->bytecode[id]);
fprintf(stderr, "%04d %08X CF NATIVE\n", id + 1, bc->bytecode[id + 1]);
break;
default:
R600_ERR("Unknown instruction %0x\n", cf->inst);
}

9
src/gallium/drivers/r600/r600_asm.h
View file

@ -135,6 +135,14 @@ struct r600_bytecode_kcache {
unsigned addr;
};
/* A value of CF_NATIVE in r600_bytecode_cf::inst means that this instruction
* has already been encoded, and the encoding has been stored in
* r600_bytecode::isa. This is used by the LLVM backend to emit CF instructions
* e.g. RAT_WRITE_* that can't be properly represented by struct
* r600_bytecode_cf.
*/
#define CF_NATIVE ~0
struct r600_bytecode_cf {
struct list_head list;
@ -157,6 +165,7 @@ struct r600_bytecode_cf {
struct r600_bytecode_alu *curr_bs_head;
struct r600_bytecode_alu *prev_bs_head;
struct r600_bytecode_alu *prev2_bs_head;
unsigned isa[2];
};
#define FC_NONE 0