fdo-mirrors/mesa
1
0
Fork 0
mirror of https://gitlab.freedesktop.org/mesa/mesa.git synced 2026-05-05 00:58:05 +02:00
Code Issues Projects Releases Packages Wiki Activity Actions 2

winsys/amdgpu: remove the dcc_enable surface flag

Browse source 
dcc_size is sufficient and doesn't need a further comment in my opinion.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
This commit is contained in:
Marek Olšák 2015-10-26 11:11:44 +01:00
parent 3aebc596b3
commit 93eb4f9287
3 changed files with 7 additions and 10 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

3
src/gallium/drivers/radeon/r600_texture.c
View file

@ -641,9 +641,8 @@ r600_texture_create_object(struct pipe_screen *screen,
return NULL;
}
}
if (rtex->surface.dcc_enabled) {
if (rtex->surface.dcc_size)
vi_texture_alloc_dcc_separate(rscreen, rtex);
}
}
/* Now create the backing buffer. */

1
src/gallium/drivers/radeon/radeon_winsys.h
View file

@ -371,7 +371,6 @@ struct radeon_surf {
uint64_t dcc_size;
uint64_t dcc_alignment;
bool dcc_enabled;
};
struct radeon_bo_list_item {

13
src/gallium/winsys/amdgpu/drm/amdgpu_surface.c
View file

@ -251,7 +251,7 @@ static int compute_level(struct amdgpu_winsys *ws,
surf->bo_size = surf_level->offset + AddrSurfInfoOut->surfSize;
if (surf->dcc_enabled) {
if (AddrSurfInfoIn->flags.dccCompatible) {
AddrDccIn->colorSurfSize = AddrSurfInfoOut->surfSize;
AddrDccIn->tileMode = AddrSurfInfoOut->tileMode;
AddrDccIn->tileInfo = *AddrSurfInfoOut->pTileInfo;
@ -267,10 +267,11 @@ static int compute_level(struct amdgpu_winsys *ws,
surf->dcc_size = surf_level->dcc_offset + AddrDccOut->dccRamSize;
surf->dcc_alignment = MAX2(surf->dcc_alignment, AddrDccOut->dccRamBaseAlign);
} else {
surf->dcc_enabled = false;
surf->dcc_size = 0;
surf_level->dcc_offset = 0;
}
} else {
surf->dcc_size = 0;
surf_level->dcc_offset = 0;
}
@ -354,10 +355,6 @@ static int amdgpu_surface_init(struct radeon_winsys *rws,
AddrDccIn.numSamples = AddrSurfInfoIn.numSamples = surf->nsamples;
AddrSurfInfoIn.tileIndex = -1;
surf->dcc_enabled = !(surf->flags & RADEON_SURF_Z_OR_SBUFFER) &&
!(surf->flags & RADEON_SURF_SCANOUT) &&
!compressed && AddrDccIn.numSamples <= 1;
/* Set the micro tile type. */
if (surf->flags & RADEON_SURF_SCANOUT)
AddrSurfInfoIn.tileType = ADDR_DISPLAYABLE;
@ -373,7 +370,9 @@ static int amdgpu_surface_init(struct radeon_winsys *rws,
AddrSurfInfoIn.flags.display = (surf->flags & RADEON_SURF_SCANOUT) != 0;
AddrSurfInfoIn.flags.pow2Pad = surf->last_level > 0;
AddrSurfInfoIn.flags.degrade4Space = 1;
AddrSurfInfoIn.flags.dccCompatible = surf->dcc_enabled;
AddrSurfInfoIn.flags.dccCompatible = !(surf->flags & RADEON_SURF_Z_OR_SBUFFER) &&
!(surf->flags & RADEON_SURF_SCANOUT) &&
!compressed && AddrDccIn.numSamples <= 1;
/* This disables incorrect calculations (hacks) in addrlib. */
AddrSurfInfoIn.flags.noStencil = 1;