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radv: emit BREAK_BATCH when the PS changes also for ESO

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Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37022>
This commit is contained in:
Samuel Pitoiset 2025-08-26 17:24:10 +02:00 • committed by Marge Bot
parent 93ffb0db03
commit 93d3427543
2 changed files with 16 additions and 17 deletions
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32
src/amd/vulkan/radv_cmd_buffer.c
View file

@ -3639,10 +3639,24 @@ radv_emit_fragment_shader(struct radv_cmd_buffer *cmd_buffer)
{
const struct radv_device *device = radv_cmd_buffer_device(cmd_buffer);
const struct radv_physical_device *pdev = radv_device_physical(device);
const struct radv_shader *ps = cmd_buffer->state.shaders[MESA_SHADER_FRAGMENT];
struct radv_shader *ps = cmd_buffer->state.shaders[MESA_SHADER_FRAGMENT];
struct radv_cmd_stream *cs = cmd_buffer->cs;
const uint64_t va = radv_shader_get_va(ps);
if (device->pbb_allowed) {
const struct radv_binning_settings *settings = &pdev->binning_settings;
if (cmd_buffer->state.emitted_ps != ps &&
(settings->context_states_per_bin > 1 || settings->persistent_states_per_bin > 1)) {
/* Break the batch on PS changes. */
radeon_begin(cs);
radeon_event_write(V_028A90_BREAK_BATCH);
radeon_end();
cmd_buffer->state.emitted_ps = ps;
}
}
radeon_begin(cs);
if (pdev->info.gfx_level >= GFX12) {
gfx12_push_sh_reg(ps->info.regs.pgm_lo, va >> 8);
@ -3924,28 +3938,12 @@ radv_emit_graphics_pipeline(struct radv_cmd_buffer *cmd_buffer)
{
struct radv_graphics_pipeline *pipeline = cmd_buffer->state.graphics_pipeline;
struct radv_device *device = radv_cmd_buffer_device(cmd_buffer);
const struct radv_physical_device *pdev = radv_device_physical(device);
struct radv_cmd_stream *cs = cmd_buffer->cs;
if (cmd_buffer->state.emitted_graphics_pipeline == pipeline)
return;
radv_emit_graphics_shaders(cmd_buffer);
if (device->pbb_allowed) {
const struct radv_binning_settings *settings = &pdev->binning_settings;
if ((!cmd_buffer->state.emitted_graphics_pipeline ||
cmd_buffer->state.emitted_graphics_pipeline->base.shaders[MESA_SHADER_FRAGMENT] !=
cmd_buffer->state.graphics_pipeline->base.shaders[MESA_SHADER_FRAGMENT]) &&
(settings->context_states_per_bin > 1 || settings->persistent_states_per_bin > 1)) {
/* Break the batch on PS changes. */
radeon_begin(cs);
radeon_event_write(V_028A90_BREAK_BATCH);
radeon_end();
}
}
if (pipeline->sqtt_shaders_reloc) {
/* Emit shaders relocation because RGP requires them to be contiguous in memory. */
radv_sqtt_emit_relocated_shaders(cmd_buffer, pipeline);

1
src/amd/vulkan/radv_cmd_buffer.h
View file

@ -499,6 +499,7 @@ struct radv_cmd_state {
struct radv_shader_part *emitted_vs_prolog;
uint32_t vbo_bound_mask;
struct radv_shader *emitted_ps;
struct radv_shader_part *emitted_ps_epilog;
/* Whether to suspend streamout for internal driver operations. */