etnaviv: ASTC texture support

Add ASTC texture support for hardware that supports this
(currently only GC3000 on i.MX6qp is known to have this).

Signed-off-by: Wladimir J. van der Laan <laanwj@gmail.com>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
This commit is contained in:
Wladimir J. van der Laan 2017-11-01 18:19:02 +01:00 committed by Christian Gmeiner
parent f1e1c60ff6
commit 93ba3f29bb
7 changed files with 57 additions and 2 deletions

View file

@ -703,6 +703,14 @@ etna_emit_state(struct etna_context *ctx)
/*03828*/ EMIT_STATE(GL_VARYING_COMPONENT_USE(x), ctx->shader_state.GL_VARYING_COMPONENT_USE[x]);
}
}
if (unlikely(ctx->specs.tex_astc && (dirty & (ETNA_DIRTY_SAMPLER_VIEWS)))) {
for (int x = 0; x < VIVS_TE_SAMPLER__LEN; ++x) {
if ((1 << x) & active_samplers) {
struct etna_sampler_view *sv = etna_sampler_view(ctx->sampler_view[x]);
/*10500*/ EMIT_STATE(NTE_SAMPLER_ASTC0(x), sv->TE_SAMPLER_ASTC0);
}
}
}
etna_coalesce_end(stream, &coalesce);
/* end only EMIT_STATE */

View file

@ -246,6 +246,36 @@ static struct etna_format formats[PIPE_FORMAT_COUNT] = {
_T(ETC2_RG11_UNORM, EXT_RG11_EAC | EXT_FORMAT, SWIZ(X, Y, Z, W), NONE),
_T(ETC2_RG11_SNORM, EXT_SIGNED_RG11_EAC | EXT_FORMAT, SWIZ(X, Y, Z, W), NONE),
_T(ASTC_4x4, ASTC_RGBA_4x4 | ASTC_FORMAT, SWIZ(X, Y, Z, W), NONE),
_T(ASTC_5x4, ASTC_RGBA_5x4 | ASTC_FORMAT, SWIZ(X, Y, Z, W), NONE),
_T(ASTC_5x5, ASTC_RGBA_5x5 | ASTC_FORMAT, SWIZ(X, Y, Z, W), NONE),
_T(ASTC_6x5, ASTC_RGBA_6x5 | ASTC_FORMAT, SWIZ(X, Y, Z, W), NONE),
_T(ASTC_6x6, ASTC_RGBA_6x6 | ASTC_FORMAT, SWIZ(X, Y, Z, W), NONE),
_T(ASTC_8x5, ASTC_RGBA_8x5 | ASTC_FORMAT, SWIZ(X, Y, Z, W), NONE),
_T(ASTC_8x6, ASTC_RGBA_8x6 | ASTC_FORMAT, SWIZ(X, Y, Z, W), NONE),
_T(ASTC_8x8, ASTC_RGBA_8x8 | ASTC_FORMAT, SWIZ(X, Y, Z, W), NONE),
_T(ASTC_10x5, ASTC_RGBA_10x5 | ASTC_FORMAT, SWIZ(X, Y, Z, W), NONE),
_T(ASTC_10x6, ASTC_RGBA_10x6 | ASTC_FORMAT, SWIZ(X, Y, Z, W), NONE),
_T(ASTC_10x8, ASTC_RGBA_10x8 | ASTC_FORMAT, SWIZ(X, Y, Z, W), NONE),
_T(ASTC_10x10, ASTC_RGBA_10x10 | ASTC_FORMAT, SWIZ(X, Y, Z, W), NONE),
_T(ASTC_12x10, ASTC_RGBA_12x10 | ASTC_FORMAT, SWIZ(X, Y, Z, W), NONE),
_T(ASTC_12x12, ASTC_RGBA_12x12 | ASTC_FORMAT, SWIZ(X, Y, Z, W), NONE),
_T(ASTC_4x4_SRGB, ASTC_SRGB8_ALPHA8_4x4 | ASTC_FORMAT, SWIZ(X, Y, Z, W), NONE),
_T(ASTC_5x4_SRGB, ASTC_SRGB8_ALPHA8_5x4 | ASTC_FORMAT, SWIZ(X, Y, Z, W), NONE),
_T(ASTC_5x5_SRGB, ASTC_SRGB8_ALPHA8_5x5 | ASTC_FORMAT, SWIZ(X, Y, Z, W), NONE),
_T(ASTC_6x5_SRGB, ASTC_SRGB8_ALPHA8_6x5 | ASTC_FORMAT, SWIZ(X, Y, Z, W), NONE),
_T(ASTC_6x6_SRGB, ASTC_SRGB8_ALPHA8_6x6 | ASTC_FORMAT, SWIZ(X, Y, Z, W), NONE),
_T(ASTC_8x5_SRGB, ASTC_SRGB8_ALPHA8_8x5 | ASTC_FORMAT, SWIZ(X, Y, Z, W), NONE),
_T(ASTC_8x6_SRGB, ASTC_SRGB8_ALPHA8_8x6 | ASTC_FORMAT, SWIZ(X, Y, Z, W), NONE),
_T(ASTC_8x8_SRGB, ASTC_SRGB8_ALPHA8_8x8 | ASTC_FORMAT, SWIZ(X, Y, Z, W), NONE),
_T(ASTC_10x5_SRGB, ASTC_SRGB8_ALPHA8_10x5 | ASTC_FORMAT, SWIZ(X, Y, Z, W), NONE),
_T(ASTC_10x6_SRGB, ASTC_SRGB8_ALPHA8_10x6 | ASTC_FORMAT, SWIZ(X, Y, Z, W), NONE),
_T(ASTC_10x8_SRGB, ASTC_SRGB8_ALPHA8_10x8 | ASTC_FORMAT, SWIZ(X, Y, Z, W), NONE),
_T(ASTC_10x10_SRGB, ASTC_SRGB8_ALPHA8_10x10 | ASTC_FORMAT, SWIZ(X, Y, Z, W), NONE),
_T(ASTC_12x10_SRGB, ASTC_SRGB8_ALPHA8_12x10 | ASTC_FORMAT, SWIZ(X, Y, Z, W), NONE),
_T(ASTC_12x12_SRGB, ASTC_SRGB8_ALPHA8_12x12 | ASTC_FORMAT, SWIZ(X, Y, Z, W), NONE),
/* YUV */
_T(YUYV, YUY2, SWIZ(X, Y, Z, W), YUY2),
_T(UYVY, UYVY, SWIZ(X, Y, Z, W), NONE),

View file

@ -32,6 +32,7 @@
#define ETNA_NO_MATCH (~0)
#define EXT_FORMAT (1 << 31)
#define ASTC_FORMAT (1 << 30)
uint32_t
translate_texture_format(enum pipe_format fmt);

View file

@ -80,6 +80,8 @@ struct etna_specs {
unsigned has_unified_uniforms : 1;
/* can load shader instructions from memory */
unsigned has_icache : 1;
/* ASTC texture support (and has associated states) */
unsigned tex_astc : 1;
/* can use any kind of wrapping mode on npot textures */
unsigned npot_tex_any_wrap;
/* number of bits per TS tile */

View file

@ -500,6 +500,10 @@ gpu_supports_texure_format(struct etna_screen *screen, uint32_t fmt,
supported = VIV_FEATURE(screen, chipMinorFeatures2, HALTI1);
}
if (fmt & ASTC_FORMAT) {
supported = screen->specs.tex_astc;
}
if (!supported)
return false;
@ -789,6 +793,8 @@ etna_get_specs(struct etna_screen *screen)
if (screen->specs.single_buffer)
DBG("etnaviv: Single buffer mode enabled with %d pixel pipes\n", screen->specs.pixel_pipes);
screen->specs.tex_astc = VIV_FEATURE(screen, chipMinorFeatures4, TEXTURE_ASTC);
return true;
fail:

View file

@ -173,6 +173,7 @@ etna_create_sampler_view(struct pipe_context *pctx, struct pipe_resource *prsc,
struct etna_context *ctx = etna_context(pctx);
const uint32_t format = translate_texture_format(so->format);
const bool ext = !!(format & EXT_FORMAT);
const bool astc = !!(format & ASTC_FORMAT);
const uint32_t swiz = get_texture_swiz(so->format, so->swizzle_r,
so->swizzle_g, so->swizzle_b,
so->swizzle_a);
@ -207,7 +208,7 @@ etna_create_sampler_view(struct pipe_context *pctx, struct pipe_resource *prsc,
sv->base.context = pctx;
/* merged with sampler state */
sv->TE_SAMPLER_CONFIG0 = COND(!ext, VIVS_TE_SAMPLER_CONFIG0_FORMAT(format));
sv->TE_SAMPLER_CONFIG0 = COND(!ext && !astc, VIVS_TE_SAMPLER_CONFIG0_FORMAT(format));
sv->TE_SAMPLER_CONFIG0_MASK = 0xffffffff;
switch (sv->base.target) {
@ -231,13 +232,19 @@ etna_create_sampler_view(struct pipe_context *pctx, struct pipe_resource *prsc,
}
sv->TE_SAMPLER_CONFIG1 = COND(ext, VIVS_TE_SAMPLER_CONFIG1_FORMAT_EXT(format)) |
COND(astc, VIVS_TE_SAMPLER_CONFIG1_FORMAT_EXT(TEXTURE_FORMAT_EXT_ASTC)) |
VIVS_TE_SAMPLER_CONFIG1_HALIGN(res->halign) | swiz;
sv->TE_SAMPLER_ASTC0 = COND(astc, VIVS_NTE_SAMPLER_ASTC0_ASTC_FORMAT(format)) |
VIVS_NTE_SAMPLER_ASTC0_UNK8(0xc) |
VIVS_NTE_SAMPLER_ASTC0_UNK16(0xc) |
VIVS_NTE_SAMPLER_ASTC0_UNK24(0xc);
sv->TE_SAMPLER_SIZE = VIVS_TE_SAMPLER_SIZE_WIDTH(res->base.width0) |
VIVS_TE_SAMPLER_SIZE_HEIGHT(res->base.height0);
sv->TE_SAMPLER_LOG_SIZE =
VIVS_TE_SAMPLER_LOG_SIZE_WIDTH(etna_log2_fixp55(res->base.width0)) |
VIVS_TE_SAMPLER_LOG_SIZE_HEIGHT(etna_log2_fixp55(res->base.height0)) |
COND(util_format_is_srgb(so->format), VIVS_TE_SAMPLER_LOG_SIZE_SRGB);
COND(util_format_is_srgb(so->format) && !astc, VIVS_TE_SAMPLER_LOG_SIZE_SRGB) |
COND(astc, VIVS_TE_SAMPLER_LOG_SIZE_ASTC);
/* Set up levels-of-detail */
for (int lod = 0; lod <= res->base.last_level; ++lod) {

View file

@ -59,6 +59,7 @@ struct etna_sampler_view {
uint32_t TE_SAMPLER_CONFIG1;
uint32_t TE_SAMPLER_SIZE;
uint32_t TE_SAMPLER_LOG_SIZE;
uint32_t TE_SAMPLER_ASTC0;
struct etna_reloc TE_SAMPLER_LOD_ADDR[VIVS_TE_SAMPLER_LOD_ADDR__LEN];
unsigned min_lod, max_lod; /* 5.5 fixp */
};