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etnaviv: ASTC texture support
Add ASTC texture support for hardware that supports this (currently only GC3000 on i.MX6qp is known to have this). Signed-off-by: Wladimir J. van der Laan <laanwj@gmail.com> Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
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parent
f1e1c60ff6
commit
93ba3f29bb
7 changed files with 57 additions and 2 deletions
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@ -703,6 +703,14 @@ etna_emit_state(struct etna_context *ctx)
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/*03828*/ EMIT_STATE(GL_VARYING_COMPONENT_USE(x), ctx->shader_state.GL_VARYING_COMPONENT_USE[x]);
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}
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}
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if (unlikely(ctx->specs.tex_astc && (dirty & (ETNA_DIRTY_SAMPLER_VIEWS)))) {
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for (int x = 0; x < VIVS_TE_SAMPLER__LEN; ++x) {
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if ((1 << x) & active_samplers) {
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struct etna_sampler_view *sv = etna_sampler_view(ctx->sampler_view[x]);
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/*10500*/ EMIT_STATE(NTE_SAMPLER_ASTC0(x), sv->TE_SAMPLER_ASTC0);
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}
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}
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}
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etna_coalesce_end(stream, &coalesce);
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/* end only EMIT_STATE */
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@ -246,6 +246,36 @@ static struct etna_format formats[PIPE_FORMAT_COUNT] = {
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_T(ETC2_RG11_UNORM, EXT_RG11_EAC | EXT_FORMAT, SWIZ(X, Y, Z, W), NONE),
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_T(ETC2_RG11_SNORM, EXT_SIGNED_RG11_EAC | EXT_FORMAT, SWIZ(X, Y, Z, W), NONE),
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_T(ASTC_4x4, ASTC_RGBA_4x4 | ASTC_FORMAT, SWIZ(X, Y, Z, W), NONE),
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_T(ASTC_5x4, ASTC_RGBA_5x4 | ASTC_FORMAT, SWIZ(X, Y, Z, W), NONE),
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_T(ASTC_5x5, ASTC_RGBA_5x5 | ASTC_FORMAT, SWIZ(X, Y, Z, W), NONE),
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_T(ASTC_6x5, ASTC_RGBA_6x5 | ASTC_FORMAT, SWIZ(X, Y, Z, W), NONE),
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_T(ASTC_6x6, ASTC_RGBA_6x6 | ASTC_FORMAT, SWIZ(X, Y, Z, W), NONE),
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_T(ASTC_8x5, ASTC_RGBA_8x5 | ASTC_FORMAT, SWIZ(X, Y, Z, W), NONE),
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_T(ASTC_8x6, ASTC_RGBA_8x6 | ASTC_FORMAT, SWIZ(X, Y, Z, W), NONE),
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_T(ASTC_8x8, ASTC_RGBA_8x8 | ASTC_FORMAT, SWIZ(X, Y, Z, W), NONE),
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_T(ASTC_10x5, ASTC_RGBA_10x5 | ASTC_FORMAT, SWIZ(X, Y, Z, W), NONE),
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_T(ASTC_10x6, ASTC_RGBA_10x6 | ASTC_FORMAT, SWIZ(X, Y, Z, W), NONE),
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_T(ASTC_10x8, ASTC_RGBA_10x8 | ASTC_FORMAT, SWIZ(X, Y, Z, W), NONE),
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_T(ASTC_10x10, ASTC_RGBA_10x10 | ASTC_FORMAT, SWIZ(X, Y, Z, W), NONE),
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_T(ASTC_12x10, ASTC_RGBA_12x10 | ASTC_FORMAT, SWIZ(X, Y, Z, W), NONE),
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_T(ASTC_12x12, ASTC_RGBA_12x12 | ASTC_FORMAT, SWIZ(X, Y, Z, W), NONE),
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_T(ASTC_4x4_SRGB, ASTC_SRGB8_ALPHA8_4x4 | ASTC_FORMAT, SWIZ(X, Y, Z, W), NONE),
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_T(ASTC_5x4_SRGB, ASTC_SRGB8_ALPHA8_5x4 | ASTC_FORMAT, SWIZ(X, Y, Z, W), NONE),
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_T(ASTC_5x5_SRGB, ASTC_SRGB8_ALPHA8_5x5 | ASTC_FORMAT, SWIZ(X, Y, Z, W), NONE),
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_T(ASTC_6x5_SRGB, ASTC_SRGB8_ALPHA8_6x5 | ASTC_FORMAT, SWIZ(X, Y, Z, W), NONE),
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_T(ASTC_6x6_SRGB, ASTC_SRGB8_ALPHA8_6x6 | ASTC_FORMAT, SWIZ(X, Y, Z, W), NONE),
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_T(ASTC_8x5_SRGB, ASTC_SRGB8_ALPHA8_8x5 | ASTC_FORMAT, SWIZ(X, Y, Z, W), NONE),
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_T(ASTC_8x6_SRGB, ASTC_SRGB8_ALPHA8_8x6 | ASTC_FORMAT, SWIZ(X, Y, Z, W), NONE),
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_T(ASTC_8x8_SRGB, ASTC_SRGB8_ALPHA8_8x8 | ASTC_FORMAT, SWIZ(X, Y, Z, W), NONE),
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_T(ASTC_10x5_SRGB, ASTC_SRGB8_ALPHA8_10x5 | ASTC_FORMAT, SWIZ(X, Y, Z, W), NONE),
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_T(ASTC_10x6_SRGB, ASTC_SRGB8_ALPHA8_10x6 | ASTC_FORMAT, SWIZ(X, Y, Z, W), NONE),
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_T(ASTC_10x8_SRGB, ASTC_SRGB8_ALPHA8_10x8 | ASTC_FORMAT, SWIZ(X, Y, Z, W), NONE),
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_T(ASTC_10x10_SRGB, ASTC_SRGB8_ALPHA8_10x10 | ASTC_FORMAT, SWIZ(X, Y, Z, W), NONE),
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_T(ASTC_12x10_SRGB, ASTC_SRGB8_ALPHA8_12x10 | ASTC_FORMAT, SWIZ(X, Y, Z, W), NONE),
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_T(ASTC_12x12_SRGB, ASTC_SRGB8_ALPHA8_12x12 | ASTC_FORMAT, SWIZ(X, Y, Z, W), NONE),
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/* YUV */
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_T(YUYV, YUY2, SWIZ(X, Y, Z, W), YUY2),
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_T(UYVY, UYVY, SWIZ(X, Y, Z, W), NONE),
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@ -32,6 +32,7 @@
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#define ETNA_NO_MATCH (~0)
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#define EXT_FORMAT (1 << 31)
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#define ASTC_FORMAT (1 << 30)
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uint32_t
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translate_texture_format(enum pipe_format fmt);
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@ -80,6 +80,8 @@ struct etna_specs {
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unsigned has_unified_uniforms : 1;
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/* can load shader instructions from memory */
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unsigned has_icache : 1;
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/* ASTC texture support (and has associated states) */
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unsigned tex_astc : 1;
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/* can use any kind of wrapping mode on npot textures */
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unsigned npot_tex_any_wrap;
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/* number of bits per TS tile */
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@ -500,6 +500,10 @@ gpu_supports_texure_format(struct etna_screen *screen, uint32_t fmt,
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supported = VIV_FEATURE(screen, chipMinorFeatures2, HALTI1);
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}
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if (fmt & ASTC_FORMAT) {
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supported = screen->specs.tex_astc;
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}
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if (!supported)
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return false;
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@ -789,6 +793,8 @@ etna_get_specs(struct etna_screen *screen)
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if (screen->specs.single_buffer)
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DBG("etnaviv: Single buffer mode enabled with %d pixel pipes\n", screen->specs.pixel_pipes);
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screen->specs.tex_astc = VIV_FEATURE(screen, chipMinorFeatures4, TEXTURE_ASTC);
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return true;
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fail:
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@ -173,6 +173,7 @@ etna_create_sampler_view(struct pipe_context *pctx, struct pipe_resource *prsc,
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struct etna_context *ctx = etna_context(pctx);
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const uint32_t format = translate_texture_format(so->format);
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const bool ext = !!(format & EXT_FORMAT);
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const bool astc = !!(format & ASTC_FORMAT);
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const uint32_t swiz = get_texture_swiz(so->format, so->swizzle_r,
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so->swizzle_g, so->swizzle_b,
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so->swizzle_a);
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@ -207,7 +208,7 @@ etna_create_sampler_view(struct pipe_context *pctx, struct pipe_resource *prsc,
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sv->base.context = pctx;
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/* merged with sampler state */
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sv->TE_SAMPLER_CONFIG0 = COND(!ext, VIVS_TE_SAMPLER_CONFIG0_FORMAT(format));
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sv->TE_SAMPLER_CONFIG0 = COND(!ext && !astc, VIVS_TE_SAMPLER_CONFIG0_FORMAT(format));
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sv->TE_SAMPLER_CONFIG0_MASK = 0xffffffff;
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switch (sv->base.target) {
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@ -231,13 +232,19 @@ etna_create_sampler_view(struct pipe_context *pctx, struct pipe_resource *prsc,
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}
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sv->TE_SAMPLER_CONFIG1 = COND(ext, VIVS_TE_SAMPLER_CONFIG1_FORMAT_EXT(format)) |
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COND(astc, VIVS_TE_SAMPLER_CONFIG1_FORMAT_EXT(TEXTURE_FORMAT_EXT_ASTC)) |
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VIVS_TE_SAMPLER_CONFIG1_HALIGN(res->halign) | swiz;
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sv->TE_SAMPLER_ASTC0 = COND(astc, VIVS_NTE_SAMPLER_ASTC0_ASTC_FORMAT(format)) |
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VIVS_NTE_SAMPLER_ASTC0_UNK8(0xc) |
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VIVS_NTE_SAMPLER_ASTC0_UNK16(0xc) |
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VIVS_NTE_SAMPLER_ASTC0_UNK24(0xc);
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sv->TE_SAMPLER_SIZE = VIVS_TE_SAMPLER_SIZE_WIDTH(res->base.width0) |
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VIVS_TE_SAMPLER_SIZE_HEIGHT(res->base.height0);
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sv->TE_SAMPLER_LOG_SIZE =
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VIVS_TE_SAMPLER_LOG_SIZE_WIDTH(etna_log2_fixp55(res->base.width0)) |
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VIVS_TE_SAMPLER_LOG_SIZE_HEIGHT(etna_log2_fixp55(res->base.height0)) |
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COND(util_format_is_srgb(so->format), VIVS_TE_SAMPLER_LOG_SIZE_SRGB);
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COND(util_format_is_srgb(so->format) && !astc, VIVS_TE_SAMPLER_LOG_SIZE_SRGB) |
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COND(astc, VIVS_TE_SAMPLER_LOG_SIZE_ASTC);
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/* Set up levels-of-detail */
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for (int lod = 0; lod <= res->base.last_level; ++lod) {
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@ -59,6 +59,7 @@ struct etna_sampler_view {
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uint32_t TE_SAMPLER_CONFIG1;
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uint32_t TE_SAMPLER_SIZE;
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uint32_t TE_SAMPLER_LOG_SIZE;
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uint32_t TE_SAMPLER_ASTC0;
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struct etna_reloc TE_SAMPLER_LOD_ADDR[VIVS_TE_SAMPLER_LOD_ADDR__LEN];
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unsigned min_lod, max_lod; /* 5.5 fixp */
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};
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