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i965: Add AccWrCtl support on Sandybridge.

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Whenever the accumulator results are needed, this bit must be set.
This commit is contained in:
Zhenyu Wang 2010-08-20 14:37:19 -07:00 • committed by Eric Anholt
parent ffb5095d56
commit 93ba0055c3
5 changed files with 20 additions and 2 deletions
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7
src/mesa/drivers/dri/i965/brw_disasm.c
View file

@ -159,6 +159,11 @@ char *saturate[2] = {
[1] = ".sat"
};
char *accwr[2] = {
[0] = "",
[1] = "AccWrEnable"
};
char *exec_size[8] = {
[0] = "1",
[1] = "2",
@ -993,6 +998,8 @@ int brw_disasm (FILE *file, struct brw_instruction *inst, int gen)
inst->header.compression_control, &space);
}
err |= control (file, "thread control", thread_ctrl, inst->header.thread_control, &space);
if (gen >= 6)
err |= control (file, "acc write control", accwr, inst->header.acc_wr_control, &space);
if (inst->header.opcode == BRW_OPCODE_SEND)
err |= control (file, "end of thread", end_of_thread,
inst->bits3.generic.end_of_thread, &space);

6
src/mesa/drivers/dri/i965/brw_eu.c
View file

@ -85,6 +85,12 @@ void brw_set_saturate( struct brw_compile *p, GLuint value )
p->current->header.saturate = value;
}
void brw_set_acc_write_control(struct brw_compile *p, GLuint value)
{
if (p->brw->intel.gen >= 6)
p->current->header.acc_wr_control = value;
}
void brw_push_insn_state( struct brw_compile *p )
{
assert(p->current != &p->stack[BRW_EU_MAX_INSN_STACK-1]);

1
src/mesa/drivers/dri/i965/brw_eu.h
View file

@ -770,6 +770,7 @@ void brw_set_compression_control( struct brw_compile *p, GLboolean control );
void brw_set_predicate_control_flag_value( struct brw_compile *p, GLuint value );
void brw_set_predicate_control( struct brw_compile *p, GLuint pc );
void brw_set_conditionalmod( struct brw_compile *p, GLuint conditional );
void brw_set_acc_write_control(struct brw_compile *p, GLuint value);
void brw_init_compile( struct brw_context *, struct brw_compile *p );
const GLuint *brw_get_program( struct brw_compile *p, GLuint *sz );

5
src/mesa/drivers/dri/i965/brw_structs.h
View file

@ -1305,13 +1305,14 @@ struct brw_instruction
GLuint access_mode:1;
GLuint mask_control:1;
GLuint dependency_control:2;
GLuint compression_control:2;
GLuint compression_control:2; /* gen6: quater control */
GLuint thread_control:2;
GLuint predicate_control:4;
GLuint predicate_inverse:1;
GLuint execution_size:3;
GLuint destreg__conditionalmod:4; /* destreg - send, conditionalmod - others */
GLuint pad0:2;
GLuint acc_wr_control:1;
GLuint cmpt_control:1;
GLuint debug_control:1;
GLuint saturate:1;
} header;

3
src/mesa/drivers/dri/i965/brw_vs_emit.c
View file

@ -1397,6 +1397,7 @@ static void emit_vertex_write( struct brw_vs_compile *c)
* of zeros followed by two sets of NDC coordinates:
*/
brw_set_access_mode(p, BRW_ALIGN_1);
brw_set_acc_write_control(p, 0);
/* The VUE layout is documented in Volume 2a. */
if (intel->gen >= 6) {
@ -1578,6 +1579,8 @@ void brw_vs_emit(struct brw_vs_compile *c )
brw_set_access_mode(p, BRW_ALIGN_16);
if_depth_in_loop[loop_depth] = 0;
brw_set_acc_write_control(p, 1);
for (insn = 0; insn < nr_insns; insn++) {
GLuint i;
struct prog_instruction *inst = &c->vp->program.Base.Instructions[insn];