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i965/gen8+: Add aux buffer alignment assertions

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This helped find the incorrect HALIGN values from the previous patches.

v2: Add PRM references for assertions (Chad)

v3: Remove duplicated part of commit message, assert num_samples > 1, instead of
num_samples > 0. (Chad)

Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
Reviewed-by: Chad Versace <chad.versace@intel.com>
Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
This commit is contained in:
Ben Widawsky 2015-05-14 09:28:37 -07:00
parent a2421623db
commit 935f1f60da
1 changed files with 22 additions and 0 deletions
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22
src/mesa/drivers/dri/i965/gen8_surface_state.c
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@ -178,6 +178,17 @@ gen8_emit_texture_surface_state(struct brw_context *brw,
if (mt->mcs_mt) {
aux_mt = mt->mcs_mt;
aux_mode = GEN8_SURFACE_AUX_MODE_MCS;
/*
* From the BDW PRM, Volume 2d, page 260 (RENDER_SURFACE_STATE):
* "When MCS is enabled for non-MSRT, HALIGN_16 must be used"
*
* From the hardware spec for GEN9:
* "When Auxiliary Surface Mode is set to AUX_CCS_D or AUX_CCS_E, HALIGN
* 16 must be used."
*/
assert(brw->gen < 9 || mt->align_w == 16);
assert(brw->gen < 8 || mt->num_samples > 1 || mt->align_w == 16);
}
uint32_t *surf = allocate_surface_state(brw, surf_offset, surf_index);
@ -391,6 +402,17 @@ gen8_update_renderbuffer_surface(struct brw_context *brw,
if (mt->mcs_mt) {
aux_mt = mt->mcs_mt;
aux_mode = GEN8_SURFACE_AUX_MODE_MCS;
/*
* From the BDW PRM, Volume 2d, page 260 (RENDER_SURFACE_STATE):
* "When MCS is enabled for non-MSRT, HALIGN_16 must be used"
*
* From the hardware spec for GEN9:
* "When Auxiliary Surface Mode is set to AUX_CCS_D or AUX_CCS_E, HALIGN
* 16 must be used."
*/
assert(brw->gen < 9 || mt->align_w == 16);
assert(brw->gen < 8 || mt->num_samples > 1 || mt->align_w == 16);
}
uint32_t *surf = allocate_surface_state(brw, &offset, surf_index);