From 933df6729646aefdfcb926ee2dc6dcf157fb0dfb Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Marek=20Ol=C5=A1=C3=A1k?= Date: Fri, 19 Mar 2021 20:42:14 -0400 Subject: [PATCH] ac/surface: add CMASK info for level 0 Reviewed-by: Pierre-Eric Pelloux-Prayer Part-of: --- src/amd/common/ac_surface.c | 6 ++++++ src/amd/common/ac_surface.h | 6 +++++- 2 files changed, 11 insertions(+), 1 deletion(-) diff --git a/src/amd/common/ac_surface.c b/src/amd/common/ac_surface.c index 4b06c23fbae..5ae8f1058cb 100644 --- a/src/amd/common/ac_surface.c +++ b/src/amd/common/ac_surface.c @@ -2102,9 +2102,11 @@ static int gfx9_compute_miptree(struct ac_addrlib *addrlib, const struct radeon_ (surf->fmask_size && in->numSamples >= 2))) { ADDR2_COMPUTE_CMASK_INFO_INPUT cin = {0}; ADDR2_COMPUTE_CMASK_INFO_OUTPUT cout = {0}; + ADDR2_META_MIP_INFO meta_mip_info[RADEON_SURF_MAX_LEVELS] = {0}; cin.size = sizeof(ADDR2_COMPUTE_CMASK_INFO_INPUT); cout.size = sizeof(ADDR2_COMPUTE_CMASK_INFO_OUTPUT); + cout.pMipInfo = meta_mip_info; assert(in->flags.metaPipeUnaligned == 0); assert(in->flags.metaRbUnaligned == 0); @@ -2115,6 +2117,8 @@ static int gfx9_compute_miptree(struct ac_addrlib *addrlib, const struct radeon_ cin.unalignedWidth = in->width; cin.unalignedHeight = in->height; cin.numSlices = in->numSlices; + cin.numMipLevels = in->numMipLevels; + cin.firstMipIdInTail = out.firstMipIdInTail; if (in->numSamples > 1) cin.swizzleMode = surf->u.gfx9.fmask.swizzle_mode; @@ -2128,6 +2132,8 @@ static int gfx9_compute_miptree(struct ac_addrlib *addrlib, const struct radeon_ surf->cmask_size = cout.cmaskBytes; surf->cmask_alignment = cout.baseAlign; surf->cmask_slice_size = cout.sliceSize; + surf->u.gfx9.cmask_level0.offset = meta_mip_info[0].offset; + surf->u.gfx9.cmask_level0.size = meta_mip_info[0].sliceSize; } } diff --git a/src/amd/common/ac_surface.h b/src/amd/common/ac_surface.h index 26feb4747b2..e8126d16cf3 100644 --- a/src/amd/common/ac_surface.h +++ b/src/amd/common/ac_surface.h @@ -151,7 +151,8 @@ struct gfx9_surf_meta_flags { struct gfx9_surf_level { unsigned offset; - unsigned size; + unsigned size; /* the size of one level in one layer (the image is an array of layers + * where each layer has an array of levels) */ }; struct gfx9_surf_layout { @@ -205,6 +206,9 @@ struct gfx9_surf_layout { /* HTILE level info */ struct gfx9_surf_level htile_levels[RADEON_SURF_MAX_LEVELS]; + + /* CMASK level info (only level 0) */ + struct gfx9_surf_level cmask_level0; }; struct radeon_surf {