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radeon/llvm: Move util functions into AMDGPU namespace

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This commit is contained in:
Tom Stellard 2012-05-10 12:49:41 -04:00
parent c569182461
commit 92faa21d29
3 changed files with 37 additions and 39 deletions
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42
src/gallium/drivers/radeon/AMDGPUUtil.cpp
View file

@ -1,4 +1,4 @@
//===-- AMDGPUUtil.cpp - TODO: Add brief description -------===//
//===-- AMDGPUUtil.cpp - AMDGPU Utility functions -------------------------===//
//
// The LLVM Compiler Infrastructure
//
@ -7,26 +7,26 @@
//
//===----------------------------------------------------------------------===//
//
// TODO: Add full description
// Common utility functions used by hw codegen targets
//
//===----------------------------------------------------------------------===//
#include "AMDGPUUtil.h"
#include "AMDGPURegisterInfo.h"
#include "AMDIL.h"
#include "llvm/CodeGen/MachineFunction.h"
#include "llvm/CodeGen/MachineInstrBuilder.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
#include "llvm/Support/ErrorHandling.h"
#include "llvm/Target/TargetInstrInfo.h"
#include "llvm/Target/TargetMachine.h"
#include "llvm/Target/TargetRegisterInfo.h"
using namespace llvm;
/* Some instructions act as place holders to emulate operations that the GPU
* hardware does automatically. This function can be used to check if
* an opcode falls into this category. */
bool llvm::isPlaceHolderOpcode(unsigned opcode)
// Some instructions act as place holders to emulate operations that the GPU
// hardware does automatically. This function can be used to check if
// an opcode falls into this category.
bool AMDGPU::isPlaceHolderOpcode(unsigned opcode)
{
switch (opcode) {
default: return false;
@ -39,7 +39,7 @@ bool llvm::isPlaceHolderOpcode(unsigned opcode)
}
}
bool llvm::isTransOp(unsigned opcode)
bool AMDGPU::isTransOp(unsigned opcode)
{
switch(opcode) {
default: return false;
@ -67,7 +67,7 @@ bool llvm::isTransOp(unsigned opcode)
}
}
bool llvm::isTexOp(unsigned opcode)
bool AMDGPU::isTexOp(unsigned opcode)
{
switch(opcode) {
default: return false;
@ -87,7 +87,7 @@ bool llvm::isTexOp(unsigned opcode)
}
}
bool llvm::isReductionOp(unsigned opcode)
bool AMDGPU::isReductionOp(unsigned opcode)
{
switch(opcode) {
default: return false;
@ -97,18 +97,18 @@ bool llvm::isReductionOp(unsigned opcode)
}
}
bool llvm::isCubeOp(unsigned opcode)
bool AMDGPU::isCubeOp(unsigned opcode)
{
switch(opcode) {
default: return false;
case AMDIL::CUBE_r600:
case AMDIL::CUBE_eg:
return true;
}
switch(opcode) {
default: return false;
case AMDIL::CUBE_r600:
case AMDIL::CUBE_eg:
return true;
}
}
bool llvm::isFCOp(unsigned opcode)
bool AMDGPU::isFCOp(unsigned opcode)
{
switch(opcode) {
default: return false;
@ -128,8 +128,10 @@ bool llvm::isFCOp(unsigned opcode)
}
}
void AMDGPU::utilAddLiveIn(MachineFunction * MF, MachineRegisterInfo & MRI,
const struct TargetInstrInfo * TII, unsigned physReg, unsigned virtReg)
void AMDGPU::utilAddLiveIn(llvm::MachineFunction * MF,
llvm::MachineRegisterInfo & MRI,
const struct llvm::TargetInstrInfo * TII,
unsigned physReg, unsigned virtReg)
{
if (!MRI.isLiveIn(physReg)) {
MRI.addLiveIn(physReg, virtReg);

24
src/gallium/drivers/radeon/AMDGPUUtil.h
View file

@ -1,4 +1,4 @@
//===-- AMDGPUUtil.h - TODO: Add brief description -------===//
//===-- AMDGPUUtil.h - AMDGPU Utility function declarations -----*- C++ -*-===//
//
// The LLVM Compiler Infrastructure
//
@ -7,22 +7,22 @@
//
//===----------------------------------------------------------------------===//
//
// TODO: Add full description
// Declarations for utility functions common to all hw codegen targets.
//
//===----------------------------------------------------------------------===//
#ifndef AMDGPU_UTIL_H
#define AMDGPU_UTIL_H
#include "AMDGPURegisterInfo.h"
#include "llvm/Support/DataTypes.h"
namespace llvm {
class AMDILMachineFunctionInfo;
class MachineFunction;
class MachineRegisterInfo;
class TargetInstrInfo;
class TargetMachine;
class TargetRegisterInfo;
}
namespace AMDGPU {
bool isPlaceHolderOpcode(unsigned opcode);
@ -32,19 +32,15 @@ bool isReductionOp(unsigned opcode);
bool isCubeOp(unsigned opcode);
bool isFCOp(unsigned opcode);
/* XXX: Move these to AMDGPUInstrInfo.h */
// XXX: Move these to AMDGPUInstrInfo.h
#define MO_FLAG_CLAMP (1 << 0)
#define MO_FLAG_NEG (1 << 1)
#define MO_FLAG_ABS (1 << 2)
#define MO_FLAG_MASK (1 << 3)
} /* End namespace llvm */
namespace AMDGPU {
void utilAddLiveIn(llvm::MachineFunction * MF, llvm::MachineRegisterInfo & MRI,
const struct llvm::TargetInstrInfo * TII, unsigned physReg, unsigned virtReg);
} // End namespace AMDGPU
#endif /* AMDGPU_UTIL_H */
#endif // AMDGPU_UTIL_H

10
src/gallium/drivers/radeon/R600CodeEmitter.cpp
View file

@ -170,11 +170,11 @@ bool R600CodeEmitter::runOnMachineFunction(MachineFunction &MF) {
if (MI.getNumOperands() > 1 && MI.getOperand(0).isReg() && MI.getOperand(0).isDead()) {
continue;
}
if (isTexOp(MI.getOpcode())) {
if (AMDGPU::isTexOp(MI.getOpcode())) {
emitTexInstr(MI);
} else if (isFCOp(MI.getOpcode())){
} else if (AMDGPU::isFCOp(MI.getOpcode())){
emitFCInstr(MI);
} else if (isReductionOp(MI.getOpcode())) {
} else if (AMDGPU::isReductionOp(MI.getOpcode())) {
isReduction = true;
isLast = false;
for (currentElement = 0; currentElement < 4; currentElement++) {
@ -182,7 +182,7 @@ bool R600CodeEmitter::runOnMachineFunction(MachineFunction &MF) {
emitALUInstr(MI);
}
isReduction = false;
} else if (isCubeOp(MI.getOpcode())) {
} else if (AMDGPU::isCubeOp(MI.getOpcode())) {
isCube = true;
isLast = false;
for (currentElement = 0; currentElement < 4; currentElement++) {
@ -288,7 +288,7 @@ void R600CodeEmitter::emitALUInstr(MachineInstr &MI)
/* Some instructions are just place holder instructions that represent
* operations that the GPU does automatically. They should be ignored. */
if (isPlaceHolderOpcode(MI.getOpcode())) {
if (AMDGPU::isPlaceHolderOpcode(MI.getOpcode())) {
return;
}