brw: brw_reg::nr for an accumulator is not part of the offset

Without this, reg_offset will return 1024 for acc0. This causes
has_invalid_dst_region to decide that the destination region is invalid
(because 1024 != 0), and the lowering code tries to treat the floating
point accumulators as integers. It's a mess.

v2: Add and use set_gfx_platform. Suggested by Caio.

Fixes: 937373eb25 ("i965/fs: Handle fixed HW GRF subnr in reg_offset().")
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
(cherry picked from commit cfdb3ddb93)

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40979>
This commit is contained in:
Ian Romanick 2026-03-27 20:59:38 -07:00 committed by Eric Engestrom
parent a46e96fbdb
commit 92bfcb208f
3 changed files with 15 additions and 2 deletions

View file

@ -3344,7 +3344,7 @@
"description": "brw: brw_reg::nr for an accumulator is not part of the offset",
"nominated": true,
"nomination_type": 2,
"resolution": 0,
"resolution": 1,
"main_sha": null,
"because_sha": "937373eb25c53b0803e526b7b273afc2b3330752",
"notes": null

View file

@ -1447,7 +1447,8 @@ reg_space(const brw_reg &r)
static inline unsigned
reg_offset(const brw_reg &r)
{
return (r.file == ADDRESS || r.file == VGRF || r.file == IMM || r.file == ATTR ? 0 : r.nr) *
return (r.file == ADDRESS || r.file == VGRF || r.file == IMM ||
r.file == ATTR || brw_reg_is_arf(r, BRW_ARF_ACCUMULATOR) ? 0 : r.nr) *
(r.file == UNIFORM ? 4 : REG_SIZE) + r.offset +
(r.file == ADDRESS || r.file == ARF || r.file == FIXED_GRF ? r.subnr : 0);
}

View file

@ -128,6 +128,18 @@ protected:
brw_init_isa_info(&compiler->isa, devinfo);
}
void
set_gfx_platform(const char *name)
{
int pci_id = intel_device_name_to_pci_device_id(name);
assert(pci_id > 0);
intel_get_device_info_from_pci_id(pci_id, devinfo);
assert(devinfo->ver > 0);
brw_init_isa_info(&compiler->isa, devinfo);
}
brw_builder
make_shader(mesa_shader_stage stage = MESA_SHADER_FRAGMENT,
unsigned dispatch_width = 0)