diff --git a/src/amd/common/ac_surface.c b/src/amd/common/ac_surface.c
index c39b9a26de2..4101af239ed 100644
--- a/src/amd/common/ac_surface.c
+++ b/src/amd/common/ac_surface.c
@@ -105,6 +105,14 @@ bool ac_modifier_has_dcc_retile(uint64_t modifier)
    return IS_AMD_FMT_MOD(modifier) && AMD_FMT_MOD_GET(DCC_RETILE, modifier);
 }
 
+bool ac_modifier_supports_dcc_image_stores(uint64_t modifier)
+{
+   return ac_modifier_has_dcc(modifier) &&
+         !AMD_FMT_MOD_GET(DCC_INDEPENDENT_64B, modifier) &&
+          AMD_FMT_MOD_GET(DCC_INDEPENDENT_128B, modifier) &&
+          AMD_FMT_MOD_GET(DCC_MAX_COMPRESSED_BLOCK, modifier) == AMD_FMT_MOD_DCC_BLOCK_128B;
+}
+
 static
 AddrSwizzleMode ac_modifier_gfx9_swizzle_mode(uint64_t modifier)
 {
diff --git a/src/amd/common/ac_surface.h b/src/amd/common/ac_surface.h
index d52a62de027..6a10e12247a 100644
--- a/src/amd/common/ac_surface.h
+++ b/src/amd/common/ac_surface.h
@@ -454,6 +454,7 @@ bool ac_get_supported_modifiers(const struct radeon_info *info,
                                 uint64_t *mods);
 bool ac_modifier_has_dcc(uint64_t modifier);
 bool ac_modifier_has_dcc_retile(uint64_t modifier);
+bool ac_modifier_supports_dcc_image_stores(uint64_t modifier);
 
 unsigned ac_surface_get_nplanes(const struct radeon_surf *surf);
 uint64_t ac_surface_get_plane_offset(enum chip_class chip_class,