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i965/vec4: fix assert to detect SIMD lowered DF instructions in IVB

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On IVB, DF instructions have lowered the SIMD width to 4 but the
exec_size will be later doubled. Fix the assert to avoid crashing in
this case.

Signed-off-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
[ Francisco Jerez: Simplify assert.  Except for the 'inst->group % 4
  == 0' part the assertion was redundant with the previous assertion. ]
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
This commit is contained in:
Francisco Jerez 2017-04-12 16:54:49 -07:00
parent 6e3265eae5
commit 92649a3e67
1 changed files with 1 additions and 5 deletions
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6
src/intel/compiler/brw_vec4_generator.cpp
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@ -1524,11 +1524,7 @@ generate_code(struct brw_codegen *p,
brw_set_default_acc_write_control(p, inst->writes_accumulator);
assert(inst->group % inst->exec_size == 0);
assert(inst->group % 8 == 0 ||
inst->dst.type == BRW_REGISTER_TYPE_DF ||
inst->src[0].type == BRW_REGISTER_TYPE_DF ||
inst->src[1].type == BRW_REGISTER_TYPE_DF ||
inst->src[2].type == BRW_REGISTER_TYPE_DF);
assert(inst->group % 4 == 0);
unsigned exec_size = inst->exec_size;
if (devinfo->gen == 7 &&