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https://gitlab.freedesktop.org/mesa/mesa.git
synced 2026-05-31 13:48:20 +02:00
radeon: move CB/ZB state init into emit code
This removes the use of the sarea for this stuff so makes DRI2 easier and emits the CB/ZB info in the correct place
This commit is contained in:
Dave Airlie
parent
158ede35d5
commit
925ea2d9a5
1 changed files with 51 additions and 82 deletions
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@ -312,37 +312,49 @@ static void ctx_emit(GLcontext *ctx, struct radeon_state_atom *atom)
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BATCH_LOCALS(&r100->radeon);
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struct radeon_renderbuffer *rrb;
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uint32_t cbpitch;
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uint32_t zbpitch;
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uint32_t zbpitch, depth_fmt;
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uint32_t dwords = atom->cmd_size;
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GLframebuffer *fb = r100->radeon.dri.drawable->driverPrivate;
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/* output the first 7 bytes of context */
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BEGIN_BATCH_NO_AUTOSTATE(dwords + 4);
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OUT_BATCH_TABLE(atom->cmd, 5);
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rrb = r100->radeon.state.depth.rrb;
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rrb = radeon_get_depthbuffer(&r100->radeon);
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if (!rrb) {
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OUT_BATCH(0);
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OUT_BATCH(0);
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} else {
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zbpitch = (rrb->pitch / rrb->cpp);
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if (r100->using_hyperz)
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zbpitch |= RADEON_DEPTH_HYPERZ;
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OUT_BATCH_RELOC(0, rrb->bo, 0, 0, RADEON_GEM_DOMAIN_VRAM, 0);
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OUT_BATCH(zbpitch);
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if (rrb->cpp == 4)
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depth_fmt = RADEON_DEPTH_FORMAT_24BIT_INT_Z;
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else
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depth_fmt = RADEON_DEPTH_FORMAT_16BIT_INT_Z;
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atom->cmd[CTX_RB3D_ZSTENCILCNTL] &= ~RADEON_DEPTH_FORMAT_MASK;
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atom->cmd[CTX_RB3D_ZSTENCILCNTL] |= depth_fmt;
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}
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OUT_BATCH(atom->cmd[CTX_RB3D_ZSTENCILCNTL]);
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OUT_BATCH(atom->cmd[CTX_CMD_1]);
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OUT_BATCH(atom->cmd[CTX_PP_CNTL]);
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OUT_BATCH(atom->cmd[CTX_RB3D_CNTL]);
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rrb = r100->radeon.state.color.rrb;
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if (r100->radeon.radeonScreen->driScreen->dri2.enabled) {
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rrb = (struct radeon_renderbuffer *)fb->Attachment[BUFFER_BACK_LEFT].Renderbuffer;
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}
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rrb = radeon_get_colorbuffer(&r100->radeon);
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if (!rrb || !rrb->bo) {
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OUT_BATCH(atom->cmd[CTX_RB3D_COLOROFFSET]);
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OUT_BATCH(atom->cmd[CTX_RB3D_CNTL]);
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OUT_BATCH(atom->cmd[CTX_RB3D_COLOROFFSET]);
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} else {
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OUT_BATCH_RELOC(0, rrb->bo, 0, 0, RADEON_GEM_DOMAIN_VRAM, 0);
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atom->cmd[CTX_RB3D_CNTL] &= ~(0xf << 10);
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if (rrb->cpp == 4)
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atom->cmd[CTX_RB3D_CNTL] |= RADEON_COLOR_FORMAT_ARGB8888;
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else
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atom->cmd[CTX_RB3D_CNTL] |= RADEON_COLOR_FORMAT_RGB565;
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OUT_BATCH(atom->cmd[CTX_RB3D_CNTL]);
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OUT_BATCH_RELOC(0, rrb->bo, 0, 0, RADEON_GEM_DOMAIN_VRAM, 0);
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}
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OUT_BATCH(atom->cmd[CTX_CMD_2]);
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@ -351,12 +363,8 @@ static void ctx_emit(GLcontext *ctx, struct radeon_state_atom *atom)
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OUT_BATCH(atom->cmd[CTX_RB3D_COLORPITCH]);
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} else {
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cbpitch = (rrb->pitch / rrb->cpp);
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if (rrb->cpp == 4)
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;
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else
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;
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if (r100->radeon.sarea->tiling_enabled)
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cbpitch |= R200_COLOR_TILE_ENABLE;
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if (rrb->bo->flags & RADEON_BO_FLAGS_MACRO_TILE)
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cbpitch |= RADEON_COLOR_TILE_ENABLE;
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OUT_BATCH(cbpitch);
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}
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@ -371,23 +379,35 @@ static void ctx_emit_cs(GLcontext *ctx, struct radeon_state_atom *atom)
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uint32_t cbpitch = 0;
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uint32_t zbpitch = 0;
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uint32_t dwords = atom->cmd_size;
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GLframebuffer *fb = r100->radeon.dri.drawable->driverPrivate;
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uint32_t depth_fmt;
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rrb = r100->radeon.state.color.rrb;
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if (r100->radeon.radeonScreen->driScreen->dri2.enabled) {
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rrb = (struct radeon_renderbuffer *)fb->Attachment[BUFFER_BACK_LEFT].Renderbuffer;
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rrb = radeon_get_colorbuffer(&r100->radeon);
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if (!rrb || !rrb->bo) {
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fprintf(stderr, "no rrb\n");
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return;
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}
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if (rrb) {
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assert(rrb->bo != NULL);
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cbpitch = (rrb->pitch / rrb->cpp);
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if (r100->radeon.sarea->tiling_enabled)
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atom->cmd[CTX_RB3D_CNTL] &= ~(0xf << 10);
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if (rrb->cpp == 4)
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atom->cmd[CTX_RB3D_CNTL] |= RADEON_COLOR_FORMAT_ARGB8888;
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else
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atom->cmd[CTX_RB3D_CNTL] |= RADEON_COLOR_FORMAT_RGB565;
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cbpitch = (rrb->pitch / rrb->cpp);
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if (rrb->bo->flags & RADEON_BO_FLAGS_MACRO_TILE)
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cbpitch |= R200_COLOR_TILE_ENABLE;
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}
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drb = r100->radeon.state.depth.rrb;
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if (drb)
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drb = radeon_get_depthbuffer(&r100->radeon);
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if (drb) {
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zbpitch = (drb->pitch / drb->cpp);
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if (drb->cpp == 4)
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depth_fmt = RADEON_DEPTH_FORMAT_24BIT_INT_Z;
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else
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depth_fmt = RADEON_DEPTH_FORMAT_16BIT_INT_Z;
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atom->cmd[CTX_RB3D_ZSTENCILCNTL] &= ~RADEON_DEPTH_FORMAT_MASK;
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atom->cmd[CTX_RB3D_ZSTENCILCNTL] |= depth_fmt;
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}
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/* output the first 7 bytes of context */
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BEGIN_BATCH_NO_AUTOSTATE(dwords);
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@ -416,10 +436,7 @@ static void ctx_emit_cs(GLcontext *ctx, struct radeon_state_atom *atom)
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}
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if (rrb) {
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if (rrb->cpp == 4)
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;
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else
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;
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cbpitch = (rrb->pitch / rrb->cpp);
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OUT_BATCH(CP_PACKET0(RADEON_RB3D_COLORPITCH, 0));
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OUT_BATCH(cbpitch);
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}
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@ -497,20 +514,7 @@ static void tex_emit(GLcontext *ctx, struct radeon_state_atom *atom)
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void radeonInitState( r100ContextPtr rmesa )
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{
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GLcontext *ctx = rmesa->radeon.glCtx;
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GLuint color_fmt, depth_fmt, i;
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GLint drawPitch, drawOffset;
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switch ( rmesa->radeon.radeonScreen->cpp ) {
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case 2:
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color_fmt = RADEON_COLOR_FORMAT_RGB565;
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break;
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case 4:
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color_fmt = RADEON_COLOR_FORMAT_ARGB8888;
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break;
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default:
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fprintf( stderr, "Error: Unsupported pixel depth... exiting\n" );
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exit( -1 );
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}
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GLuint i;
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rmesa->radeon.state.color.clear = 0x00000000;
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@ -518,13 +522,11 @@ void radeonInitState( r100ContextPtr rmesa )
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case 16:
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rmesa->radeon.state.depth.clear = 0x0000ffff;
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rmesa->radeon.state.depth.scale = 1.0 / (GLfloat)0xffff;
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depth_fmt = RADEON_DEPTH_FORMAT_16BIT_INT_Z;
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rmesa->radeon.state.stencil.clear = 0x00000000;
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break;
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case 24:
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rmesa->radeon.state.depth.clear = 0x00ffffff;
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rmesa->radeon.state.depth.scale = 1.0 / (GLfloat)0xffffff;
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depth_fmt = RADEON_DEPTH_FORMAT_24BIT_INT_Z;
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rmesa->radeon.state.stencil.clear = 0xffff0000;
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break;
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default:
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@ -539,13 +541,6 @@ void radeonInitState( r100ContextPtr rmesa )
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rmesa->radeon.Fallback = 0;
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if ( ctx->Visual.doubleBufferMode && rmesa->radeon.sarea->pfCurrentPage == 0 ) {
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drawOffset = rmesa->radeon.radeonScreen->backOffset;
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drawPitch = rmesa->radeon.radeonScreen->backPitch;
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} else {
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drawOffset = rmesa->radeon.radeonScreen->frontOffset;
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drawPitch = rmesa->radeon.radeonScreen->frontPitch;
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}
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rmesa->radeon.hw.max_state_size = 0;
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@ -708,19 +703,7 @@ void radeonInitState( r100ContextPtr rmesa )
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RADEON_SRC_BLEND_GL_ONE |
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RADEON_DST_BLEND_GL_ZERO );
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rmesa->hw.ctx.cmd[CTX_RB3D_DEPTHOFFSET] =
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rmesa->radeon.radeonScreen->depthOffset + rmesa->radeon.radeonScreen->fbLocation;
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rmesa->hw.ctx.cmd[CTX_RB3D_DEPTHPITCH] =
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((rmesa->radeon.radeonScreen->depthPitch &
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RADEON_DEPTHPITCH_MASK) |
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RADEON_DEPTH_ENDIAN_NO_SWAP);
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if (rmesa->using_hyperz)
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rmesa->hw.ctx.cmd[CTX_RB3D_DEPTHPITCH] |= RADEON_DEPTH_HYPERZ;
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rmesa->hw.ctx.cmd[CTX_RB3D_ZSTENCILCNTL] = (depth_fmt |
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RADEON_Z_TEST_LESS |
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rmesa->hw.ctx.cmd[CTX_RB3D_ZSTENCILCNTL] = (RADEON_Z_TEST_LESS |
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RADEON_STENCIL_TEST_ALWAYS |
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RADEON_STENCIL_FAIL_KEEP |
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RADEON_STENCIL_ZPASS_KEEP |
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@ -742,7 +725,6 @@ void radeonInitState( r100ContextPtr rmesa )
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RADEON_ANTI_ALIAS_NONE);
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rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] = (RADEON_PLANE_MASK_ENABLE |
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color_fmt |
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RADEON_ZBLOCK16);
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switch ( driQueryOptioni( &rmesa->radeon.optionCache, "dither_mode" ) ) {
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@ -764,19 +746,6 @@ void radeonInitState( r100ContextPtr rmesa )
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else
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rmesa->hw.ctx.cmd[CTX_RB3D_CNTL] |= rmesa->radeon.state.color.roundEnable;
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rmesa->hw.ctx.cmd[CTX_RB3D_COLOROFFSET] = ((drawOffset +
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rmesa->radeon.radeonScreen->fbLocation)
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& RADEON_COLOROFFSET_MASK);
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rmesa->hw.ctx.cmd[CTX_RB3D_COLORPITCH] = ((drawPitch &
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RADEON_COLORPITCH_MASK) |
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RADEON_COLOR_ENDIAN_NO_SWAP);
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/* (fixed size) sarea is initialized to zero afaics so can omit version check. Phew! */
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if (rmesa->radeon.sarea->tiling_enabled) {
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rmesa->hw.ctx.cmd[CTX_RB3D_COLORPITCH] |= RADEON_COLOR_TILE_ENABLE;
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}
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rmesa->hw.set.cmd[SET_SE_CNTL] = (RADEON_FFACE_CULL_CCW |
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RADEON_BFACE_SOLID |
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