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lima/ppir: fix alignment on regalloc spilling loads

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The spilling code spills entire vec4 registers regardless of the
components used by the spilled uses.
The inserted stores code force the 4 components, but these loads were
using a variable number of components, causing bugs on loading the
spilled registers.

Signed-off-by: Erico Nunes <nunes.erico@gmail.com>
Reviewed-by: Qiang Yu <yuq825@gmail.com>
This commit is contained in:
Erico Nunes 2019-07-22 00:55:24 +02:00
parent 9343c93e34
commit 9254059dd8
1 changed files with 1 additions and 1 deletions
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2
src/gallium/drivers/lima/ir/pp/regalloc.c
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@ -410,7 +410,7 @@ static ppir_alu_node* ppir_update_spilled_src(ppir_compiler *comp,
ppir_load_node *load = ppir_node_to_load(load_node);
load->index = -comp->prog->stack_size; /* index sizes are negative */
load->num_components = src->reg->num_components;
load->num_components = 4;
ppir_dest *ld_dest = &load->dest;
ld_dest->type = ppir_target_pipeline;